[RFC PATCH 0/3] PCI: generate proper configuration access cycles

[RFC PATCH 0/3] PCI: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found some pci hosts also have the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. Fix them by using the pci_generic_config_write.

Another problem is do we need to use proper readb/readw for config read?

Jisheng Zhang (3):
  PCI: iproc: generate proper configuration access cycles
  PCI: tegra: generate proper configuration access cycles
  PCI: xgene: generate proper configuration access cycles

 drivers/pci/host/pci-tegra.c  | 2 +-
 drivers/pci/host/pci-xgene.c  | 2 +-
 drivers/pci/host/pcie-iproc.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

-- 
2.6.2

[RFC PATCH 0/3] PCI: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found some pci hosts also have the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. Fix them by using the pci_generic_config_write.

Another problem is do we need to use proper readb/readw for config read?

Jisheng Zhang (3):
  PCI: iproc: generate proper configuration access cycles
  PCI: tegra: generate proper configuration access cycles
  PCI: xgene: generate proper configuration access cycles

 drivers/pci/host/pci-tegra.c  | 2 +-
 drivers/pci/host/pci-xgene.c  | 2 +-
 drivers/pci/host/pcie-iproc.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

-- 
2.6.2

[RFC PATCH 0/3] PCI: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found some pci hosts also have the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. Fix them by using the pci_generic_config_write.

Another problem is do we need to use proper readb/readw for config read?

Jisheng Zhang (3):
  PCI: iproc: generate proper configuration access cycles
  PCI: tegra: generate proper configuration access cycles
  PCI: xgene: generate proper configuration access cycles

 drivers/pci/host/pci-tegra.c  | 2 +-
 drivers/pci/host/pci-xgene.c  | 2 +-
 drivers/pci/host/pcie-iproc.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

-- 
2.6.2

[RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found current iproc also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. This patch fix this issue by using the pci_generic_config_write.

[1]http://www.spinics.net/lists/linux-pci/msg44869.html

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pcie-iproc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
index fe2efb1..0c423f2 100644
--- a/drivers/pci/host/pcie-iproc.c
+++ b/drivers/pci/host/pcie-iproc.c
@@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
 static struct pci_ops iproc_pcie_ops = {
 	.map_bus = iproc_pcie_map_cfg_bus,
 	.read = pci_generic_config_read32,
-	.write = pci_generic_config_write32,
+	.write = pci_generic_config_write,
 };
 
 static void iproc_pcie_reset(struct iproc_pcie *pcie)
-- 
2.6.2

[RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found current iproc also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. This patch fix this issue by using the pci_generic_config_write.

[1]http://www.spinics.net/lists/linux-pci/msg44869.html

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pcie-iproc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
index fe2efb1..0c423f2 100644
--- a/drivers/pci/host/pcie-iproc.c
+++ b/drivers/pci/host/pcie-iproc.c
@@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
 static struct pci_ops iproc_pcie_ops = {
 	.map_bus = iproc_pcie_map_cfg_bus,
 	.read = pci_generic_config_read32,
-	.write = pci_generic_config_write32,
+	.write = pci_generic_config_write,
 };
 
 static void iproc_pcie_reset(struct iproc_pcie *pcie)
-- 
2.6.2

[RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found current iproc also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. This patch fix this issue by using the pci_generic_config_write.

[1]http://www.spinics.net/lists/linux-pci/msg44869.html

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pcie-iproc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
index fe2efb1..0c423f2 100644
--- a/drivers/pci/host/pcie-iproc.c
+++ b/drivers/pci/host/pcie-iproc.c
@@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
 static struct pci_ops iproc_pcie_ops = {
 	.map_bus = iproc_pcie_map_cfg_bus,
 	.read = pci_generic_config_read32,
-	.write = pci_generic_config_write32,
+	.write = pci_generic_config_write,
 };
 
 static void iproc_pcie_reset(struct iproc_pcie *pcie)
-- 
2.6.2

Re: [RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Ray Jui]

Hi Jisheng,

On 10/26/2015 4:02 AM, Jisheng Zhang wrote:
> Inspired by Russell King's patch[1], I found current iproc also has the
> same issue of "reading 32-bits from the command register, modifying the
> command register, and then writing it back has the effect of clearing
> any status bits that were indicating at that time" as pointed out by
> Russell. This patch fix this issue by using the pci_generic_config_write.
>
> [1]http://www.spinics.net/lists/linux-pci/msg44869.html
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> ---
>   drivers/pci/host/pcie-iproc.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
> index fe2efb1..0c423f2 100644
> --- a/drivers/pci/host/pcie-iproc.c
> +++ b/drivers/pci/host/pcie-iproc.c
> @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
>   static struct pci_ops iproc_pcie_ops = {
>   	.map_bus = iproc_pcie_map_cfg_bus,
>   	.read = pci_generic_config_read32,
> -	.write = pci_generic_config_write32,
> +	.write = pci_generic_config_write,
>   };
>
>   static void iproc_pcie_reset(struct iproc_pcie *pcie)
>

I have already confirmed with the ASIC team that the current iProc PCIe 
controller requires 32-bit aligned access into the configuration space 
due to the way how it was integrated into various iProc SoCs including 
NSP, Cygnus, and NS2.

This change will prevent the driver from working properly.

I've informed our ASIC team about this issue and all future iProc based 
SoCs should be able to support 8-bit, 16-bit access and therefore 
pci_generic_config_write/read can be used for those SoCs.

Thanks,

Ray

[RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Ray Jui]

Hi Jisheng,

On 10/26/2015 4:02 AM, Jisheng Zhang wrote:
> Inspired by Russell King's patch[1], I found current iproc also has the
> same issue of "reading 32-bits from the command register, modifying the
> command register, and then writing it back has the effect of clearing
> any status bits that were indicating at that time" as pointed out by
> Russell. This patch fix this issue by using the pci_generic_config_write.
>
> [1]http://www.spinics.net/lists/linux-pci/msg44869.html
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> ---
>   drivers/pci/host/pcie-iproc.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
> index fe2efb1..0c423f2 100644
> --- a/drivers/pci/host/pcie-iproc.c
> +++ b/drivers/pci/host/pcie-iproc.c
> @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
>   static struct pci_ops iproc_pcie_ops = {
>   	.map_bus = iproc_pcie_map_cfg_bus,
>   	.read = pci_generic_config_read32,
> -	.write = pci_generic_config_write32,
> +	.write = pci_generic_config_write,
>   };
>
>   static void iproc_pcie_reset(struct iproc_pcie *pcie)
>

I have already confirmed with the ASIC team that the current iProc PCIe 
controller requires 32-bit aligned access into the configuration space 
due to the way how it was integrated into various iProc SoCs including 
NSP, Cygnus, and NS2.

This change will prevent the driver from working properly.

I've informed our ASIC team about this issue and all future iProc based 
SoCs should be able to support 8-bit, 16-bit access and therefore 
pci_generic_config_write/read can be used for those SoCs.

Thanks,

Ray

Re: [RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Ray Jui]

Hi Jisheng,

On 10/26/2015 4:02 AM, Jisheng Zhang wrote:
> Inspired by Russell King's patch[1], I found current iproc also has the
> same issue of "reading 32-bits from the command register, modifying the
> command register, and then writing it back has the effect of clearing
> any status bits that were indicating at that time" as pointed out by
> Russell. This patch fix this issue by using the pci_generic_config_write.
>
> [1]http://www.spinics.net/lists/linux-pci/msg44869.html
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> ---
>   drivers/pci/host/pcie-iproc.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
> index fe2efb1..0c423f2 100644
> --- a/drivers/pci/host/pcie-iproc.c
> +++ b/drivers/pci/host/pcie-iproc.c
> @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
>   static struct pci_ops iproc_pcie_ops = {
>   	.map_bus = iproc_pcie_map_cfg_bus,
>   	.read = pci_generic_config_read32,
> -	.write = pci_generic_config_write32,
> +	.write = pci_generic_config_write,
>   };
>
>   static void iproc_pcie_reset(struct iproc_pcie *pcie)
>

I have already confirmed with the ASIC team that the current iProc PCIe 
controller requires 32-bit aligned access into the configuration space 
due to the way how it was integrated into various iProc SoCs including 
NSP, Cygnus, and NS2.

This change will prevent the driver from working properly.

I've informed our ASIC team about this issue and all future iProc based 
SoCs should be able to support 8-bit, 16-bit access and therefore 
pci_generic_config_write/read can be used for those SoCs.

Thanks,

Ray

Re: [RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Jisheng Zhang]

On Mon, 26 Oct 2015 10:18:14 -0700
Ray Jui <rjui@broadcom.com> wrote:

> Hi Jisheng,
> 
> On 10/26/2015 4:02 AM, Jisheng Zhang wrote:
> > Inspired by Russell King's patch[1], I found current iproc also has the
> > same issue of "reading 32-bits from the command register, modifying the
> > command register, and then writing it back has the effect of clearing
> > any status bits that were indicating at that time" as pointed out by
> > Russell. This patch fix this issue by using the pci_generic_config_write.
> >
> > [1]http://www.spinics.net/lists/linux-pci/msg44869.html
> >
> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> > ---
> >   drivers/pci/host/pcie-iproc.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
> > index fe2efb1..0c423f2 100644
> > --- a/drivers/pci/host/pcie-iproc.c
> > +++ b/drivers/pci/host/pcie-iproc.c
> > @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
> >   static struct pci_ops iproc_pcie_ops = {
> >   	.map_bus = iproc_pcie_map_cfg_bus,
> >   	.read = pci_generic_config_read32,
> > -	.write = pci_generic_config_write32,
> > +	.write = pci_generic_config_write,
> >   };
> >
> >   static void iproc_pcie_reset(struct iproc_pcie *pcie)
> >  
> 
> I have already confirmed with the ASIC team that the current iProc PCIe 
> controller requires 32-bit aligned access into the configuration space 
> due to the way how it was integrated into various iProc SoCs including 
> NSP, Cygnus, and NS2.
> 
> This change will prevent the driver from working properly.
> 
> I've informed our ASIC team about this issue and all future iProc based 
> SoCs should be able to support 8-bit, 16-bit access and therefore 
> pci_generic_config_write/read can be used for those SoCs.
> 
> Thanks,
> 
> Ray

Got it. 

Thanks for the information,
Jisheng

[RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Jisheng Zhang]

On Mon, 26 Oct 2015 10:18:14 -0700
Ray Jui <rjui@broadcom.com> wrote:

> Hi Jisheng,
> 
> On 10/26/2015 4:02 AM, Jisheng Zhang wrote:
> > Inspired by Russell King's patch[1], I found current iproc also has the
> > same issue of "reading 32-bits from the command register, modifying the
> > command register, and then writing it back has the effect of clearing
> > any status bits that were indicating at that time" as pointed out by
> > Russell. This patch fix this issue by using the pci_generic_config_write.
> >
> > [1]http://www.spinics.net/lists/linux-pci/msg44869.html
> >
> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> > ---
> >   drivers/pci/host/pcie-iproc.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
> > index fe2efb1..0c423f2 100644
> > --- a/drivers/pci/host/pcie-iproc.c
> > +++ b/drivers/pci/host/pcie-iproc.c
> > @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
> >   static struct pci_ops iproc_pcie_ops = {
> >   	.map_bus = iproc_pcie_map_cfg_bus,
> >   	.read = pci_generic_config_read32,
> > -	.write = pci_generic_config_write32,
> > +	.write = pci_generic_config_write,
> >   };
> >
> >   static void iproc_pcie_reset(struct iproc_pcie *pcie)
> >  
> 
> I have already confirmed with the ASIC team that the current iProc PCIe 
> controller requires 32-bit aligned access into the configuration space 
> due to the way how it was integrated into various iProc SoCs including 
> NSP, Cygnus, and NS2.
> 
> This change will prevent the driver from working properly.
> 
> I've informed our ASIC team about this issue and all future iProc based 
> SoCs should be able to support 8-bit, 16-bit access and therefore 
> pci_generic_config_write/read can be used for those SoCs.
> 
> Thanks,
> 
> Ray

Got it. 

Thanks for the information,
Jisheng

Re: [RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Jisheng Zhang]

On Mon, 26 Oct 2015 10:18:14 -0700
Ray Jui <rjui@broadcom.com> wrote:

> Hi Jisheng,
> 
> On 10/26/2015 4:02 AM, Jisheng Zhang wrote:
> > Inspired by Russell King's patch[1], I found current iproc also has the
> > same issue of "reading 32-bits from the command register, modifying the
> > command register, and then writing it back has the effect of clearing
> > any status bits that were indicating at that time" as pointed out by
> > Russell. This patch fix this issue by using the pci_generic_config_write.
> >
> > [1]http://www.spinics.net/lists/linux-pci/msg44869.html
> >
> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> > ---
> >   drivers/pci/host/pcie-iproc.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
> > index fe2efb1..0c423f2 100644
> > --- a/drivers/pci/host/pcie-iproc.c
> > +++ b/drivers/pci/host/pcie-iproc.c
> > @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
> >   static struct pci_ops iproc_pcie_ops = {
> >   	.map_bus = iproc_pcie_map_cfg_bus,
> >   	.read = pci_generic_config_read32,
> > -	.write = pci_generic_config_write32,
> > +	.write = pci_generic_config_write,
> >   };
> >
> >   static void iproc_pcie_reset(struct iproc_pcie *pcie)
> >  
> 
> I have already confirmed with the ASIC team that the current iProc PCIe 
> controller requires 32-bit aligned access into the configuration space 
> due to the way how it was integrated into various iProc SoCs including 
> NSP, Cygnus, and NS2.
> 
> This change will prevent the driver from working properly.
> 
> I've informed our ASIC team about this issue and all future iProc based 
> SoCs should be able to support 8-bit, 16-bit access and therefore 
> pci_generic_config_write/read can be used for those SoCs.
> 
> Thanks,
> 
> Ray

Got it. 

Thanks for the information,
Jisheng

Re: [RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Arnd Bergmann]

On Tuesday 27 October 2015 10:18:20 Jisheng Zhang wrote:
> On Mon, 26 Oct 2015 10:18:14 -0700 Ray Jui <rjui@broadcom.com> wrote:
> 
> > Hi Jisheng,
> > 
> > On 10/26/2015 4:02 AM, Jisheng Zhang wrote:
> > > Inspired by Russell King's patch[1], I found current iproc also has the
> > > same issue of "reading 32-bits from the command register, modifying the
> > > command register, and then writing it back has the effect of clearing
> > > any status bits that were indicating at that time" as pointed out by
> > > Russell. This patch fix this issue by using the pci_generic_config_write.
> > >
> > > [1]http://www.spinics.net/lists/linux-pci/msg44869.html
> > >
> > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> > > ---
> > >   drivers/pci/host/pcie-iproc.c | 2 +-
> > >   1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
> > > index fe2efb1..0c423f2 100644
> > > --- a/drivers/pci/host/pcie-iproc.c
> > > +++ b/drivers/pci/host/pcie-iproc.c
> > > @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
> > >   static struct pci_ops iproc_pcie_ops = {
> > >     .map_bus = iproc_pcie_map_cfg_bus,
> > >     .read = pci_generic_config_read32,
> > > -   .write = pci_generic_config_write32,
> > > +   .write = pci_generic_config_write,
> > >   };
> > >
> > >   static void iproc_pcie_reset(struct iproc_pcie *pcie)
> > >  
> > 
> > I have already confirmed with the ASIC team that the current iProc PCIe 
> > controller requires 32-bit aligned access into the configuration space 
> > due to the way how it was integrated into various iProc SoCs including 
> > NSP, Cygnus, and NS2.
> > 
> > This change will prevent the driver from working properly.
> > 
> > I've informed our ASIC team about this issue and all future iProc based 
> > SoCs should be able to support 8-bit, 16-bit access and therefore 
> > pci_generic_config_write/read can be used for those SoCs.
>
> Thanks for the information,

We discussed the same issue when the X-gene PCI host driver was first
reviewed, and someone from APM then clarified that it had the same bug.

However, I don't know the details about the Tegra implementation, or
whether the X-Gene bug has been fixed in a newer version of the parts,
so we need to get confirmation from the respective developers before
applying any of the patches. If X-gene has been fixed in the meantime,
we need to make sure we match on the exact product numbers in the
compatible property so we only do it for the newer ones.

	Arnd

[RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles

[Arnd Bergmann]

On Tuesday 27 October 2015 10:18:20 Jisheng Zhang wrote:
> On Mon, 26 Oct 2015 10:18:14 -0700 Ray Jui <rjui@broadcom.com> wrote:
> 
> > Hi Jisheng,
> > 
> > On 10/26/2015 4:02 AM, Jisheng Zhang wrote:
> > > Inspired by Russell King's patch[1], I found current iproc also has the
> > > same issue of "reading 32-bits from the command register, modifying the
> > > command register, and then writing it back has the effect of clearing
> > > any status bits that were indicating at that time" as pointed out by
> > > Russell. This patch fix this issue by using the pci_generic_config_write.
> > >
> > > [1]http://www.spinics.net/lists/linux-pci/msg44869.html
> > >
> > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> > > ---
> > >   drivers/pci/host/pcie-iproc.c | 2 +-
> > >   1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
> > > index fe2efb1..0c423f2 100644
> > > --- a/drivers/pci/host/pcie-iproc.c
> > > +++ b/drivers/pci/host/pcie-iproc.c
> > > @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
> > >   static struct pci_ops iproc_pcie_ops = {
> > >     .map_bus = iproc_pcie_map_cfg_bus,
> > >     .read = pci_generic_config_read32,
> > > -   .write = pci_generic_config_write32,
> > > +   .write = pci_generic_config_write,
> > >   };
> > >
> > >   static void iproc_pcie_reset(struct iproc_pcie *pcie)
> > >  
> > 
> > I have already confirmed with the ASIC team that the current iProc PCIe 
> > controller requires 32-bit aligned access into the configuration space 
> > due to the way how it was integrated into various iProc SoCs including 
> > NSP, Cygnus, and NS2.
> > 
> > This change will prevent the driver from working properly.
> > 
> > I've informed our ASIC team about this issue and all future iProc based 
> > SoCs should be able to support 8-bit, 16-bit access and therefore 
> > pci_generic_config_write/read can be used for those SoCs.
>
> Thanks for the information,

We discussed the same issue when the X-gene PCI host driver was first
reviewed, and someone from APM then clarified that it had the same bug.

However, I don't know the details about the Tegra implementation, or
whether the X-Gene bug has been fixed in a newer version of the parts,
so we need to get confirmation from the respective developers before
applying any of the patches. If X-gene has been fixed in the meantime,
we need to make sure we match on the exact product numbers in the
compatible property so we only do it for the newer ones.

	Arnd

[RFC PATCH 2/3] PCI: tegra: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found current tegra also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. This patch fix this issue by using the pci_generic_config_write.

[1]http://www.spinics.net/lists/linux-pci/msg44869.html

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 81df0c1..d926e3e 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -483,7 +483,7 @@ static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus,
 static struct pci_ops tegra_pcie_ops = {
 	.map_bus = tegra_pcie_conf_address,
 	.read = pci_generic_config_read32,
-	.write = pci_generic_config_write32,
+	.write = pci_generic_config_write,
 };
 
 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
-- 
2.6.2

[RFC PATCH 2/3] PCI: tegra: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found current tegra also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. This patch fix this issue by using the pci_generic_config_write.

[1]http://www.spinics.net/lists/linux-pci/msg44869.html

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 81df0c1..d926e3e 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -483,7 +483,7 @@ static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus,
 static struct pci_ops tegra_pcie_ops = {
 	.map_bus = tegra_pcie_conf_address,
 	.read = pci_generic_config_read32,
-	.write = pci_generic_config_write32,
+	.write = pci_generic_config_write,
 };
 
 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
-- 
2.6.2

[RFC PATCH 2/3] PCI: tegra: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found current tegra also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. This patch fix this issue by using the pci_generic_config_write.

[1]http://www.spinics.net/lists/linux-pci/msg44869.html

Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
---
 drivers/pci/host/pci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 81df0c1..d926e3e 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -483,7 +483,7 @@ static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus,
 static struct pci_ops tegra_pcie_ops = {
 	.map_bus = tegra_pcie_conf_address,
 	.read = pci_generic_config_read32,
-	.write = pci_generic_config_write32,
+	.write = pci_generic_config_write,
 };
 
 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
-- 
2.6.2

[RFC PATCH 3/3] PCI: xgene: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found current tegra also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. This patch fix this issue by using the pci_generic_config_write.

[1]http://www.spinics.net/lists/linux-pci/msg44869.html

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pci-xgene.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index 0236ab9..8946a6c 100644
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -176,7 +176,7 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
 static struct pci_ops xgene_pcie_ops = {
 	.map_bus = xgene_pcie_map_bus,
 	.read = xgene_pcie_config_read32,
-	.write = pci_generic_config_write32,
+	.write = pci_generic_config_write,
 };
 
 static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
-- 
2.6.2

[RFC PATCH 3/3] PCI: xgene: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found current tegra also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. This patch fix this issue by using the pci_generic_config_write.

[1]http://www.spinics.net/lists/linux-pci/msg44869.html

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pci-xgene.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index 0236ab9..8946a6c 100644
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -176,7 +176,7 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
 static struct pci_ops xgene_pcie_ops = {
 	.map_bus = xgene_pcie_map_bus,
 	.read = xgene_pcie_config_read32,
-	.write = pci_generic_config_write32,
+	.write = pci_generic_config_write,
 };
 
 static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
-- 
2.6.2

[RFC PATCH 3/3] PCI: xgene: generate proper configuration access cycles

[Jisheng Zhang]

Inspired by Russell King's patch[1], I found current tegra also has the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. This patch fix this issue by using the pci_generic_config_write.

[1]http://www.spinics.net/lists/linux-pci/msg44869.html

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/pci/host/pci-xgene.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index 0236ab9..8946a6c 100644
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -176,7 +176,7 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
 static struct pci_ops xgene_pcie_ops = {
 	.map_bus = xgene_pcie_map_bus,
 	.read = xgene_pcie_config_read32,
-	.write = pci_generic_config_write32,
+	.write = pci_generic_config_write,
 };
 
 static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
-- 
2.6.2