* [Qemu-devel] [PATCH v3 1/6] e1000: Cosmetic and alignment fixes
2015-10-28 15:31 [Qemu-devel] [PATCH v3 0/6] e1000: Various fixes and registers' implementation Leonid Bloch
@ 2015-10-28 15:31 ` Leonid Bloch
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 2/6] e1000: Trivial implementation of various MAC registers Leonid Bloch
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Leonid Bloch @ 2015-10-28 15:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Dmitry Fleytman, Jason Wang, Leonid Bloch, Shmulik Ladkani
This fixes some alignment and cosmetic issues. The changes are made
in order that the following patches in this series will look like
integral parts of the code surrounding them, while conforming to the
coding style. Although some changes in unrelated areas are also made.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
---
hw/net/e1000.c | 135 +++++++++++++++++++++++++++-------------------------
hw/net/e1000_regs.h | 2 +-
2 files changed, 71 insertions(+), 66 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index 09c9e9d..232edf1 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -41,20 +41,20 @@
#ifdef E1000_DEBUG
enum {
- DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
- DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
- DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
+ DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
+ DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
+ DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET,
};
-#define DBGBIT(x) (1<<DEBUG_##x)
+#define DBGBIT(x) (1<<DEBUG_##x)
static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
-#define DBGOUT(what, fmt, ...) do { \
+#define DBGOUT(what, fmt, ...) do { \
if (debugflags & DBGBIT(what)) \
fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
} while (0)
#else
-#define DBGOUT(what, fmt, ...) do {} while (0)
+#define DBGOUT(what, fmt, ...) do {} while (0)
#endif
#define IOPORT_SIZE 0x40
@@ -118,7 +118,7 @@ typedef struct E1000State_st {
} tx;
struct {
- uint32_t val_in; // shifted in from guest driver
+ uint32_t val_in; /* shifted in from guest driver */
uint16_t bitnum_in;
uint16_t bitnum_out;
uint16_t reading;
@@ -155,19 +155,19 @@ typedef struct E1000BaseClass {
#define E1000_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(E1000BaseClass, (obj), TYPE_E1000_BASE)
-#define defreg(x) x = (E1000_##x>>2)
+#define defreg(x) x = (E1000_##x>>2)
enum {
- defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
- defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
- defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
- defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
- defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
- defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
- defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
- defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
- defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
- defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
- defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV),
+ defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
+ defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
+ defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
+ defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
+ defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
+ defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
+ defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
+ defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
+ defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
+ defreg(RA), defreg(MTA), defreg(CRCERRS), defreg(VFTA),
+ defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV),
defreg(ITR),
};
@@ -226,12 +226,12 @@ enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) };
enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
static const char phy_regcap[0x20] = {
- [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
- [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
- [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
- [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
- [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
- [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R,
+ [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
+ [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
+ [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
+ [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
+ [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
+ [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R,
[PHY_AUTONEG_EXP] = PHY_R,
};
@@ -510,17 +510,17 @@ set_eecd(E1000State *s, int index, uint32_t val)
s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
- if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
- return;
- if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
- s->eecd_state.val_in = 0;
- s->eecd_state.bitnum_in = 0;
- s->eecd_state.bitnum_out = 0;
- s->eecd_state.reading = 0;
+ if (!(E1000_EECD_CS & val)) /* CS inactive; nothing to do */
+ return;
+ if (E1000_EECD_CS & (val ^ oldval)) { /* CS rise edge; reset state */
+ s->eecd_state.val_in = 0;
+ s->eecd_state.bitnum_in = 0;
+ s->eecd_state.bitnum_out = 0;
+ s->eecd_state.reading = 0;
}
- if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
+ if (!(E1000_EECD_SK & (val ^ oldval))) /* no clock edge */
return;
- if (!(E1000_EECD_SK & val)) { // falling edge
+ if (!(E1000_EECD_SK & val)) { /* falling edge */
s->eecd_state.bitnum_out++;
return;
}
@@ -621,11 +621,11 @@ xmit_seg(E1000State *s)
css = tp->ipcss;
DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
frames, tp->size, css);
- if (tp->ip) { // IPv4
+ if (tp->ip) { /* IPv4 */
stw_be_p(tp->data+css+2, tp->size - css);
stw_be_p(tp->data+css+4,
be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
- } else // IPv6
+ } else /* IPv6 */
stw_be_p(tp->data+css+4, tp->size - css);
css = tp->tucss;
len = tp->size - css;
@@ -634,8 +634,8 @@ xmit_seg(E1000State *s)
sofar = frames * tp->mss;
stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */
if (tp->paylen - sofar > tp->mss)
- tp->data[css + 13] &= ~9; // PSH, FIN
- } else // UDP
+ tp->data[css + 13] &= ~9; /* PSH, FIN */
+ } else /* UDP */
stw_be_p(tp->data+css+4, len);
if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
unsigned int phsum;
@@ -657,8 +657,10 @@ xmit_seg(E1000State *s)
memmove(tp->data, tp->data + 4, 8);
memcpy(tp->data + 8, tp->vlan_header, 4);
e1000_send_packet(s, tp->vlan, tp->size + 4);
- } else
+ } else {
e1000_send_packet(s, tp->data, tp->size);
+ }
+
s->mac_reg[TPT]++;
s->mac_reg[GPTC]++;
n = s->mac_reg[TOTL];
@@ -679,7 +681,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
struct e1000_tx *tp = &s->tx;
s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE);
- if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
+ if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
op = le32_to_cpu(xp->cmd_and_length);
tp->ipcss = xp->lower_setup.ip_fields.ipcss;
tp->ipcso = xp->lower_setup.ip_fields.ipcso;
@@ -694,7 +696,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
tp->tso_frames = 0;
- if (tp->tucso == 0) { // this is probably wrong
+ if (tp->tucso == 0) { /* this is probably wrong */
DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
}
@@ -718,7 +720,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
stw_be_p(tp->vlan_header + 2,
le16_to_cpu(dp->upper.fields.special));
}
-
+
addr = le64_to_cpu(dp->buffer_addr);
if (tp->tse && tp->cptse) {
msh = tp->hdr_len + tp->mss;
@@ -1206,20 +1208,22 @@ set_ims(E1000State *s, int index, uint32_t val)
set_ics(s, 0, 0);
}
-#define getreg(x) [x] = mac_readreg
+#define getreg(x) [x] = mac_readreg
static uint32_t (*macreg_readops[])(E1000State *, int) = {
- getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
- getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
- getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
- getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
- getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
- getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
- getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
- getreg(TADV), getreg(ITR),
-
- [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
- [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
- [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
+ getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
+ getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
+ getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
+ getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
+ getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
+ getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
+ getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
+ getreg(TADV), getreg(ITR),
+
+ [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
+ [GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4,
+ [TPT] = mac_read_clr4, [TPR] = mac_read_clr4,
+ [ICR] = mac_icr_read, [EECD] = get_eecd,
+ [EERD] = flash_eerd_read,
[CRCERRS ... MPC] = &mac_readreg,
[RA ... RA+31] = &mac_readreg,
[MTA ... MTA+127] = &mac_readreg,
@@ -1227,17 +1231,18 @@ static uint32_t (*macreg_readops[])(E1000State *, int) = {
};
enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
-#define putreg(x) [x] = mac_writereg
+#define putreg(x) [x] = mac_writereg
static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
- putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
- putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
- putreg(RDBAL), putreg(LEDCTL), putreg(VET),
- [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
- [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
- [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
- [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
- [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
- [RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
+ putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
+ putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
+ putreg(RDBAL), putreg(LEDCTL), putreg(VET),
+
+ [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
+ [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
+ [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
+ [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
+ [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
+ [RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
[ITR] = set_16bit,
[RA ... RA+31] = &mac_writereg,
[MTA ... MTA+127] = &mac_writereg,
diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h
index 60b96aa..afd81cc 100644
--- a/hw/net/e1000_regs.h
+++ b/hw/net/e1000_regs.h
@@ -158,7 +158,7 @@
#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
#define FEXTNVM_SW_CONFIG 0x0001
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
-#define E1000_PBS 0x01008 /* Packet Buffer Size */
+#define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
#define E1000_FLASH_UPDATES 1000
#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
--
2.4.3
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v3 2/6] e1000: Trivial implementation of various MAC registers
2015-10-28 15:31 [Qemu-devel] [PATCH v3 0/6] e1000: Various fixes and registers' implementation Leonid Bloch
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 1/6] e1000: Cosmetic and alignment fixes Leonid Bloch
@ 2015-10-28 15:31 ` Leonid Bloch
2015-10-29 3:04 ` Jason Wang
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 3/6] e1000: Fixing the received/transmitted packets' counters Leonid Bloch
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Leonid Bloch @ 2015-10-28 15:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Dmitry Fleytman, Jason Wang, Leonid Bloch, Shmulik Ladkani
These registers appear in Intel's specs, but were not implemented.
These registers are now implemented trivially, i.e. they are initiated
with zero values, and if they are RW, they can be written or read by the
driver, or read only if they are R (essentially retaining their zero
values). For these registers no other procedures are performed.
For the trivially implemented Diagnostic registers, a debug warning is
produced on read/write attempts.
The registers implemented here are:
Transmit:
RW: AIT
Management:
RW: WUC WUS IPAV IP6AT* IP4AT* FFLT* WUPM* FFMT* FFVT*
Diagnostic:
RW: RDFH RDFT RDFHS RDFTS RDFPC PBM* TDFH TDFT TDFHS
TDFTS TDFPC
Statistic:
RW: FCRUC
R: RNBC TSCTFC MGTPRC MGTPDC MGTPTC RFC RJC SCC ECOL
LATECOL MCC COLC DC TNCRS SEC CEXTERR RLEC XONRXC
XONTXC XOFFRXC XOFFTXC
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
---
hw/net/e1000.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++++++-
hw/net/e1000_regs.h | 6 ++
2 files changed, 157 insertions(+), 3 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index 232edf1..fa65e79 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -168,7 +168,17 @@ enum {
defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
defreg(RA), defreg(MTA), defreg(CRCERRS), defreg(VFTA),
defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV),
- defreg(ITR),
+ defreg(ITR), defreg(FCRUC), defreg(TDFH), defreg(TDFT),
+ defreg(TDFHS), defreg(TDFTS), defreg(TDFPC), defreg(RDFH),
+ defreg(RDFT), defreg(RDFHS), defreg(RDFTS), defreg(RDFPC),
+ defreg(IPAV), defreg(WUC), defreg(WUS), defreg(AIT),
+ defreg(IP6AT), defreg(IP4AT), defreg(FFLT), defreg(FFMT),
+ defreg(FFVT), defreg(WUPM), defreg(PBM), defreg(SCC),
+ defreg(ECOL), defreg(MCC), defreg(LATECOL), defreg(COLC),
+ defreg(DC), defreg(TNCRS), defreg(SEC), defreg(CEXTERR),
+ defreg(RLEC), defreg(XONRXC), defreg(XONTXC), defreg(XOFFRXC),
+ defreg(XOFFTXC), defreg(RFC), defreg(RJC), defreg(RNBC),
+ defreg(TSCTFC), defreg(MGTPRC), defreg(MGTPDC), defreg(MGTPTC)
};
static void
@@ -1116,6 +1126,48 @@ mac_readreg(E1000State *s, int index)
}
static uint32_t
+mac_readreg_prt(E1000State *s, int index)
+{
+ DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
+ "It is not fully implemented.\n", index<<2);
+ return s->mac_reg[index];
+}
+
+static uint32_t
+mac_low4_read(E1000State *s, int index)
+{
+ return s->mac_reg[index] & 0xf;
+}
+
+static uint32_t
+mac_low11_read(E1000State *s, int index)
+{
+ return s->mac_reg[index] & 0x7ff;
+}
+
+static uint32_t
+mac_low11_read_prt(E1000State *s, int index)
+{
+ DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
+ "It is not fully implemented.\n", index<<2);
+ return s->mac_reg[index] & 0x7ff;
+}
+
+static uint32_t
+mac_low13_read_prt(E1000State *s, int index)
+{
+ DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
+ "It is not fully implemented.\n", index<<2);
+ return s->mac_reg[index] & 0x1fff;
+}
+
+static uint32_t
+mac_low16_read(E1000State *s, int index)
+{
+ return s->mac_reg[index] & 0xffff;
+}
+
+static uint32_t
mac_icr_read(E1000State *s, int index)
{
uint32_t ret = s->mac_reg[ICR];
@@ -1159,6 +1211,14 @@ mac_writereg(E1000State *s, int index, uint32_t val)
}
static void
+mac_writereg_prt(E1000State *s, int index, uint32_t val)
+{
+ DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. "
+ "It is not fully implemented.\n", index<<2);
+ s->mac_reg[index] = val;
+}
+
+static void
set_rdt(E1000State *s, int index, uint32_t val)
{
s->mac_reg[index] = val & 0xffff;
@@ -1217,25 +1277,49 @@ static uint32_t (*macreg_readops[])(E1000State *, int) = {
getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
- getreg(TADV), getreg(ITR),
+ getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
+ getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
+ getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
+ getreg(TNCRS), getreg(SEC), getreg(CEXTERR), getreg(RLEC),
+ getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC),
+ getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC),
+ getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC),
[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
[GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4,
[TPT] = mac_read_clr4, [TPR] = mac_read_clr4,
[ICR] = mac_icr_read, [EECD] = get_eecd,
[EERD] = flash_eerd_read,
+ [RDFH] = mac_low13_read_prt, [RDFT] = mac_low13_read_prt,
+ [RDFHS] = mac_low13_read_prt, [RDFTS] = mac_low13_read_prt,
+ [RDFPC] = mac_low13_read_prt,
+ [TDFH] = mac_low11_read_prt, [TDFT] = mac_low11_read_prt,
+ [TDFHS] = mac_low13_read_prt, [TDFTS] = mac_low13_read_prt,
+ [TDFPC] = mac_low13_read_prt,
+ [AIT] = mac_low16_read,
[CRCERRS ... MPC] = &mac_readreg,
+ [IP6AT ... IP6AT+3] = &mac_readreg, [IP4AT ... IP4AT+6] = &mac_readreg,
+ [FFLT ... FFLT+6] = &mac_low11_read,
[RA ... RA+31] = &mac_readreg,
+ [WUPM ... WUPM+31] = &mac_readreg,
[MTA ... MTA+127] = &mac_readreg,
[VFTA ... VFTA+127] = &mac_readreg,
+ [FFMT ... FFMT+254] = &mac_low4_read,
+ [FFVT ... FFVT+254] = &mac_readreg,
+ [PBM ... PBM+16383] = &mac_readreg_prt,
};
enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
#define putreg(x) [x] = mac_writereg
+#define putPreg(x) [x] = mac_writereg_prt
static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
- putreg(RDBAL), putreg(LEDCTL), putreg(VET),
+ putreg(RDBAL), putreg(LEDCTL), putreg(VET), putreg(FCRUC),
+ putPreg(TDFH), putPreg(TDFT), putPreg(TDFHS), putPreg(TDFTS),
+ putPreg(TDFPC), putPreg(RDFH), putPreg(RDFT), putPreg(RDFHS),
+ putPreg(RDFTS), putPreg(RDFPC), putreg(IPAV), putreg(WUC),
+ putreg(WUS), putreg(AIT),
[TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
[TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
@@ -1244,9 +1328,14 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
[EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
[RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
[ITR] = set_16bit,
+ [IP6AT ... IP6AT+3] = &mac_writereg, [IP4AT ... IP4AT+6] = &mac_writereg,
+ [FFLT ... FFLT+6] = &mac_writereg,
[RA ... RA+31] = &mac_writereg,
+ [WUPM ... WUPM+31] = &mac_writereg,
[MTA ... MTA+127] = &mac_writereg,
[VFTA ... VFTA+127] = &mac_writereg,
+ [FFMT ... FFMT+254] = &mac_writereg, [FFVT ... FFVT+254] = &mac_writereg,
+ [PBM ... PBM+16383] = &mac_writereg_prt,
};
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
@@ -1390,6 +1479,64 @@ static const VMStateDescription vmstate_e1000_mit_state = {
}
};
+static bool e1000_extra_trivial_regs_needed(void *opaque)
+{
+ return true;
+}
+
+static const VMStateDescription vmstate_e1000_extra_trivial_regs = {
+ .name = "e1000/extra_trivial_regs",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = e1000_extra_trivial_regs_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(mac_reg[AIT], E1000State),
+ VMSTATE_UINT32(mac_reg[SCC], E1000State),
+ VMSTATE_UINT32(mac_reg[ECOL], E1000State),
+ VMSTATE_UINT32(mac_reg[MCC], E1000State),
+ VMSTATE_UINT32(mac_reg[LATECOL], E1000State),
+ VMSTATE_UINT32(mac_reg[COLC], E1000State),
+ VMSTATE_UINT32(mac_reg[DC], E1000State),
+ VMSTATE_UINT32(mac_reg[TNCRS], E1000State),
+ VMSTATE_UINT32(mac_reg[SEC], E1000State),
+ VMSTATE_UINT32(mac_reg[CEXTERR], E1000State),
+ VMSTATE_UINT32(mac_reg[RLEC], E1000State),
+ VMSTATE_UINT32(mac_reg[XONRXC], E1000State),
+ VMSTATE_UINT32(mac_reg[XONTXC], E1000State),
+ VMSTATE_UINT32(mac_reg[XOFFRXC], E1000State),
+ VMSTATE_UINT32(mac_reg[XOFFTXC], E1000State),
+ VMSTATE_UINT32(mac_reg[FCRUC], E1000State),
+ VMSTATE_UINT32(mac_reg[RNBC], E1000State),
+ VMSTATE_UINT32(mac_reg[RFC], E1000State),
+ VMSTATE_UINT32(mac_reg[RJC], E1000State),
+ VMSTATE_UINT32(mac_reg[MGTPRC], E1000State),
+ VMSTATE_UINT32(mac_reg[MGTPDC], E1000State),
+ VMSTATE_UINT32(mac_reg[MGTPTC], E1000State),
+ VMSTATE_UINT32(mac_reg[TSCTFC], E1000State),
+ VMSTATE_UINT32(mac_reg[WUC], E1000State),
+ VMSTATE_UINT32(mac_reg[WUS], E1000State),
+ VMSTATE_UINT32(mac_reg[IPAV], E1000State),
+ VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP4AT, 7),
+ VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP6AT, 4),
+ VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, WUPM, 32),
+ VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFLT, 7),
+ VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFMT, 255),
+ VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFVT, 255),
+ VMSTATE_UINT32(mac_reg[RDFH], E1000State),
+ VMSTATE_UINT32(mac_reg[RDFT], E1000State),
+ VMSTATE_UINT32(mac_reg[RDFHS], E1000State),
+ VMSTATE_UINT32(mac_reg[RDFTS], E1000State),
+ VMSTATE_UINT32(mac_reg[RDFPC], E1000State),
+ VMSTATE_UINT32(mac_reg[TDFH], E1000State),
+ VMSTATE_UINT32(mac_reg[TDFT], E1000State),
+ VMSTATE_UINT32(mac_reg[TDFHS], E1000State),
+ VMSTATE_UINT32(mac_reg[TDFTS], E1000State),
+ VMSTATE_UINT32(mac_reg[TDFPC], E1000State),
+ VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, PBM, 16384),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_e1000 = {
.name = "e1000",
.version_id = 2,
@@ -1469,6 +1616,7 @@ static const VMStateDescription vmstate_e1000 = {
},
.subsections = (const VMStateDescription*[]) {
&vmstate_e1000_mit_state,
+ &vmstate_e1000_extra_trivial_regs,
NULL
}
};
diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h
index afd81cc..1c40244 100644
--- a/hw/net/e1000_regs.h
+++ b/hw/net/e1000_regs.h
@@ -158,6 +158,7 @@
#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
#define FEXTNVM_SW_CONFIG 0x0001
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
+#define E1000_PBM 0x10000 /* Packet Buffer Memory - RW */
#define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
#define E1000_FLASH_UPDATES 1000
@@ -191,6 +192,11 @@
#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
+#define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */
+#define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */
+#define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */
+#define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */
+#define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */
#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
--
2.4.3
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v3 2/6] e1000: Trivial implementation of various MAC registers
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 2/6] e1000: Trivial implementation of various MAC registers Leonid Bloch
@ 2015-10-29 3:04 ` Jason Wang
2015-10-29 9:33 ` Leonid Bloch
0 siblings, 1 reply; 12+ messages in thread
From: Jason Wang @ 2015-10-29 3:04 UTC (permalink / raw)
To: Leonid Bloch, qemu-devel; +Cc: Dmitry Fleytman, Leonid Bloch, Shmulik Ladkani
On 10/28/2015 11:31 PM, Leonid Bloch wrote:
> These registers appear in Intel's specs, but were not implemented.
> These registers are now implemented trivially, i.e. they are initiated
> with zero values, and if they are RW, they can be written or read by the
> driver, or read only if they are R (essentially retaining their zero
> values). For these registers no other procedures are performed.
>
> For the trivially implemented Diagnostic registers, a debug warning is
> produced on read/write attempts.
>
> The registers implemented here are:
>
> Transmit:
> RW: AIT
>
> Management:
> RW: WUC WUS IPAV IP6AT* IP4AT* FFLT* WUPM* FFMT* FFVT*
>
> Diagnostic:
> RW: RDFH RDFT RDFHS RDFTS RDFPC PBM* TDFH TDFT TDFHS
> TDFTS TDFPC
>
> Statistic:
> RW: FCRUC
> R: RNBC TSCTFC MGTPRC MGTPDC MGTPTC RFC RJC SCC ECOL
> LATECOL MCC COLC DC TNCRS SEC CEXTERR RLEC XONRXC
> XONTXC XOFFRXC XOFFTXC
>
> Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
> Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
> ---
> hw/net/e1000.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++++++-
> hw/net/e1000_regs.h | 6 ++
> 2 files changed, 157 insertions(+), 3 deletions(-)
>
> diff --git a/hw/net/e1000.c b/hw/net/e1000.c
> index 232edf1..fa65e79 100644
> --- a/hw/net/e1000.c
> +++ b/hw/net/e1000.c
> @@ -168,7 +168,17 @@ enum {
> defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
> defreg(RA), defreg(MTA), defreg(CRCERRS), defreg(VFTA),
> defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV),
> - defreg(ITR),
> + defreg(ITR), defreg(FCRUC), defreg(TDFH), defreg(TDFT),
> + defreg(TDFHS), defreg(TDFTS), defreg(TDFPC), defreg(RDFH),
> + defreg(RDFT), defreg(RDFHS), defreg(RDFTS), defreg(RDFPC),
> + defreg(IPAV), defreg(WUC), defreg(WUS), defreg(AIT),
> + defreg(IP6AT), defreg(IP4AT), defreg(FFLT), defreg(FFMT),
> + defreg(FFVT), defreg(WUPM), defreg(PBM), defreg(SCC),
> + defreg(ECOL), defreg(MCC), defreg(LATECOL), defreg(COLC),
> + defreg(DC), defreg(TNCRS), defreg(SEC), defreg(CEXTERR),
> + defreg(RLEC), defreg(XONRXC), defreg(XONTXC), defreg(XOFFRXC),
> + defreg(XOFFTXC), defreg(RFC), defreg(RJC), defreg(RNBC),
> + defreg(TSCTFC), defreg(MGTPRC), defreg(MGTPDC), defreg(MGTPTC)
> };
>
> static void
> @@ -1116,6 +1126,48 @@ mac_readreg(E1000State *s, int index)
> }
>
> static uint32_t
> +mac_readreg_prt(E1000State *s, int index)
> +{
> + DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
> + "It is not fully implemented.\n", index<<2);
> + return s->mac_reg[index];
> +}
> +
> +static uint32_t
> +mac_low4_read(E1000State *s, int index)
> +{
> + return s->mac_reg[index] & 0xf;
> +}
> +
> +static uint32_t
> +mac_low11_read(E1000State *s, int index)
> +{
> + return s->mac_reg[index] & 0x7ff;
> +}
> +
> +static uint32_t
> +mac_low11_read_prt(E1000State *s, int index)
> +{
> + DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
> + "It is not fully implemented.\n", index<<2);
> + return s->mac_reg[index] & 0x7ff;
> +}
> +
> +static uint32_t
> +mac_low13_read_prt(E1000State *s, int index)
> +{
> + DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
> + "It is not fully implemented.\n", index<<2);
> + return s->mac_reg[index] & 0x1fff;
> +}
> +
> +static uint32_t
> +mac_low16_read(E1000State *s, int index)
> +{
> + return s->mac_reg[index] & 0xffff;
> +}
> +
> +static uint32_t
> mac_icr_read(E1000State *s, int index)
> {
> uint32_t ret = s->mac_reg[ICR];
> @@ -1159,6 +1211,14 @@ mac_writereg(E1000State *s, int index, uint32_t val)
> }
>
> static void
> +mac_writereg_prt(E1000State *s, int index, uint32_t val)
> +{
> + DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. "
> + "It is not fully implemented.\n", index<<2);
> + s->mac_reg[index] = val;
> +}
> +
> +static void
> set_rdt(E1000State *s, int index, uint32_t val)
> {
> s->mac_reg[index] = val & 0xffff;
> @@ -1217,25 +1277,49 @@ static uint32_t (*macreg_readops[])(E1000State *, int) = {
> getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
> getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
> getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
> - getreg(TADV), getreg(ITR),
> + getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
> + getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
> + getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
> + getreg(TNCRS), getreg(SEC), getreg(CEXTERR), getreg(RLEC),
> + getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC),
> + getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC),
> + getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC),
>
> [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
> [GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4,
> [TPT] = mac_read_clr4, [TPR] = mac_read_clr4,
> [ICR] = mac_icr_read, [EECD] = get_eecd,
> [EERD] = flash_eerd_read,
> + [RDFH] = mac_low13_read_prt, [RDFT] = mac_low13_read_prt,
> + [RDFHS] = mac_low13_read_prt, [RDFTS] = mac_low13_read_prt,
> + [RDFPC] = mac_low13_read_prt,
> + [TDFH] = mac_low11_read_prt, [TDFT] = mac_low11_read_prt,
> + [TDFHS] = mac_low13_read_prt, [TDFTS] = mac_low13_read_prt,
> + [TDFPC] = mac_low13_read_prt,
> + [AIT] = mac_low16_read,
> [CRCERRS ... MPC] = &mac_readreg,
> + [IP6AT ... IP6AT+3] = &mac_readreg, [IP4AT ... IP4AT+6] = &mac_readreg,
> + [FFLT ... FFLT+6] = &mac_low11_read,
> [RA ... RA+31] = &mac_readreg,
> + [WUPM ... WUPM+31] = &mac_readreg,
> [MTA ... MTA+127] = &mac_readreg,
> [VFTA ... VFTA+127] = &mac_readreg,
> + [FFMT ... FFMT+254] = &mac_low4_read,
> + [FFVT ... FFVT+254] = &mac_readreg,
> + [PBM ... PBM+16383] = &mac_readreg_prt,
> };
> enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
>
> #define putreg(x) [x] = mac_writereg
> +#define putPreg(x) [x] = mac_writereg_prt
> static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
> putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
> putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
> - putreg(RDBAL), putreg(LEDCTL), putreg(VET),
> + putreg(RDBAL), putreg(LEDCTL), putreg(VET), putreg(FCRUC),
> + putPreg(TDFH), putPreg(TDFT), putPreg(TDFHS), putPreg(TDFTS),
> + putPreg(TDFPC), putPreg(RDFH), putPreg(RDFT), putPreg(RDFHS),
> + putPreg(RDFTS), putPreg(RDFPC), putreg(IPAV), putreg(WUC),
> + putreg(WUS), putreg(AIT),
>
> [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
> [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
> @@ -1244,9 +1328,14 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
> [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
> [RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
> [ITR] = set_16bit,
> + [IP6AT ... IP6AT+3] = &mac_writereg, [IP4AT ... IP4AT+6] = &mac_writereg,
> + [FFLT ... FFLT+6] = &mac_writereg,
> [RA ... RA+31] = &mac_writereg,
> + [WUPM ... WUPM+31] = &mac_writereg,
> [MTA ... MTA+127] = &mac_writereg,
> [VFTA ... VFTA+127] = &mac_writereg,
> + [FFMT ... FFMT+254] = &mac_writereg, [FFVT ... FFVT+254] = &mac_writereg,
> + [PBM ... PBM+16383] = &mac_writereg_prt,
> };
>
> enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
> @@ -1390,6 +1479,64 @@ static const VMStateDescription vmstate_e1000_mit_state = {
> }
> };
>
> +static bool e1000_extra_trivial_regs_needed(void *opaque)
> +{
> + return true;
> +}
This reminds me that we need care the migration compatibility to older
version here. Probably we need another property for e1000, and only
migrate and implement the new mac registers for version >= 2.5. An
example is mit implementation. (see
e9845f0985f088dd01790f4821026df0afba5795). And need to do the same for
patch 6.
> +
> +static const VMStateDescription vmstate_e1000_extra_trivial_regs = {
> + .name = "e1000/extra_trivial_regs",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .needed = e1000_extra_trivial_regs_needed,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(mac_reg[AIT], E1000State),
> + VMSTATE_UINT32(mac_reg[SCC], E1000State),
> + VMSTATE_UINT32(mac_reg[ECOL], E1000State),
> + VMSTATE_UINT32(mac_reg[MCC], E1000State),
> + VMSTATE_UINT32(mac_reg[LATECOL], E1000State),
> + VMSTATE_UINT32(mac_reg[COLC], E1000State),
> + VMSTATE_UINT32(mac_reg[DC], E1000State),
> + VMSTATE_UINT32(mac_reg[TNCRS], E1000State),
> + VMSTATE_UINT32(mac_reg[SEC], E1000State),
> + VMSTATE_UINT32(mac_reg[CEXTERR], E1000State),
> + VMSTATE_UINT32(mac_reg[RLEC], E1000State),
> + VMSTATE_UINT32(mac_reg[XONRXC], E1000State),
> + VMSTATE_UINT32(mac_reg[XONTXC], E1000State),
> + VMSTATE_UINT32(mac_reg[XOFFRXC], E1000State),
> + VMSTATE_UINT32(mac_reg[XOFFTXC], E1000State),
> + VMSTATE_UINT32(mac_reg[FCRUC], E1000State),
> + VMSTATE_UINT32(mac_reg[RNBC], E1000State),
> + VMSTATE_UINT32(mac_reg[RFC], E1000State),
> + VMSTATE_UINT32(mac_reg[RJC], E1000State),
> + VMSTATE_UINT32(mac_reg[MGTPRC], E1000State),
> + VMSTATE_UINT32(mac_reg[MGTPDC], E1000State),
> + VMSTATE_UINT32(mac_reg[MGTPTC], E1000State),
> + VMSTATE_UINT32(mac_reg[TSCTFC], E1000State),
> + VMSTATE_UINT32(mac_reg[WUC], E1000State),
> + VMSTATE_UINT32(mac_reg[WUS], E1000State),
> + VMSTATE_UINT32(mac_reg[IPAV], E1000State),
> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP4AT, 7),
> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP6AT, 4),
> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, WUPM, 32),
> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFLT, 7),
> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFMT, 255),
> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFVT, 255),
> + VMSTATE_UINT32(mac_reg[RDFH], E1000State),
> + VMSTATE_UINT32(mac_reg[RDFT], E1000State),
> + VMSTATE_UINT32(mac_reg[RDFHS], E1000State),
> + VMSTATE_UINT32(mac_reg[RDFTS], E1000State),
> + VMSTATE_UINT32(mac_reg[RDFPC], E1000State),
> + VMSTATE_UINT32(mac_reg[TDFH], E1000State),
> + VMSTATE_UINT32(mac_reg[TDFT], E1000State),
> + VMSTATE_UINT32(mac_reg[TDFHS], E1000State),
> + VMSTATE_UINT32(mac_reg[TDFTS], E1000State),
> + VMSTATE_UINT32(mac_reg[TDFPC], E1000State),
> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, PBM, 16384),
> + VMSTATE_END_OF_LIST()
> + }
> +};
I was considering a better approach here. Since we may want to add more
mac register implementation in the future, so we probably don't want to
add another subsections like this. How about just migrate mac_reg array
instead of specific registers here?
Thanks
> +
> static const VMStateDescription vmstate_e1000 = {
> .name = "e1000",
> .version_id = 2,
> @@ -1469,6 +1616,7 @@ static const VMStateDescription vmstate_e1000 = {
> },
> .subsections = (const VMStateDescription*[]) {
> &vmstate_e1000_mit_state,
> + &vmstate_e1000_extra_trivial_regs,
> NULL
> }
> };
> diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h
> index afd81cc..1c40244 100644
> --- a/hw/net/e1000_regs.h
> +++ b/hw/net/e1000_regs.h
> @@ -158,6 +158,7 @@
> #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
> #define FEXTNVM_SW_CONFIG 0x0001
> #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
> +#define E1000_PBM 0x10000 /* Packet Buffer Memory - RW */
> #define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
> #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
> #define E1000_FLASH_UPDATES 1000
> @@ -191,6 +192,11 @@
> #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
> #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
> #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
> +#define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */
> +#define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */
> +#define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */
> +#define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */
> +#define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */
> #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
> #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
> #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v3 2/6] e1000: Trivial implementation of various MAC registers
2015-10-29 3:04 ` Jason Wang
@ 2015-10-29 9:33 ` Leonid Bloch
2015-10-29 10:01 ` Jason Wang
0 siblings, 1 reply; 12+ messages in thread
From: Leonid Bloch @ 2015-10-29 9:33 UTC (permalink / raw)
To: Jason Wang; +Cc: Dmitry Fleytman, Leonid Bloch, qemu-devel, Shmulik Ladkani
On Thu, Oct 29, 2015 at 5:04 AM, Jason Wang <jasowang@redhat.com> wrote:
>
>
> On 10/28/2015 11:31 PM, Leonid Bloch wrote:
>> These registers appear in Intel's specs, but were not implemented.
>> These registers are now implemented trivially, i.e. they are initiated
>> with zero values, and if they are RW, they can be written or read by the
>> driver, or read only if they are R (essentially retaining their zero
>> values). For these registers no other procedures are performed.
>>
>> For the trivially implemented Diagnostic registers, a debug warning is
>> produced on read/write attempts.
>>
>> The registers implemented here are:
>>
>> Transmit:
>> RW: AIT
>>
>> Management:
>> RW: WUC WUS IPAV IP6AT* IP4AT* FFLT* WUPM* FFMT* FFVT*
>>
>> Diagnostic:
>> RW: RDFH RDFT RDFHS RDFTS RDFPC PBM* TDFH TDFT TDFHS
>> TDFTS TDFPC
>>
>> Statistic:
>> RW: FCRUC
>> R: RNBC TSCTFC MGTPRC MGTPDC MGTPTC RFC RJC SCC ECOL
>> LATECOL MCC COLC DC TNCRS SEC CEXTERR RLEC XONRXC
>> XONTXC XOFFRXC XOFFTXC
>>
>> Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
>> Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
>> ---
>> hw/net/e1000.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++++++-
>> hw/net/e1000_regs.h | 6 ++
>> 2 files changed, 157 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/net/e1000.c b/hw/net/e1000.c
>> index 232edf1..fa65e79 100644
>> --- a/hw/net/e1000.c
>> +++ b/hw/net/e1000.c
>> @@ -168,7 +168,17 @@ enum {
>> defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
>> defreg(RA), defreg(MTA), defreg(CRCERRS), defreg(VFTA),
>> defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV),
>> - defreg(ITR),
>> + defreg(ITR), defreg(FCRUC), defreg(TDFH), defreg(TDFT),
>> + defreg(TDFHS), defreg(TDFTS), defreg(TDFPC), defreg(RDFH),
>> + defreg(RDFT), defreg(RDFHS), defreg(RDFTS), defreg(RDFPC),
>> + defreg(IPAV), defreg(WUC), defreg(WUS), defreg(AIT),
>> + defreg(IP6AT), defreg(IP4AT), defreg(FFLT), defreg(FFMT),
>> + defreg(FFVT), defreg(WUPM), defreg(PBM), defreg(SCC),
>> + defreg(ECOL), defreg(MCC), defreg(LATECOL), defreg(COLC),
>> + defreg(DC), defreg(TNCRS), defreg(SEC), defreg(CEXTERR),
>> + defreg(RLEC), defreg(XONRXC), defreg(XONTXC), defreg(XOFFRXC),
>> + defreg(XOFFTXC), defreg(RFC), defreg(RJC), defreg(RNBC),
>> + defreg(TSCTFC), defreg(MGTPRC), defreg(MGTPDC), defreg(MGTPTC)
>> };
>>
>> static void
>> @@ -1116,6 +1126,48 @@ mac_readreg(E1000State *s, int index)
>> }
>>
>> static uint32_t
>> +mac_readreg_prt(E1000State *s, int index)
>> +{
>> + DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
>> + "It is not fully implemented.\n", index<<2);
>> + return s->mac_reg[index];
>> +}
>> +
>> +static uint32_t
>> +mac_low4_read(E1000State *s, int index)
>> +{
>> + return s->mac_reg[index] & 0xf;
>> +}
>> +
>> +static uint32_t
>> +mac_low11_read(E1000State *s, int index)
>> +{
>> + return s->mac_reg[index] & 0x7ff;
>> +}
>> +
>> +static uint32_t
>> +mac_low11_read_prt(E1000State *s, int index)
>> +{
>> + DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
>> + "It is not fully implemented.\n", index<<2);
>> + return s->mac_reg[index] & 0x7ff;
>> +}
>> +
>> +static uint32_t
>> +mac_low13_read_prt(E1000State *s, int index)
>> +{
>> + DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
>> + "It is not fully implemented.\n", index<<2);
>> + return s->mac_reg[index] & 0x1fff;
>> +}
>> +
>> +static uint32_t
>> +mac_low16_read(E1000State *s, int index)
>> +{
>> + return s->mac_reg[index] & 0xffff;
>> +}
>> +
>> +static uint32_t
>> mac_icr_read(E1000State *s, int index)
>> {
>> uint32_t ret = s->mac_reg[ICR];
>> @@ -1159,6 +1211,14 @@ mac_writereg(E1000State *s, int index, uint32_t val)
>> }
>>
>> static void
>> +mac_writereg_prt(E1000State *s, int index, uint32_t val)
>> +{
>> + DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. "
>> + "It is not fully implemented.\n", index<<2);
>> + s->mac_reg[index] = val;
>> +}
>> +
>> +static void
>> set_rdt(E1000State *s, int index, uint32_t val)
>> {
>> s->mac_reg[index] = val & 0xffff;
>> @@ -1217,25 +1277,49 @@ static uint32_t (*macreg_readops[])(E1000State *, int) = {
>> getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
>> getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
>> getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
>> - getreg(TADV), getreg(ITR),
>> + getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
>> + getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
>> + getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
>> + getreg(TNCRS), getreg(SEC), getreg(CEXTERR), getreg(RLEC),
>> + getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC),
>> + getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC),
>> + getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC),
>>
>> [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
>> [GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4,
>> [TPT] = mac_read_clr4, [TPR] = mac_read_clr4,
>> [ICR] = mac_icr_read, [EECD] = get_eecd,
>> [EERD] = flash_eerd_read,
>> + [RDFH] = mac_low13_read_prt, [RDFT] = mac_low13_read_prt,
>> + [RDFHS] = mac_low13_read_prt, [RDFTS] = mac_low13_read_prt,
>> + [RDFPC] = mac_low13_read_prt,
>> + [TDFH] = mac_low11_read_prt, [TDFT] = mac_low11_read_prt,
>> + [TDFHS] = mac_low13_read_prt, [TDFTS] = mac_low13_read_prt,
>> + [TDFPC] = mac_low13_read_prt,
>> + [AIT] = mac_low16_read,
>> [CRCERRS ... MPC] = &mac_readreg,
>> + [IP6AT ... IP6AT+3] = &mac_readreg, [IP4AT ... IP4AT+6] = &mac_readreg,
>> + [FFLT ... FFLT+6] = &mac_low11_read,
>> [RA ... RA+31] = &mac_readreg,
>> + [WUPM ... WUPM+31] = &mac_readreg,
>> [MTA ... MTA+127] = &mac_readreg,
>> [VFTA ... VFTA+127] = &mac_readreg,
>> + [FFMT ... FFMT+254] = &mac_low4_read,
>> + [FFVT ... FFVT+254] = &mac_readreg,
>> + [PBM ... PBM+16383] = &mac_readreg_prt,
>> };
>> enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
>>
>> #define putreg(x) [x] = mac_writereg
>> +#define putPreg(x) [x] = mac_writereg_prt
>> static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
>> putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
>> putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
>> - putreg(RDBAL), putreg(LEDCTL), putreg(VET),
>> + putreg(RDBAL), putreg(LEDCTL), putreg(VET), putreg(FCRUC),
>> + putPreg(TDFH), putPreg(TDFT), putPreg(TDFHS), putPreg(TDFTS),
>> + putPreg(TDFPC), putPreg(RDFH), putPreg(RDFT), putPreg(RDFHS),
>> + putPreg(RDFTS), putPreg(RDFPC), putreg(IPAV), putreg(WUC),
>> + putreg(WUS), putreg(AIT),
>>
>> [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
>> [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
>> @@ -1244,9 +1328,14 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
>> [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
>> [RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
>> [ITR] = set_16bit,
>> + [IP6AT ... IP6AT+3] = &mac_writereg, [IP4AT ... IP4AT+6] = &mac_writereg,
>> + [FFLT ... FFLT+6] = &mac_writereg,
>> [RA ... RA+31] = &mac_writereg,
>> + [WUPM ... WUPM+31] = &mac_writereg,
>> [MTA ... MTA+127] = &mac_writereg,
>> [VFTA ... VFTA+127] = &mac_writereg,
>> + [FFMT ... FFMT+254] = &mac_writereg, [FFVT ... FFVT+254] = &mac_writereg,
>> + [PBM ... PBM+16383] = &mac_writereg_prt,
>> };
>>
>> enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
>> @@ -1390,6 +1479,64 @@ static const VMStateDescription vmstate_e1000_mit_state = {
>> }
>> };
>>
>> +static bool e1000_extra_trivial_regs_needed(void *opaque)
>> +{
>> + return true;
>> +}
>
> This reminds me that we need care the migration compatibility to older
> version here. Probably we need another property for e1000, and only
> migrate and implement the new mac registers for version >= 2.5. An
> example is mit implementation. (see
> e9845f0985f088dd01790f4821026df0afba5795). And need to do the same for
> patch 6.
>
>> +
>> +static const VMStateDescription vmstate_e1000_extra_trivial_regs = {
>> + .name = "e1000/extra_trivial_regs",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .needed = e1000_extra_trivial_regs_needed,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT32(mac_reg[AIT], E1000State),
>> + VMSTATE_UINT32(mac_reg[SCC], E1000State),
>> + VMSTATE_UINT32(mac_reg[ECOL], E1000State),
>> + VMSTATE_UINT32(mac_reg[MCC], E1000State),
>> + VMSTATE_UINT32(mac_reg[LATECOL], E1000State),
>> + VMSTATE_UINT32(mac_reg[COLC], E1000State),
>> + VMSTATE_UINT32(mac_reg[DC], E1000State),
>> + VMSTATE_UINT32(mac_reg[TNCRS], E1000State),
>> + VMSTATE_UINT32(mac_reg[SEC], E1000State),
>> + VMSTATE_UINT32(mac_reg[CEXTERR], E1000State),
>> + VMSTATE_UINT32(mac_reg[RLEC], E1000State),
>> + VMSTATE_UINT32(mac_reg[XONRXC], E1000State),
>> + VMSTATE_UINT32(mac_reg[XONTXC], E1000State),
>> + VMSTATE_UINT32(mac_reg[XOFFRXC], E1000State),
>> + VMSTATE_UINT32(mac_reg[XOFFTXC], E1000State),
>> + VMSTATE_UINT32(mac_reg[FCRUC], E1000State),
>> + VMSTATE_UINT32(mac_reg[RNBC], E1000State),
>> + VMSTATE_UINT32(mac_reg[RFC], E1000State),
>> + VMSTATE_UINT32(mac_reg[RJC], E1000State),
>> + VMSTATE_UINT32(mac_reg[MGTPRC], E1000State),
>> + VMSTATE_UINT32(mac_reg[MGTPDC], E1000State),
>> + VMSTATE_UINT32(mac_reg[MGTPTC], E1000State),
>> + VMSTATE_UINT32(mac_reg[TSCTFC], E1000State),
>> + VMSTATE_UINT32(mac_reg[WUC], E1000State),
>> + VMSTATE_UINT32(mac_reg[WUS], E1000State),
>> + VMSTATE_UINT32(mac_reg[IPAV], E1000State),
>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP4AT, 7),
>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP6AT, 4),
>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, WUPM, 32),
>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFLT, 7),
>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFMT, 255),
>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFVT, 255),
>> + VMSTATE_UINT32(mac_reg[RDFH], E1000State),
>> + VMSTATE_UINT32(mac_reg[RDFT], E1000State),
>> + VMSTATE_UINT32(mac_reg[RDFHS], E1000State),
>> + VMSTATE_UINT32(mac_reg[RDFTS], E1000State),
>> + VMSTATE_UINT32(mac_reg[RDFPC], E1000State),
>> + VMSTATE_UINT32(mac_reg[TDFH], E1000State),
>> + VMSTATE_UINT32(mac_reg[TDFT], E1000State),
>> + VMSTATE_UINT32(mac_reg[TDFHS], E1000State),
>> + VMSTATE_UINT32(mac_reg[TDFTS], E1000State),
>> + VMSTATE_UINT32(mac_reg[TDFPC], E1000State),
>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, PBM, 16384),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>
> I was considering a better approach here. Since we may want to add more
> mac register implementation in the future, so we probably don't want to
> add another subsections like this. How about just migrate mac_reg array
> instead of specific registers here?
>
> Thanks
>
>> +
>> static const VMStateDescription vmstate_e1000 = {
>> .name = "e1000",
>> .version_id = 2,
>> @@ -1469,6 +1616,7 @@ static const VMStateDescription vmstate_e1000 = {
>> },
>> .subsections = (const VMStateDescription*[]) {
>> &vmstate_e1000_mit_state,
>> + &vmstate_e1000_extra_trivial_regs,
>> NULL
>> }
>> };
>> diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h
>> index afd81cc..1c40244 100644
>> --- a/hw/net/e1000_regs.h
>> +++ b/hw/net/e1000_regs.h
>> @@ -158,6 +158,7 @@
>> #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
>> #define FEXTNVM_SW_CONFIG 0x0001
>> #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
>> +#define E1000_PBM 0x10000 /* Packet Buffer Memory - RW */
>> #define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
>> #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
>> #define E1000_FLASH_UPDATES 1000
>> @@ -191,6 +192,11 @@
>> #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
>> #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
>> #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
>> +#define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */
>> +#define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */
>> +#define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */
>> +#define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */
>> +#define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */
>> #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
>> #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
>> #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
>
So you mean adding another boolean parameter, "full_mac_migration",
for instance, and if it is set - migrate the full mac_reg array,
otherwise - migrate just the registers that were previously
implemented?
Leonid.
__________
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v3 2/6] e1000: Trivial implementation of various MAC registers
2015-10-29 9:33 ` Leonid Bloch
@ 2015-10-29 10:01 ` Jason Wang
2015-10-29 10:27 ` Leonid Bloch
0 siblings, 1 reply; 12+ messages in thread
From: Jason Wang @ 2015-10-29 10:01 UTC (permalink / raw)
To: Leonid Bloch; +Cc: Dmitry Fleytman, Leonid Bloch, qemu-devel, Shmulik Ladkani
On 10/29/2015 05:33 PM, Leonid Bloch wrote:
> On Thu, Oct 29, 2015 at 5:04 AM, Jason Wang <jasowang@redhat.com> wrote:
>>
>> On 10/28/2015 11:31 PM, Leonid Bloch wrote:
>>> These registers appear in Intel's specs, but were not implemented.
>>> These registers are now implemented trivially, i.e. they are initiated
>>> with zero values, and if they are RW, they can be written or read by the
>>> driver, or read only if they are R (essentially retaining their zero
>>> values). For these registers no other procedures are performed.
>>>
>>> For the trivially implemented Diagnostic registers, a debug warning is
>>> produced on read/write attempts.
>>>
>>> The registers implemented here are:
>>>
>>> Transmit:
>>> RW: AIT
>>>
>>> Management:
>>> RW: WUC WUS IPAV IP6AT* IP4AT* FFLT* WUPM* FFMT* FFVT*
>>>
>>> Diagnostic:
>>> RW: RDFH RDFT RDFHS RDFTS RDFPC PBM* TDFH TDFT TDFHS
>>> TDFTS TDFPC
>>>
>>> Statistic:
>>> RW: FCRUC
>>> R: RNBC TSCTFC MGTPRC MGTPDC MGTPTC RFC RJC SCC ECOL
>>> LATECOL MCC COLC DC TNCRS SEC CEXTERR RLEC XONRXC
>>> XONTXC XOFFRXC XOFFTXC
>>>
>>> Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
>>> Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
>>> ---
>>> hw/net/e1000.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++++++-
>>> hw/net/e1000_regs.h | 6 ++
>>> 2 files changed, 157 insertions(+), 3 deletions(-)
[...]
>>>
>>> +static bool e1000_extra_trivial_regs_needed(void *opaque)
>>> +{
>>> + return true;
>>> +}
>> This reminds me that we need care the migration compatibility to older
>> version here. Probably we need another property for e1000, and only
>> migrate and implement the new mac registers for version >= 2.5. An
>> example is mit implementation. (see
>> e9845f0985f088dd01790f4821026df0afba5795). And need to do the same for
>> patch 6.
>>
>>> +
>>> +static const VMStateDescription vmstate_e1000_extra_trivial_regs = {
>>> + .name = "e1000/extra_trivial_regs",
>>> + .version_id = 1,
>>> + .minimum_version_id = 1,
>>> + .needed = e1000_extra_trivial_regs_needed,
>>> + .fields = (VMStateField[]) {
>>> + VMSTATE_UINT32(mac_reg[AIT], E1000State),
>>> + VMSTATE_UINT32(mac_reg[SCC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[ECOL], E1000State),
>>> + VMSTATE_UINT32(mac_reg[MCC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[LATECOL], E1000State),
>>> + VMSTATE_UINT32(mac_reg[COLC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[DC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[TNCRS], E1000State),
>>> + VMSTATE_UINT32(mac_reg[SEC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[CEXTERR], E1000State),
>>> + VMSTATE_UINT32(mac_reg[RLEC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[XONRXC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[XONTXC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[XOFFRXC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[XOFFTXC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[FCRUC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[RNBC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[RFC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[RJC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[MGTPRC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[MGTPDC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[MGTPTC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[TSCTFC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[WUC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[WUS], E1000State),
>>> + VMSTATE_UINT32(mac_reg[IPAV], E1000State),
>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP4AT, 7),
>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP6AT, 4),
>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, WUPM, 32),
>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFLT, 7),
>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFMT, 255),
>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFVT, 255),
>>> + VMSTATE_UINT32(mac_reg[RDFH], E1000State),
>>> + VMSTATE_UINT32(mac_reg[RDFT], E1000State),
>>> + VMSTATE_UINT32(mac_reg[RDFHS], E1000State),
>>> + VMSTATE_UINT32(mac_reg[RDFTS], E1000State),
>>> + VMSTATE_UINT32(mac_reg[RDFPC], E1000State),
>>> + VMSTATE_UINT32(mac_reg[TDFH], E1000State),
>>> + VMSTATE_UINT32(mac_reg[TDFT], E1000State),
>>> + VMSTATE_UINT32(mac_reg[TDFHS], E1000State),
>>> + VMSTATE_UINT32(mac_reg[TDFTS], E1000State),
>>> + VMSTATE_UINT32(mac_reg[TDFPC], E1000State),
>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, PBM, 16384),
>>> + VMSTATE_END_OF_LIST()
>>> + }
>>> +};
>> I was considering a better approach here. Since we may want to add more
>> mac register implementation in the future, so we probably don't want to
>> add another subsections like this. How about just migrate mac_reg array
>> instead of specific registers here?
>>
>> Thanks
>>
>>> +
>>> static const VMStateDescription vmstate_e1000 = {
>>> .name = "e1000",
>>> .version_id = 2,
>>> @@ -1469,6 +1616,7 @@ static const VMStateDescription vmstate_e1000 = {
>>> },
>>> .subsections = (const VMStateDescription*[]) {
>>> &vmstate_e1000_mit_state,
>>> + &vmstate_e1000_extra_trivial_regs,
>>> NULL
>>> }
>>> };
>>> diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h
>>> index afd81cc..1c40244 100644
>>> --- a/hw/net/e1000_regs.h
>>> +++ b/hw/net/e1000_regs.h
>>> @@ -158,6 +158,7 @@
>>> #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
>>> #define FEXTNVM_SW_CONFIG 0x0001
>>> #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
>>> +#define E1000_PBM 0x10000 /* Packet Buffer Memory - RW */
>>> #define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
>>> #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
>>> #define E1000_FLASH_UPDATES 1000
>>> @@ -191,6 +192,11 @@
>>> #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
>>> #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
>>> #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
>>> +#define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */
>>> +#define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */
>>> +#define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */
>>> +#define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */
>>> +#define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */
>>> #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
>>> #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
>>> #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
> So you mean adding another boolean parameter, "full_mac_migration",
> for instance, and if it is set - migrate the full mac_reg array,
> otherwise - migrate just the registers that were previously
> implemented?
>
> Leonid.
> __________
>
Something like this, but this parameter may also be used to decide
whether or not we should emulate the new mac registers, so maybe a
better name is needed and we it will imply to migrate full mac_reg
array. (Since patch 6 adds even more mac registers, maybe it's better to
squash that one into this?)
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v3 2/6] e1000: Trivial implementation of various MAC registers
2015-10-29 10:01 ` Jason Wang
@ 2015-10-29 10:27 ` Leonid Bloch
2015-10-30 3:22 ` Jason Wang
0 siblings, 1 reply; 12+ messages in thread
From: Leonid Bloch @ 2015-10-29 10:27 UTC (permalink / raw)
To: Jason Wang; +Cc: Dmitry Fleytman, Leonid Bloch, qemu-devel, Shmulik Ladkani
On Thu, Oct 29, 2015 at 12:01 PM, Jason Wang <jasowang@redhat.com> wrote:
>
>
> On 10/29/2015 05:33 PM, Leonid Bloch wrote:
>> On Thu, Oct 29, 2015 at 5:04 AM, Jason Wang <jasowang@redhat.com> wrote:
>>>
>>> On 10/28/2015 11:31 PM, Leonid Bloch wrote:
>>>> These registers appear in Intel's specs, but were not implemented.
>>>> These registers are now implemented trivially, i.e. they are initiated
>>>> with zero values, and if they are RW, they can be written or read by the
>>>> driver, or read only if they are R (essentially retaining their zero
>>>> values). For these registers no other procedures are performed.
>>>>
>>>> For the trivially implemented Diagnostic registers, a debug warning is
>>>> produced on read/write attempts.
>>>>
>>>> The registers implemented here are:
>>>>
>>>> Transmit:
>>>> RW: AIT
>>>>
>>>> Management:
>>>> RW: WUC WUS IPAV IP6AT* IP4AT* FFLT* WUPM* FFMT* FFVT*
>>>>
>>>> Diagnostic:
>>>> RW: RDFH RDFT RDFHS RDFTS RDFPC PBM* TDFH TDFT TDFHS
>>>> TDFTS TDFPC
>>>>
>>>> Statistic:
>>>> RW: FCRUC
>>>> R: RNBC TSCTFC MGTPRC MGTPDC MGTPTC RFC RJC SCC ECOL
>>>> LATECOL MCC COLC DC TNCRS SEC CEXTERR RLEC XONRXC
>>>> XONTXC XOFFRXC XOFFTXC
>>>>
>>>> Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
>>>> Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
>>>> ---
>>>> hw/net/e1000.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++++++-
>>>> hw/net/e1000_regs.h | 6 ++
>>>> 2 files changed, 157 insertions(+), 3 deletions(-)
>
> [...]
>
>>>>
>>>> +static bool e1000_extra_trivial_regs_needed(void *opaque)
>>>> +{
>>>> + return true;
>>>> +}
>>> This reminds me that we need care the migration compatibility to older
>>> version here. Probably we need another property for e1000, and only
>>> migrate and implement the new mac registers for version >= 2.5. An
>>> example is mit implementation. (see
>>> e9845f0985f088dd01790f4821026df0afba5795). And need to do the same for
>>> patch 6.
>>>
>>>> +
>>>> +static const VMStateDescription vmstate_e1000_extra_trivial_regs = {
>>>> + .name = "e1000/extra_trivial_regs",
>>>> + .version_id = 1,
>>>> + .minimum_version_id = 1,
>>>> + .needed = e1000_extra_trivial_regs_needed,
>>>> + .fields = (VMStateField[]) {
>>>> + VMSTATE_UINT32(mac_reg[AIT], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[SCC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[ECOL], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[MCC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[LATECOL], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[COLC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[DC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[TNCRS], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[SEC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[CEXTERR], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[RLEC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[XONRXC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[XONTXC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[XOFFRXC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[XOFFTXC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[FCRUC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[RNBC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[RFC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[RJC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[MGTPRC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[MGTPDC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[MGTPTC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[TSCTFC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[WUC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[WUS], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[IPAV], E1000State),
>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP4AT, 7),
>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP6AT, 4),
>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, WUPM, 32),
>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFLT, 7),
>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFMT, 255),
>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFVT, 255),
>>>> + VMSTATE_UINT32(mac_reg[RDFH], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[RDFT], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[RDFHS], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[RDFTS], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[RDFPC], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[TDFH], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[TDFT], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[TDFHS], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[TDFTS], E1000State),
>>>> + VMSTATE_UINT32(mac_reg[TDFPC], E1000State),
>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, PBM, 16384),
>>>> + VMSTATE_END_OF_LIST()
>>>> + }
>>>> +};
>>> I was considering a better approach here. Since we may want to add more
>>> mac register implementation in the future, so we probably don't want to
>>> add another subsections like this. How about just migrate mac_reg array
>>> instead of specific registers here?
>>>
>>> Thanks
>>>
>>>> +
>>>> static const VMStateDescription vmstate_e1000 = {
>>>> .name = "e1000",
>>>> .version_id = 2,
>>>> @@ -1469,6 +1616,7 @@ static const VMStateDescription vmstate_e1000 = {
>>>> },
>>>> .subsections = (const VMStateDescription*[]) {
>>>> &vmstate_e1000_mit_state,
>>>> + &vmstate_e1000_extra_trivial_regs,
>>>> NULL
>>>> }
>>>> };
>>>> diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h
>>>> index afd81cc..1c40244 100644
>>>> --- a/hw/net/e1000_regs.h
>>>> +++ b/hw/net/e1000_regs.h
>>>> @@ -158,6 +158,7 @@
>>>> #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
>>>> #define FEXTNVM_SW_CONFIG 0x0001
>>>> #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
>>>> +#define E1000_PBM 0x10000 /* Packet Buffer Memory - RW */
>>>> #define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
>>>> #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
>>>> #define E1000_FLASH_UPDATES 1000
>>>> @@ -191,6 +192,11 @@
>>>> #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
>>>> #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
>>>> #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
>>>> +#define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */
>>>> +#define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */
>>>> +#define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */
>>>> +#define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */
>>>> +#define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */
>>>> #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
>>>> #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
>>>> #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
>> So you mean adding another boolean parameter, "full_mac_migration",
>> for instance, and if it is set - migrate the full mac_reg array,
>> otherwise - migrate just the registers that were previously
>> implemented?
>>
>> Leonid.
>> __________
>>
>
> Something like this, but this parameter may also be used to decide
> whether or not we should emulate the new mac registers, so maybe a
> better name is needed and we it will imply to migrate full mac_reg
> array. (Since patch 6 adds even more mac registers, maybe it's better to
> squash that one into this?)
>
In such case, I'd add a patch #2, introducing this parameter, say
"extra_mac_registers", that at first will take care of the migration
of the entire mac_reg array, and in the consecutive patches, where new
registers are introduced, it will also control their implementation.
But: can you think of a use case where someone will start a Qemu VM
knowing ahead of time that migration to an older version may occur?
This seems highly unlikely to me, but more code will be needed for
this unlikely scenario, which will make it less understandable and
harder to maintain, IMHO.
Leonid.
_
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v3 2/6] e1000: Trivial implementation of various MAC registers
2015-10-29 10:27 ` Leonid Bloch
@ 2015-10-30 3:22 ` Jason Wang
0 siblings, 0 replies; 12+ messages in thread
From: Jason Wang @ 2015-10-30 3:22 UTC (permalink / raw)
To: Leonid Bloch; +Cc: Dmitry Fleytman, Leonid Bloch, qemu-devel, Shmulik Ladkani
On 10/29/2015 06:27 PM, Leonid Bloch wrote:
> On Thu, Oct 29, 2015 at 12:01 PM, Jason Wang <jasowang@redhat.com> wrote:
>>
>> On 10/29/2015 05:33 PM, Leonid Bloch wrote:
>>> On Thu, Oct 29, 2015 at 5:04 AM, Jason Wang <jasowang@redhat.com> wrote:
>>>> On 10/28/2015 11:31 PM, Leonid Bloch wrote:
>>>>> These registers appear in Intel's specs, but were not implemented.
>>>>> These registers are now implemented trivially, i.e. they are initiated
>>>>> with zero values, and if they are RW, they can be written or read by the
>>>>> driver, or read only if they are R (essentially retaining their zero
>>>>> values). For these registers no other procedures are performed.
>>>>>
>>>>> For the trivially implemented Diagnostic registers, a debug warning is
>>>>> produced on read/write attempts.
>>>>>
>>>>> The registers implemented here are:
>>>>>
>>>>> Transmit:
>>>>> RW: AIT
>>>>>
>>>>> Management:
>>>>> RW: WUC WUS IPAV IP6AT* IP4AT* FFLT* WUPM* FFMT* FFVT*
>>>>>
>>>>> Diagnostic:
>>>>> RW: RDFH RDFT RDFHS RDFTS RDFPC PBM* TDFH TDFT TDFHS
>>>>> TDFTS TDFPC
>>>>>
>>>>> Statistic:
>>>>> RW: FCRUC
>>>>> R: RNBC TSCTFC MGTPRC MGTPDC MGTPTC RFC RJC SCC ECOL
>>>>> LATECOL MCC COLC DC TNCRS SEC CEXTERR RLEC XONRXC
>>>>> XONTXC XOFFRXC XOFFTXC
>>>>>
>>>>> Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
>>>>> Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
>>>>> ---
>>>>> hw/net/e1000.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++++++-
>>>>> hw/net/e1000_regs.h | 6 ++
>>>>> 2 files changed, 157 insertions(+), 3 deletions(-)
>> [...]
>>
>>>>> +static bool e1000_extra_trivial_regs_needed(void *opaque)
>>>>> +{
>>>>> + return true;
>>>>> +}
>>>> This reminds me that we need care the migration compatibility to older
>>>> version here. Probably we need another property for e1000, and only
>>>> migrate and implement the new mac registers for version >= 2.5. An
>>>> example is mit implementation. (see
>>>> e9845f0985f088dd01790f4821026df0afba5795). And need to do the same for
>>>> patch 6.
>>>>
>>>>> +
>>>>> +static const VMStateDescription vmstate_e1000_extra_trivial_regs = {
>>>>> + .name = "e1000/extra_trivial_regs",
>>>>> + .version_id = 1,
>>>>> + .minimum_version_id = 1,
>>>>> + .needed = e1000_extra_trivial_regs_needed,
>>>>> + .fields = (VMStateField[]) {
>>>>> + VMSTATE_UINT32(mac_reg[AIT], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[SCC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[ECOL], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[MCC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[LATECOL], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[COLC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[DC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[TNCRS], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[SEC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[CEXTERR], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[RLEC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[XONRXC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[XONTXC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[XOFFRXC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[XOFFTXC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[FCRUC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[RNBC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[RFC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[RJC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[MGTPRC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[MGTPDC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[MGTPTC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[TSCTFC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[WUC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[WUS], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[IPAV], E1000State),
>>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP4AT, 7),
>>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, IP6AT, 4),
>>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, WUPM, 32),
>>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFLT, 7),
>>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFMT, 255),
>>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, FFVT, 255),
>>>>> + VMSTATE_UINT32(mac_reg[RDFH], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[RDFT], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[RDFHS], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[RDFTS], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[RDFPC], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[TDFH], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[TDFT], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[TDFHS], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[TDFTS], E1000State),
>>>>> + VMSTATE_UINT32(mac_reg[TDFPC], E1000State),
>>>>> + VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, PBM, 16384),
>>>>> + VMSTATE_END_OF_LIST()
>>>>> + }
>>>>> +};
>>>> I was considering a better approach here. Since we may want to add more
>>>> mac register implementation in the future, so we probably don't want to
>>>> add another subsections like this. How about just migrate mac_reg array
>>>> instead of specific registers here?
>>>>
>>>> Thanks
>>>>
>>>>> +
>>>>> static const VMStateDescription vmstate_e1000 = {
>>>>> .name = "e1000",
>>>>> .version_id = 2,
>>>>> @@ -1469,6 +1616,7 @@ static const VMStateDescription vmstate_e1000 = {
>>>>> },
>>>>> .subsections = (const VMStateDescription*[]) {
>>>>> &vmstate_e1000_mit_state,
>>>>> + &vmstate_e1000_extra_trivial_regs,
>>>>> NULL
>>>>> }
>>>>> };
>>>>> diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h
>>>>> index afd81cc..1c40244 100644
>>>>> --- a/hw/net/e1000_regs.h
>>>>> +++ b/hw/net/e1000_regs.h
>>>>> @@ -158,6 +158,7 @@
>>>>> #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
>>>>> #define FEXTNVM_SW_CONFIG 0x0001
>>>>> #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
>>>>> +#define E1000_PBM 0x10000 /* Packet Buffer Memory - RW */
>>>>> #define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
>>>>> #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
>>>>> #define E1000_FLASH_UPDATES 1000
>>>>> @@ -191,6 +192,11 @@
>>>>> #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
>>>>> #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
>>>>> #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
>>>>> +#define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */
>>>>> +#define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */
>>>>> +#define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */
>>>>> +#define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */
>>>>> +#define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */
>>>>> #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
>>>>> #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
>>>>> #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
>>> So you mean adding another boolean parameter, "full_mac_migration",
>>> for instance, and if it is set - migrate the full mac_reg array,
>>> otherwise - migrate just the registers that were previously
>>> implemented?
>>>
>>> Leonid.
>>> __________
>>>
>> Something like this, but this parameter may also be used to decide
>> whether or not we should emulate the new mac registers, so maybe a
>> better name is needed and we it will imply to migrate full mac_reg
>> array. (Since patch 6 adds even more mac registers, maybe it's better to
>> squash that one into this?)
>>
> In such case, I'd add a patch #2, introducing this parameter, say
> "extra_mac_registers", that at first will take care of the migration
> of the entire mac_reg array, and in the consecutive patches, where new
> registers are introduced, it will also control their implementation.
> But: can you think of a use case where someone will start a Qemu VM
> knowing ahead of time that migration to an older version may occur?
Yes. It's not rare in production environment. Consider some old machines
are running qemu 2.4, but some new ones are running qemu 2.5. If we want
to do migration between those machine for some reason (e.g load balance
or other), the only thing that can preserve guest ABI is using machine
type 2.4. So in this case, it's possible that we may migrate a VM from
2.5 (with machine type 2.4) to 2.4. We've made lots of effort for keep
compatibility in the past.
> This seems highly unlikely to me, but more code will be needed for
> this unlikely scenario, which will make it less understandable and
> harder to maintain, IMHO.
>
> Leonid.
> _
I agree the code may become more complex than just implementing the
function itself. But keeping migration works across different versions
are important for users or customers. For the case of e1000, it would be
better that all mac regs was migrated since first today. But for some
reason, it doesn't, and we couldn't change exist codes. So we need
handle this.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v3 3/6] e1000: Fixing the received/transmitted packets' counters
2015-10-28 15:31 [Qemu-devel] [PATCH v3 0/6] e1000: Various fixes and registers' implementation Leonid Bloch
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 1/6] e1000: Cosmetic and alignment fixes Leonid Bloch
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 2/6] e1000: Trivial implementation of various MAC registers Leonid Bloch
@ 2015-10-28 15:31 ` Leonid Bloch
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 4/6] e1000: Fixing the received/transmitted octets' counters Leonid Bloch
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Leonid Bloch @ 2015-10-28 15:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Dmitry Fleytman, Jason Wang, Leonid Bloch, Shmulik Ladkani
According to Intel's specs, these counters (as the other Statistic
registers) stick at 0xffffffff when this maximal value is reached.
Previously, they would reset after the max. value.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
---
hw/net/e1000.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index fa65e79..f55a3f6 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -575,6 +575,14 @@ putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
}
}
+static inline void
+inc_reg_if_not_full(E1000State *s, int index)
+{
+ if (s->mac_reg[index] != 0xffffffff) {
+ s->mac_reg[index]++;
+ }
+}
+
static inline int
vlan_enabled(E1000State *s)
{
@@ -671,8 +679,8 @@ xmit_seg(E1000State *s)
e1000_send_packet(s, tp->data, tp->size);
}
- s->mac_reg[TPT]++;
- s->mac_reg[GPTC]++;
+ inc_reg_if_not_full(s, TPT);
+ s->mac_reg[GPTC] = s->mac_reg[TPT];
n = s->mac_reg[TOTL];
if ((s->mac_reg[TOTL] += s->tx.size) < n)
s->mac_reg[TOTH]++;
@@ -1085,8 +1093,8 @@ e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
}
} while (desc_offset < total_size);
- s->mac_reg[GPRC]++;
- s->mac_reg[TPR]++;
+ inc_reg_if_not_full(s, TPR);
+ s->mac_reg[GPRC] = s->mac_reg[TPR];
/* TOR - Total Octets Received:
* This register includes bytes received in a packet from the <Destination
* Address> field through the <CRC> field, inclusively.
--
2.4.3
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v3 4/6] e1000: Fixing the received/transmitted octets' counters
2015-10-28 15:31 [Qemu-devel] [PATCH v3 0/6] e1000: Various fixes and registers' implementation Leonid Bloch
` (2 preceding siblings ...)
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 3/6] e1000: Fixing the received/transmitted packets' counters Leonid Bloch
@ 2015-10-28 15:31 ` Leonid Bloch
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 5/6] e1000: Fixing the packet address filtering procedure Leonid Bloch
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 6/6] e1000: Implementing various counters Leonid Bloch
5 siblings, 0 replies; 12+ messages in thread
From: Leonid Bloch @ 2015-10-28 15:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Dmitry Fleytman, Jason Wang, Leonid Bloch, Shmulik Ladkani
Previously, these 64-bit registers did not stick at their maximal
values when (and if) they reached them, as they should do, according to
the specs.
This patch introduces a function that takes care of such registers,
avoiding code duplication, making the relevant parts more compatible
with the QEMU coding style, while ensuring that in the unlikely case
of reaching the maximal value, the counter will stick there, as it
supposed to.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
---
hw/net/e1000.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index f55a3f6..57c2596 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -583,6 +583,20 @@ inc_reg_if_not_full(E1000State *s, int index)
}
}
+static void
+grow_8reg_if_not_full(E1000State *s, int index, int size)
+{
+ uint64_t sum = s->mac_reg[index] | (uint64_t)s->mac_reg[index+1] << 32;
+
+ if (sum + size < sum) {
+ sum = ~0ULL;
+ } else {
+ sum += size;
+ }
+ s->mac_reg[index] = sum;
+ s->mac_reg[index+1] = sum >> 32;
+}
+
static inline int
vlan_enabled(E1000State *s)
{
@@ -632,7 +646,7 @@ static void
xmit_seg(E1000State *s)
{
uint16_t len, *sp;
- unsigned int frames = s->tx.tso_frames, css, sofar, n;
+ unsigned int frames = s->tx.tso_frames, css, sofar;
struct e1000_tx *tp = &s->tx;
if (tp->tse && tp->cptse) {
@@ -680,10 +694,8 @@ xmit_seg(E1000State *s)
}
inc_reg_if_not_full(s, TPT);
+ grow_8reg_if_not_full(s, TOTL, s->tx.size);
s->mac_reg[GPTC] = s->mac_reg[TPT];
- n = s->mac_reg[TOTL];
- if ((s->mac_reg[TOTL] += s->tx.size) < n)
- s->mac_reg[TOTH]++;
}
static void
@@ -1098,11 +1110,9 @@ e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
/* TOR - Total Octets Received:
* This register includes bytes received in a packet from the <Destination
* Address> field through the <CRC> field, inclusively.
+ * Always include FCS length (4) in size.
*/
- n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
- if (n < s->mac_reg[TORL])
- s->mac_reg[TORH]++;
- s->mac_reg[TORL] = n;
+ grow_8reg_if_not_full(s, TORL, size+4);
n = E1000_ICS_RXT0;
if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
--
2.4.3
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v3 5/6] e1000: Fixing the packet address filtering procedure
2015-10-28 15:31 [Qemu-devel] [PATCH v3 0/6] e1000: Various fixes and registers' implementation Leonid Bloch
` (3 preceding siblings ...)
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 4/6] e1000: Fixing the received/transmitted octets' counters Leonid Bloch
@ 2015-10-28 15:31 ` Leonid Bloch
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 6/6] e1000: Implementing various counters Leonid Bloch
5 siblings, 0 replies; 12+ messages in thread
From: Leonid Bloch @ 2015-10-28 15:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Dmitry Fleytman, Jason Wang, Leonid Bloch, Shmulik Ladkani
Previously, if promiscuous unicast was enabled, a packet was received
straight away, even if it was a multicast or a broadcast packet. This
patch fixes that behavior, while making the filtering procedure a bit
more human-readable.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
---
hw/net/e1000.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index 57c2596..2f83a9e 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -866,6 +866,7 @@ receive_filter(E1000State *s, const uint8_t *buf, int size)
static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
static const int mta_shift[] = {4, 3, 2, 0};
uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
+ int isbcast = !memcmp(buf, bcast, sizeof bcast), ismcast = (buf[0] & 1);
if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
@@ -875,14 +876,17 @@ receive_filter(E1000State *s, const uint8_t *buf, int size)
return 0;
}
- if (rctl & E1000_RCTL_UPE) // promiscuous
+ if (!isbcast && !ismcast && (rctl & E1000_RCTL_UPE)) { /* promiscuous ucast */
return 1;
+ }
- if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
+ if (ismcast && (rctl & E1000_RCTL_MPE)) { /* promiscuous mcast */
return 1;
+ }
- if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
+ if (isbcast && (rctl & E1000_RCTL_BAM)) { /* broadcast enabled */
return 1;
+ }
for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
if (!(rp[1] & E1000_RAH_AV))
--
2.4.3
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v3 6/6] e1000: Implementing various counters
2015-10-28 15:31 [Qemu-devel] [PATCH v3 0/6] e1000: Various fixes and registers' implementation Leonid Bloch
` (4 preceding siblings ...)
2015-10-28 15:31 ` [Qemu-devel] [PATCH v3 5/6] e1000: Fixing the packet address filtering procedure Leonid Bloch
@ 2015-10-28 15:31 ` Leonid Bloch
5 siblings, 0 replies; 12+ messages in thread
From: Leonid Bloch @ 2015-10-28 15:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Dmitry Fleytman, Jason Wang, Leonid Bloch, Shmulik Ladkani
This implements the following Statistic registers (various counters)
according to Intel's specs:
TSCTC GOTCL GOTCH GORCL GORCH MPRC BPRC RUC ROC
BPTC MPTC PTC... PRC...
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
---
hw/net/e1000.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 112 insertions(+), 5 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index 2f83a9e..c24cd24 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -37,6 +37,8 @@
#include "e1000_regs.h"
+static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
#define E1000_DEBUG
#ifdef E1000_DEBUG
@@ -178,7 +180,13 @@ enum {
defreg(DC), defreg(TNCRS), defreg(SEC), defreg(CEXTERR),
defreg(RLEC), defreg(XONRXC), defreg(XONTXC), defreg(XOFFRXC),
defreg(XOFFTXC), defreg(RFC), defreg(RJC), defreg(RNBC),
- defreg(TSCTFC), defreg(MGTPRC), defreg(MGTPDC), defreg(MGTPTC)
+ defreg(TSCTFC), defreg(MGTPRC), defreg(MGTPDC), defreg(MGTPTC),
+ defreg(RUC), defreg(ROC), defreg(GORCL), defreg(GORCH),
+ defreg(GOTCL), defreg(GOTCH), defreg(BPRC), defreg(MPRC),
+ defreg(TSCTC), defreg(PRC64), defreg(PRC127), defreg(PRC255),
+ defreg(PRC511), defreg(PRC1023), defreg(PRC1522), defreg(PTC64),
+ defreg(PTC127), defreg(PTC255), defreg(PTC511), defreg(PTC1023),
+ defreg(PTC1522), defreg(MPTC), defreg(BPTC)
};
static void
@@ -583,6 +591,16 @@ inc_reg_if_not_full(E1000State *s, int index)
}
}
+static inline void
+inc_tx_bcast_or_mcast_count(E1000State *s, const unsigned char *arr)
+{
+ if (!memcmp(arr, bcast, sizeof bcast)) {
+ inc_reg_if_not_full(s, BPTC);
+ } else if (arr[0] & 1) {
+ inc_reg_if_not_full(s, MPTC);
+ }
+}
+
static void
grow_8reg_if_not_full(E1000State *s, int index, int size)
{
@@ -597,6 +615,24 @@ grow_8reg_if_not_full(E1000State *s, int index, int size)
s->mac_reg[index+1] = sum >> 32;
}
+static void
+increase_size_stats(E1000State *s, const int *size_regs, int size)
+{
+ if (size > 1023) {
+ inc_reg_if_not_full(s, size_regs[5]);
+ } else if (size > 511) {
+ inc_reg_if_not_full(s, size_regs[4]);
+ } else if (size > 255) {
+ inc_reg_if_not_full(s, size_regs[3]);
+ } else if (size > 127) {
+ inc_reg_if_not_full(s, size_regs[2]);
+ } else if (size > 64) {
+ inc_reg_if_not_full(s, size_regs[1]);
+ } else if (size == 64) {
+ inc_reg_if_not_full(s, size_regs[0]);
+ }
+}
+
static inline int
vlan_enabled(E1000State *s)
{
@@ -634,12 +670,17 @@ fcs_len(E1000State *s)
static void
e1000_send_packet(E1000State *s, const uint8_t *buf, int size)
{
+ static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
+ PTC1023, PTC1522 };
+
NetClientState *nc = qemu_get_queue(s->nic);
if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) {
nc->info->receive(nc, buf, size);
} else {
qemu_send_packet(nc, buf, size);
}
+ inc_tx_bcast_or_mcast_count(s, buf);
+ increase_size_stats(s, PTCregs, size);
}
static void
@@ -665,8 +706,11 @@ xmit_seg(E1000State *s)
if (tp->tcp) {
sofar = frames * tp->mss;
stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */
- if (tp->paylen - sofar > tp->mss)
+ if (tp->paylen - sofar > tp->mss) {
tp->data[css + 13] &= ~9; /* PSH, FIN */
+ } else if (frames) {
+ inc_reg_if_not_full(s, TSCTC);
+ }
} else /* UDP */
stw_be_p(tp->data+css+4, len);
if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
@@ -696,6 +740,8 @@ xmit_seg(E1000State *s)
inc_reg_if_not_full(s, TPT);
grow_8reg_if_not_full(s, TOTL, s->tx.size);
s->mac_reg[GPTC] = s->mac_reg[TPT];
+ s->mac_reg[GOTCL] = s->mac_reg[TOTL];
+ s->mac_reg[GOTCH] = s->mac_reg[TOTH];
}
static void
@@ -863,7 +909,6 @@ start_xmit(E1000State *s)
static int
receive_filter(E1000State *s, const uint8_t *buf, int size)
{
- static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
static const int mta_shift[] = {4, 3, 2, 0};
uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
int isbcast = !memcmp(buf, bcast, sizeof bcast), ismcast = (buf[0] & 1);
@@ -881,10 +926,12 @@ receive_filter(E1000State *s, const uint8_t *buf, int size)
}
if (ismcast && (rctl & E1000_RCTL_MPE)) { /* promiscuous mcast */
+ inc_reg_if_not_full(s, MPRC);
return 1;
}
if (isbcast && (rctl & E1000_RCTL_BAM)) { /* broadcast enabled */
+ inc_reg_if_not_full(s, BPRC);
return 1;
}
@@ -906,8 +953,10 @@ receive_filter(E1000State *s, const uint8_t *buf, int size)
f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
- if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
+ if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f))) {
+ inc_reg_if_not_full(s, MPRC);
return 1;
+ }
DBGOUT(RXFILTER,
"dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
@@ -996,6 +1045,8 @@ e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
size_t desc_offset;
size_t desc_size;
size_t total_size;
+ static const int PRCregs[6] = { PRC64, PRC127, PRC255, PRC511,
+ PRC1023, PRC1522 };
if (!(s->mac_reg[STATUS] & E1000_STATUS_LU)) {
return -1;
@@ -1009,6 +1060,7 @@ e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
if (size < sizeof(min_buf)) {
iov_to_buf(iov, iovcnt, 0, min_buf, size);
memset(&min_buf[size], 0, sizeof(min_buf) - size);
+ inc_reg_if_not_full(s, RUC);
min_iov.iov_base = filter_buf = min_buf;
min_iov.iov_len = size = sizeof(min_buf);
iovcnt = 1;
@@ -1024,6 +1076,7 @@ e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
(size > MAXIMUM_ETHERNET_VLAN_SIZE
&& !(s->mac_reg[RCTL] & E1000_RCTL_LPE)))
&& !(s->mac_reg[RCTL] & E1000_RCTL_SBP)) {
+ inc_reg_if_not_full(s, ROC);
return size;
}
@@ -1109,6 +1162,7 @@ e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
}
} while (desc_offset < total_size);
+ increase_size_stats(s, PRCregs, total_size);
inc_reg_if_not_full(s, TPR);
s->mac_reg[GPRC] = s->mac_reg[TPR];
/* TOR - Total Octets Received:
@@ -1117,6 +1171,8 @@ e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
* Always include FCS length (4) in size.
*/
grow_8reg_if_not_full(s, TORL, size+4);
+ s->mac_reg[GORCL] = s->mac_reg[TORL];
+ s->mac_reg[GORCH] = s->mac_reg[TORH];
n = E1000_ICS_RXT0;
if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
@@ -1305,11 +1361,23 @@ static uint32_t (*macreg_readops[])(E1000State *, int) = {
getreg(TNCRS), getreg(SEC), getreg(CEXTERR), getreg(RLEC),
getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC),
getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC),
- getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC),
+ getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC), getreg(GORCL),
+ getreg(GOTCL),
[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
+ [GOTCH] = mac_read_clr8, [GORCH] = mac_read_clr8,
+ [PRC64] = mac_read_clr4, [PRC127] = mac_read_clr4,
+ [PRC255] = mac_read_clr4, [PRC511] = mac_read_clr4,
+ [PRC1023] = mac_read_clr4, [PRC1522] = mac_read_clr4,
+ [PTC64] = mac_read_clr4, [PTC127] = mac_read_clr4,
+ [PTC255] = mac_read_clr4, [PTC511] = mac_read_clr4,
+ [PTC1023] = mac_read_clr4, [PTC1522] = mac_read_clr4,
[GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4,
[TPT] = mac_read_clr4, [TPR] = mac_read_clr4,
+ [RUC] = mac_read_clr4, [ROC] = mac_read_clr4,
+ [BPRC] = mac_read_clr4, [MPRC] = mac_read_clr4,
+ [TSCTC] = mac_read_clr4, [BPTC] = mac_read_clr4,
+ [MPTC] = mac_read_clr4,
[ICR] = mac_icr_read, [EECD] = get_eecd,
[EERD] = flash_eerd_read,
[RDFH] = mac_low13_read_prt, [RDFT] = mac_low13_read_prt,
@@ -1559,6 +1627,44 @@ static const VMStateDescription vmstate_e1000_extra_trivial_regs = {
}
};
+static bool e1000_extra_counters_needed(void *opaque)
+{
+ return true;
+}
+
+static const VMStateDescription vmstate_e1000_extra_counters = {
+ .name = "e1000/extra_counters",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = e1000_extra_counters_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(mac_reg[PRC64], E1000State),
+ VMSTATE_UINT32(mac_reg[PRC127], E1000State),
+ VMSTATE_UINT32(mac_reg[PRC255], E1000State),
+ VMSTATE_UINT32(mac_reg[PRC511], E1000State),
+ VMSTATE_UINT32(mac_reg[PRC1023], E1000State),
+ VMSTATE_UINT32(mac_reg[PRC1522], E1000State),
+ VMSTATE_UINT32(mac_reg[BPRC], E1000State),
+ VMSTATE_UINT32(mac_reg[MPRC], E1000State),
+ VMSTATE_UINT32(mac_reg[GORCL], E1000State),
+ VMSTATE_UINT32(mac_reg[GORCH], E1000State),
+ VMSTATE_UINT32(mac_reg[GOTCL], E1000State),
+ VMSTATE_UINT32(mac_reg[GOTCH], E1000State),
+ VMSTATE_UINT32(mac_reg[RUC], E1000State),
+ VMSTATE_UINT32(mac_reg[ROC], E1000State),
+ VMSTATE_UINT32(mac_reg[PTC64], E1000State),
+ VMSTATE_UINT32(mac_reg[PTC127], E1000State),
+ VMSTATE_UINT32(mac_reg[PTC255], E1000State),
+ VMSTATE_UINT32(mac_reg[PTC511], E1000State),
+ VMSTATE_UINT32(mac_reg[PTC1023], E1000State),
+ VMSTATE_UINT32(mac_reg[PTC1522], E1000State),
+ VMSTATE_UINT32(mac_reg[MPTC], E1000State),
+ VMSTATE_UINT32(mac_reg[BPTC], E1000State),
+ VMSTATE_UINT32(mac_reg[TSCTC], E1000State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_e1000 = {
.name = "e1000",
.version_id = 2,
@@ -1639,6 +1745,7 @@ static const VMStateDescription vmstate_e1000 = {
.subsections = (const VMStateDescription*[]) {
&vmstate_e1000_mit_state,
&vmstate_e1000_extra_trivial_regs,
+ &vmstate_e1000_extra_counters,
NULL
}
};
--
2.4.3
^ permalink raw reply related [flat|nested] 12+ messages in thread