From: Sergey Fedorov <serge.fdrv@gmail.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org
Subject: Re: [Qemu-arm] [PATCH 1/2] target-arm: Update condexec before CP access check in AA32 translation
Date: Tue, 17 Nov 2015 13:59:00 +0300 [thread overview]
Message-ID: <564B0874.3050902@gmail.com> (raw)
In-Reply-To: <1447702479-6997-2-git-send-email-serge.fdrv@gmail.com>
On 16.11.2015 22:34, Sergey Fedorov wrote:
> Coprocessor access instructions are allowed inside IT block.
> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
> bits should be updated before.
>
> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
> target-arm/translate.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 4351854..f1f8129 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
> break;
> }
>
> + gen_set_condexec(dc);
Ah, there must be gen_set_condexec(s).
> gen_set_pc_im(s, s->pc - 4);
> tmpptr = tcg_const_ptr(ri);
> tcg_syn = tcg_const_i32(syndrome);
WARNING: multiple messages have this Message-ID (diff)
From: Sergey Fedorov <serge.fdrv@gmail.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 1/2] target-arm: Update condexec before CP access check in AA32 translation
Date: Tue, 17 Nov 2015 13:59:00 +0300 [thread overview]
Message-ID: <564B0874.3050902@gmail.com> (raw)
In-Reply-To: <1447702479-6997-2-git-send-email-serge.fdrv@gmail.com>
On 16.11.2015 22:34, Sergey Fedorov wrote:
> Coprocessor access instructions are allowed inside IT block.
> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
> bits should be updated before.
>
> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
> target-arm/translate.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 4351854..f1f8129 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
> break;
> }
>
> + gen_set_condexec(dc);
Ah, there must be gen_set_condexec(s).
> gen_set_pc_im(s, s->pc - 4);
> tmpptr = tcg_const_ptr(ri);
> tcg_syn = tcg_const_i32(syndrome);
next prev parent reply other threads:[~2015-11-17 10:59 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-16 19:34 [Qemu-arm] [PATCH 0/2] target-arm: Missed gen_set_condexec() in AA32 translation Sergey Fedorov
2015-11-16 19:34 ` [Qemu-devel] " Sergey Fedorov
2015-11-16 19:34 ` [Qemu-devel] [PATCH 1/2] target-arm: Update condexec before CP access check " Sergey Fedorov
2015-11-17 10:59 ` Sergey Fedorov [this message]
2015-11-17 10:59 ` Sergey Fedorov
2015-11-17 13:31 ` [Qemu-arm] " Peter Maydell
2015-11-17 13:31 ` [Qemu-devel] " Peter Maydell
2015-11-17 13:38 ` [Qemu-arm] " Sergey Fedorov
2015-11-17 13:38 ` [Qemu-devel] " Sergey Fedorov
2015-11-16 19:34 ` [Qemu-devel] [PATCH 2/2] target-arm: Update condexec before arch BP " Sergey Fedorov
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