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From: Suzuki.Poulose@arm.com (Suzuki K. Poulose)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/5] arm64: cpufeature: Track unsigned fields
Date: Fri, 20 Nov 2015 13:37:00 +0000	[thread overview]
Message-ID: <564F21FC.1030306@arm.com> (raw)
In-Reply-To: <20151119184533.GB10823@e104818-lin.cambridge.arm.com>

On 19/11/15 18:45, Catalin Marinas wrote:
> On Thu, Nov 19, 2015 at 10:03:13AM +0000, Suzuki K. Poulose wrote:
>> On 19/11/15 04:57, AKASHI Takahiro wrote:


> a) A precise value (number of breakpoint registers) or a value from
>     which you derive some precise value. You mentioned these above
>
> b) Fields defining the presence of a feature (1, 2, 3). These would
>     always be positive since the absence of such feature would mean a
>     value of 0
>
> c) Fields defining the absence of a feature by setting 0xf. These are
>     usually fields that were initial RAZ and turned to -1. I don't expect
>     such field be greater than 0, nor smaller than -1.
>
> So I think we can treat (a) and (b) as unsigned permanently.

Agreed.

> We could treat (c) as unsigned as well with a value of 0xf though I'm not sure
> how it matches your LOWER/HIGHER_SAFE definitions.

I think we should treat (c) as signed, as we never know what could change,
given that meaning of (0xf - implies unsupported) < meaning of (0 - supported).
Treating them unsigned could break the LOWER/HIGHER_SAFE definitions and makes
the safe value selection ugly.

Cheers
Suzuki

WARNING: multiple messages have this Message-ID (diff)
From: "Suzuki K. Poulose" <Suzuki.Poulose@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>,
	linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com,
	will.deacon@arm.com, linux-kernel@vger.kernel.org,
	ard.biesheuvel@linaro.org
Subject: Re: [PATCH 2/5] arm64: cpufeature: Track unsigned fields
Date: Fri, 20 Nov 2015 13:37:00 +0000	[thread overview]
Message-ID: <564F21FC.1030306@arm.com> (raw)
In-Reply-To: <20151119184533.GB10823@e104818-lin.cambridge.arm.com>

On 19/11/15 18:45, Catalin Marinas wrote:
> On Thu, Nov 19, 2015 at 10:03:13AM +0000, Suzuki K. Poulose wrote:
>> On 19/11/15 04:57, AKASHI Takahiro wrote:


> a) A precise value (number of breakpoint registers) or a value from
>     which you derive some precise value. You mentioned these above
>
> b) Fields defining the presence of a feature (1, 2, 3). These would
>     always be positive since the absence of such feature would mean a
>     value of 0
>
> c) Fields defining the absence of a feature by setting 0xf. These are
>     usually fields that were initial RAZ and turned to -1. I don't expect
>     such field be greater than 0, nor smaller than -1.
>
> So I think we can treat (a) and (b) as unsigned permanently.

Agreed.

> We could treat (c) as unsigned as well with a value of 0xf though I'm not sure
> how it matches your LOWER/HIGHER_SAFE definitions.

I think we should treat (c) as signed, as we never know what could change,
given that meaning of (0xf - implies unsupported) < meaning of (0 - supported).
Treating them unsigned could break the LOWER/HIGHER_SAFE definitions and makes
the safe value selection ugly.

Cheers
Suzuki


  reply	other threads:[~2015-11-20 13:37 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-18 17:03 [PATCH 0/5] arm64: cpufeature: Fixes for 4.4-rc1 Suzuki K. Poulose
2015-11-18 17:03 ` Suzuki K. Poulose
2015-11-18 17:08 ` [PATCH 1/5] arm64: cpufeature: Add helpers for extracting unsigned values Suzuki K. Poulose
2015-11-18 17:08   ` Suzuki K. Poulose
2015-11-18 17:08   ` [PATCH 2/5] arm64: cpufeature: Track unsigned fields Suzuki K. Poulose
2015-11-18 17:08     ` Suzuki K. Poulose
2015-11-19  4:57     ` AKASHI Takahiro
2015-11-19  4:57       ` AKASHI Takahiro
2015-11-19 10:03       ` Suzuki K. Poulose
2015-11-19 10:03         ` Suzuki K. Poulose
2015-11-19 10:06         ` Suzuki K. Poulose
2015-11-19 10:06           ` Suzuki K. Poulose
2015-11-19 18:45         ` Catalin Marinas
2015-11-19 18:45           ` Catalin Marinas
2015-11-20 13:37           ` Suzuki K. Poulose [this message]
2015-11-20 13:37             ` Suzuki K. Poulose
2015-11-18 17:08   ` [PATCH 3/5] arm64: debug: Treat the BRPs/WRPs as unsigned Suzuki K. Poulose
2015-11-18 17:08     ` Suzuki K. Poulose
2015-11-23 17:29     ` Will Deacon
2015-11-23 17:29       ` Will Deacon
2015-11-18 17:08   ` [PATCH 4/5] arm64: Make fail_incapable_cpu reusable Suzuki K. Poulose
2015-11-18 17:08     ` Suzuki K. Poulose
2015-11-18 17:09   ` [PATCH 5/5] arm64: Ensure the secondary CPUs have safe ASIDBits size Suzuki K. Poulose
2015-11-18 17:09     ` Suzuki K. Poulose
2015-11-23 17:29     ` Will Deacon
2015-11-23 17:29       ` Will Deacon
2015-11-23 23:48       ` Suzuki K. Poulose
2015-11-23 23:48         ` Suzuki K. Poulose
2015-11-26 18:13 ` [PATCH 0/5] arm64: cpufeature: Fixes for 4.4-rc1 Catalin Marinas
2015-11-26 18:13   ` Catalin Marinas

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