From: Jon Hunter <jonathanh@nvidia.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
"Stephen Warren" <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
Alexandre Courbot <gnurou@gmail.com>, <linux-clk@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Rhyland Klein <rklein@nvidia.com>
Subject: Re: [PATCH] clk: tegra: Fix bypassing of PLLs
Date: Mon, 23 Nov 2015 12:36:33 +0000 [thread overview]
Message-ID: <56530851.8020206@nvidia.com> (raw)
In-Reply-To: <20151120171527.GL32672@codeaurora.org>
On 20/11/15 17:15, Stephen Boyd wrote:
> On 11/20, Jon Hunter wrote:
>> The _clk_disable_pll() function will attempt to place a PLL into bypass
>> if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL
>> by clearing the enable bit. To place the PLL into bypass, the bypass bit
>> needs to be set and not cleared. Fix this by setting the bypass bit and
>> not clearing it.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>
> Fixes tag? It looks like this has been wrong from the beginning
> of time.
Yes good point.
Thierry, I see you have put this in the -next branch for tegra. Do you
want to add the following?
Fixes: 8f8f484bf355 ("clk: tegra: add Tegra specific clocks")
Jon
WARNING: multiple messages have this Message-ID (diff)
From: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH] clk: tegra: Fix bypassing of PLLs
Date: Mon, 23 Nov 2015 12:36:33 +0000 [thread overview]
Message-ID: <56530851.8020206@nvidia.com> (raw)
In-Reply-To: <20151120171527.GL32672-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 20/11/15 17:15, Stephen Boyd wrote:
> On 11/20, Jon Hunter wrote:
>> The _clk_disable_pll() function will attempt to place a PLL into bypass
>> if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL
>> by clearing the enable bit. To place the PLL into bypass, the bypass bit
>> needs to be set and not cleared. Fix this by setting the bypass bit and
>> not clearing it.
>>
>> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>
> Fixes tag? It looks like this has been wrong from the beginning
> of time.
Yes good point.
Thierry, I see you have put this in the -next branch for tegra. Do you
want to add the following?
Fixes: 8f8f484bf355 ("clk: tegra: add Tegra specific clocks")
Jon
next prev parent reply other threads:[~2015-11-23 12:36 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-20 15:11 [PATCH] clk: tegra: Fix bypassing of PLLs Jon Hunter
2015-11-20 15:11 ` Jon Hunter
2015-11-20 16:43 ` Rhyland Klein
2015-11-20 16:43 ` Rhyland Klein
2015-11-20 17:15 ` Stephen Boyd
2015-11-20 17:15 ` Stephen Boyd
2015-11-23 12:36 ` Jon Hunter [this message]
2015-11-23 12:36 ` Jon Hunter
2015-11-23 23:18 ` Tyler Baker
2015-11-24 10:21 ` Jon Hunter
2015-11-24 10:21 ` Jon Hunter
2015-11-24 15:10 ` Thierry Reding
2015-11-24 15:25 ` Jon Hunter
2015-11-24 15:25 ` Jon Hunter
2015-11-25 15:11 ` Thierry Reding
2015-11-25 15:52 ` Tyler Baker
2015-11-25 15:52 ` Tyler Baker
2015-11-25 17:48 ` Jon Hunter
2015-11-25 17:48 ` Jon Hunter
2015-11-26 9:56 ` Jon Hunter
2015-11-26 9:56 ` Jon Hunter
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