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From: Leon Alrae <leon.alrae@imgtec.com>
To: Dongxue Zhang <elta.era@gmail.com>,
	QEMU Developers <qemu-devel@nongnu.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH] target-mips/cpu.h: Fix spell error
Date: Wed, 25 Nov 2015 13:09:56 +0000	[thread overview]
Message-ID: <5655B324.4070409@imgtec.com> (raw)
In-Reply-To: <CAEomy4Ro6rV0EMVFHP-E_JaUXF2Weaa2+xNyd=MwAVxxTNCKxw@mail.gmail.com>

On 25/11/15 12:57, Dongxue Zhang wrote:
> CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'.
> 
> Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
> ---
>  target-mips/cpu.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 89c01f7..17817c3 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -358,7 +358,7 @@ struct CPUMIPSState {
>  #define CP0St_IE    0
>      int32_t CP0_IntCtl;
>  #define CP0IntCtl_IPTI 29
> -#define CP0IntCtl_IPPC1 26
> +#define CP0IntCtl_IPPCI 26
>  #define CP0IntCtl_VS 5
>      int32_t CP0_SRSCtl;
>  #define CP0SRSCtl_HSS 26
> 

Thanks for the patch. I've applied it to post-2.5 target-mips queue.

Regards,
Leon

  reply	other threads:[~2015-11-25 13:10 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-25 12:57 [Qemu-devel] [PATCH] target-mips/cpu.h: Fix spell error Dongxue Zhang
2015-11-25 13:09 ` Leon Alrae [this message]
  -- strict thread matches above, loose matches on Subject: below --
2015-11-25  7:08 Dongxue Zhang

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