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From: aryabinin@virtuozzo.com (Andrey Ryabinin)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFT] arm64: kasan: Make KASAN work with 16K pages + 48 bit VA
Date: Fri, 27 Nov 2015 11:12:28 +0300	[thread overview]
Message-ID: <5658106C.10207@virtuozzo.com> (raw)
In-Reply-To: <CAKv+Gu_L1shTWp_5KydCW97Z6TbeXEB9gjmb2oUSuCHfC29M9A@mail.gmail.com>

On 11/26/2015 07:40 PM, Ard Biesheuvel wrote:
> On 26 November 2015 at 14:14, Andrey Ryabinin <aryabinin@virtuozzo.com> wrote:
>> Currently kasan assumes that shadow memory covers one or more entire PGDs.
>> That's not true for 16K pages + 48bit VA space, where PGDIR_SIZE is bigger
>> than the whole shadow memory.
>>
>> This patch tries to fix that case.
>> clear_page_tables() is a new replacement of clear_pgs(). Instead of always
>> clearing pgds it clears top level page table entries that entirely belongs
>> to shadow memory.
>> In addition to 'tmp_pg_dir' we now have 'tmp_pud' which is used to store
>> puds that now might be cleared by clear_page_tables.
>>
>> Reported-by: Suzuki K. Poulose <Suzuki.Poulose@arm.com>
>> Signed-off-by: Andrey Ryabinin <aryabinin@virtuozzo.com>
> 
> I would argue that the Kasan code is complicated enough, and we should
> avoid complicating it even further for a configuration that is highly
> theoretical in nature.
> 
> In a 16k configuration, the 4th level only adds a single bit of VA
> space (which is, as I understand it, exactly the issue you need to
> address here since the top level page table has only 2 entries and
> hence does not divide by 8 cleanly), which means you are better off
> using 3 levels unless you *really* need more than 128 TB of VA space.
> 
> So can't we just live with the limitation, and keep the current code?
 

No objections from my side. Let's keep the current code.

WARNING: multiple messages have this Message-ID (diff)
From: Andrey Ryabinin <aryabinin@virtuozzo.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	Yury <yury.norov@gmail.com>,
	Alexey Klimov <klimov.linux@gmail.com>,
	Arnd Bergmann <arnd@arndb.de>,
	"linux-mm@kvack.org" <linux-mm@kvack.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	David Keitel <dkeitel@codeaurora.org>,
	Alexander Potapenko <glider@google.com>,
	Dmitry Vyukov <dvyukov@google.com>,
	"Suzuki K. Poulose" <Suzuki.Poulose@arm.com>,
	Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH RFT] arm64: kasan: Make KASAN work with 16K pages + 48 bit VA
Date: Fri, 27 Nov 2015 11:12:28 +0300	[thread overview]
Message-ID: <5658106C.10207@virtuozzo.com> (raw)
In-Reply-To: <CAKv+Gu_L1shTWp_5KydCW97Z6TbeXEB9gjmb2oUSuCHfC29M9A@mail.gmail.com>

On 11/26/2015 07:40 PM, Ard Biesheuvel wrote:
> On 26 November 2015 at 14:14, Andrey Ryabinin <aryabinin@virtuozzo.com> wrote:
>> Currently kasan assumes that shadow memory covers one or more entire PGDs.
>> That's not true for 16K pages + 48bit VA space, where PGDIR_SIZE is bigger
>> than the whole shadow memory.
>>
>> This patch tries to fix that case.
>> clear_page_tables() is a new replacement of clear_pgs(). Instead of always
>> clearing pgds it clears top level page table entries that entirely belongs
>> to shadow memory.
>> In addition to 'tmp_pg_dir' we now have 'tmp_pud' which is used to store
>> puds that now might be cleared by clear_page_tables.
>>
>> Reported-by: Suzuki K. Poulose <Suzuki.Poulose@arm.com>
>> Signed-off-by: Andrey Ryabinin <aryabinin@virtuozzo.com>
> 
> I would argue that the Kasan code is complicated enough, and we should
> avoid complicating it even further for a configuration that is highly
> theoretical in nature.
> 
> In a 16k configuration, the 4th level only adds a single bit of VA
> space (which is, as I understand it, exactly the issue you need to
> address here since the top level page table has only 2 entries and
> hence does not divide by 8 cleanly), which means you are better off
> using 3 levels unless you *really* need more than 128 TB of VA space.
> 
> So can't we just live with the limitation, and keep the current code?
 

No objections from my side. Let's keep the current code.

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WARNING: multiple messages have this Message-ID (diff)
From: Andrey Ryabinin <aryabinin@virtuozzo.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	Yury <yury.norov@gmail.com>,
	Alexey Klimov <klimov.linux@gmail.com>,
	Arnd Bergmann <arnd@arndb.de>,
	"linux-mm@kvack.org" <linux-mm@kvack.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	David Keitel <dkeitel@codeaurora.org>,
	Alexander Potapenko <glider@google.com>,
	Dmitry Vyukov <dvyukov@google.com>,
	"Suzuki K. Poulose" <Suzuki.Poulose@arm.com>,
	Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH RFT] arm64: kasan: Make KASAN work with 16K pages + 48 bit VA
Date: Fri, 27 Nov 2015 11:12:28 +0300	[thread overview]
Message-ID: <5658106C.10207@virtuozzo.com> (raw)
In-Reply-To: <CAKv+Gu_L1shTWp_5KydCW97Z6TbeXEB9gjmb2oUSuCHfC29M9A@mail.gmail.com>

On 11/26/2015 07:40 PM, Ard Biesheuvel wrote:
> On 26 November 2015 at 14:14, Andrey Ryabinin <aryabinin@virtuozzo.com> wrote:
>> Currently kasan assumes that shadow memory covers one or more entire PGDs.
>> That's not true for 16K pages + 48bit VA space, where PGDIR_SIZE is bigger
>> than the whole shadow memory.
>>
>> This patch tries to fix that case.
>> clear_page_tables() is a new replacement of clear_pgs(). Instead of always
>> clearing pgds it clears top level page table entries that entirely belongs
>> to shadow memory.
>> In addition to 'tmp_pg_dir' we now have 'tmp_pud' which is used to store
>> puds that now might be cleared by clear_page_tables.
>>
>> Reported-by: Suzuki K. Poulose <Suzuki.Poulose@arm.com>
>> Signed-off-by: Andrey Ryabinin <aryabinin@virtuozzo.com>
> 
> I would argue that the Kasan code is complicated enough, and we should
> avoid complicating it even further for a configuration that is highly
> theoretical in nature.
> 
> In a 16k configuration, the 4th level only adds a single bit of VA
> space (which is, as I understand it, exactly the issue you need to
> address here since the top level page table has only 2 entries and
> hence does not divide by 8 cleanly), which means you are better off
> using 3 levels unless you *really* need more than 128 TB of VA space.
> 
> So can't we just live with the limitation, and keep the current code?
 

No objections from my side. Let's keep the current code.

  reply	other threads:[~2015-11-27  8:12 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-26 13:14 [PATCH RFT] arm64: kasan: Make KASAN work with 16K pages + 48 bit VA Andrey Ryabinin
2015-11-26 13:14 ` Andrey Ryabinin
2015-11-26 13:14 ` Andrey Ryabinin
2015-11-26 14:48 ` Mark Rutland
2015-11-26 14:48   ` Mark Rutland
2015-11-26 14:48   ` Mark Rutland
2015-11-26 15:47   ` Andrey Ryabinin
2015-11-26 15:47     ` Andrey Ryabinin
2015-11-26 15:47     ` Andrey Ryabinin
2015-11-26 16:21     ` Mark Rutland
2015-11-26 16:21       ` Mark Rutland
2015-11-26 16:21       ` Mark Rutland
2015-11-26 16:40       ` Andrey Ryabinin
2015-11-26 16:40         ` Andrey Ryabinin
2015-11-26 16:40         ` Andrey Ryabinin
2015-11-26 17:08         ` Mark Rutland
2015-11-26 17:08           ` Mark Rutland
2015-11-26 17:08           ` Mark Rutland
2015-11-26 16:40 ` Ard Biesheuvel
2015-11-26 16:40   ` Ard Biesheuvel
2015-11-26 16:40   ` Ard Biesheuvel
2015-11-27  8:12   ` Andrey Ryabinin [this message]
2015-11-27  8:12     ` Andrey Ryabinin
2015-11-27  8:12     ` Andrey Ryabinin
2015-11-27  9:35     ` Catalin Marinas
2015-11-27  9:35       ` Catalin Marinas
2015-11-27  9:35       ` Catalin Marinas
2015-11-27 10:02       ` Will Deacon
2015-11-27 10:02         ` Will Deacon
2015-11-27 10:02         ` Will Deacon
2015-11-27 10:39         ` Ard Biesheuvel
2015-11-27 10:39           ` Ard Biesheuvel
2015-11-27 10:39           ` Ard Biesheuvel
2015-11-27 14:11         ` Catalin Marinas
2015-11-27 14:11           ` Catalin Marinas
2015-11-27 14:11           ` Catalin Marinas

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