From: Michael Tokarev <mjt@tls.msk.ru>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: qemu-trivial@nongnu.org
Subject: Re: [Qemu-trivial] [PATCH] gt64xxx: fix decoding of ISD register
Date: Sun, 29 Nov 2015 13:46:58 +0300 [thread overview]
Message-ID: <565AD7A2.9080409@msgid.tls.msk.ru> (raw)
In-Reply-To: <1446824046-4478-1-git-send-email-pbonzini@redhat.com>
06.11.2015 18:34, Paolo Bonzini wrote:
> The GT64xxx's internal registers can be placed above the first 4 GiB
> in the address space, but not above the first 64 GiB. Correctly cast
> the register to a 64-bit integer, and mask away bits above bit 35.
Applied to -trivial, thank you!
/mjt
WARNING: multiple messages have this Message-ID (diff)
From: Michael Tokarev <mjt@tls.msk.ru>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: qemu-trivial@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] gt64xxx: fix decoding of ISD register
Date: Sun, 29 Nov 2015 13:46:58 +0300 [thread overview]
Message-ID: <565AD7A2.9080409@msgid.tls.msk.ru> (raw)
In-Reply-To: <1446824046-4478-1-git-send-email-pbonzini@redhat.com>
06.11.2015 18:34, Paolo Bonzini wrote:
> The GT64xxx's internal registers can be placed above the first 4 GiB
> in the address space, but not above the first 64 GiB. Correctly cast
> the register to a 64-bit integer, and mask away bits above bit 35.
Applied to -trivial, thank you!
/mjt
next prev parent reply other threads:[~2015-11-29 10:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-06 15:34 [Qemu-trivial] [PATCH] gt64xxx: fix decoding of ISD register Paolo Bonzini
2015-11-06 15:34 ` [Qemu-devel] " Paolo Bonzini
2015-11-29 10:46 ` Michael Tokarev [this message]
2015-11-29 10:46 ` Michael Tokarev
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