* [PATCH v3 0/7] ARM: dts: Add Advantech board support
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: devicetree
Cc: mark.rutland, justin.waters, linux, Akshay Bhat, ijc+devicetree,
robh+dt, peter.stretz, kernel, galak, l.stach, shawnguo,
linux-arm-kernel, martin.donnelly
This series aims to add Advantech BA-16 module (iMX6 based) and GE board support.
This series has been tested against linux-next tag next-20151110.
Modifications:
v2->v3:
- Change vendor prefix from adv to advantech as suggested by Rob Herring
- Reorder patches and squash/fold v2 commits as suggested by Lucas Stash
History:
--------
[v1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/381872.html
[v2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/383276.html
Akshay Bhat (5):
of: Add vendor prefix for Advantech Corporation
of: Add vendor prefix for General Electric Company
ARM: dts: imx: Add support for Advantech/GE B450v3
ARM: dts: imx: Add support for Advantech/GE B650v3
ARM: dts: imx: Add support for Advantech/GE B850v3
Justin Waters (2):
ARM: dts: imx: Add Advantech BA-16 Qseven module
ARM: dts: imx: Add support for Advantech/GE Bx50v3
.../devicetree/bindings/vendor-prefixes.txt | 2 +
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx6q-b450v3.dts | 75 +++
arch/arm/boot/dts/imx6q-b650v3.dts | 74 +++
arch/arm/boot/dts/imx6q-b850v3.dts | 122 +++++
arch/arm/boot/dts/imx6q-ba16.dtsi | 584 +++++++++++++++++++++
arch/arm/boot/dts/imx6q-bx50v3.dtsi | 211 ++++++++
7 files changed, 1071 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
create mode 100644 arch/arm/boot/dts/imx6q-b650v3.dts
create mode 100644 arch/arm/boot/dts/imx6q-b850v3.dts
create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
create mode 100644 arch/arm/boot/dts/imx6q-bx50v3.dtsi
--
2.6.3
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 1/7] of: Add vendor prefix for Advantech Corporation
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds vendor prefix for Advantech Corporation.
Website: http://www.advantech.com/
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 55df1d4..5134b24 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -10,6 +10,7 @@ ad Avionic Design GmbH
adapteva Adapteva, Inc.
adh AD Holdings Plc.
adi Analog Devices, Inc.
+advantech Advantech Corporation
aeroflexgaisler Aeroflex Gaisler AB
al Annapurna Labs
allwinner Allwinner Technology Co., Ltd.
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 1/7] of: Add vendor prefix for Advantech Corporation
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ, martin.donnelly-JJi787mZWgc,
peter.stretz-ELdSlb/RfAS1Z/+hSey0Gg,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
This patch adds vendor prefix for Advantech Corporation.
Website: http://www.advantech.com/
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 55df1d4..5134b24 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -10,6 +10,7 @@ ad Avionic Design GmbH
adapteva Adapteva, Inc.
adh AD Holdings Plc.
adi Analog Devices, Inc.
+advantech Advantech Corporation
aeroflexgaisler Aeroflex Gaisler AB
al Annapurna Labs
allwinner Allwinner Technology Co., Ltd.
--
2.6.3
--
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^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 1/7] of: Add vendor prefix for Advantech Corporation
@ 2015-11-10 20:09 ` Rob Herring
0 siblings, 0 replies; 26+ messages in thread
From: Rob Herring @ 2015-11-10 20:09 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Nov 10, 2015 at 12:00 PM, Akshay Bhat <akshay.bhat@timesys.com> wrote:
> This patch adds vendor prefix for Advantech Corporation.
>
> Website: http://www.advantech.com/
> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 55df1d4..5134b24 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -10,6 +10,7 @@ ad Avionic Design GmbH
> adapteva Adapteva, Inc.
> adh AD Holdings Plc.
> adi Analog Devices, Inc.
> +advantech Advantech Corporation
> aeroflexgaisler Aeroflex Gaisler AB
> al Annapurna Labs
> allwinner Allwinner Technology Co., Ltd.
> --
> 2.6.3
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 1/7] of: Add vendor prefix for Advantech Corporation
@ 2015-11-10 20:09 ` Rob Herring
0 siblings, 0 replies; 26+ messages in thread
From: Rob Herring @ 2015-11-10 20:09 UTC (permalink / raw)
To: Akshay Bhat
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
Russell King - ARM Linux, Kumar Gala, Mark Rutland, Ian Campbell,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ, martin.donnelly-JJi787mZWgc,
peter.stretz-ELdSlb/RfAS1Z/+hSey0Gg, Lucas Stach
On Tue, Nov 10, 2015 at 12:00 PM, Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org> wrote:
> This patch adds vendor prefix for Advantech Corporation.
>
> Website: http://www.advantech.com/
> Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 55df1d4..5134b24 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -10,6 +10,7 @@ ad Avionic Design GmbH
> adapteva Adapteva, Inc.
> adh AD Holdings Plc.
> adi Analog Devices, Inc.
> +advantech Advantech Corporation
> aeroflexgaisler Aeroflex Gaisler AB
> al Annapurna Labs
> allwinner Allwinner Technology Co., Ltd.
> --
> 2.6.3
>
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^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 2/7] of: Add vendor prefix for General Electric Company
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds vendor prefix for General Electric Company
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 5134b24..598154c 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -87,6 +87,7 @@ fcs Fairchild Semiconductor
firefly Firefly
focaltech FocalTech Systems Co.,Ltd
fsl Freescale Semiconductor
+ge General Electric Company
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
geniatech Geniatech, Inc.
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 2/7] of: Add vendor prefix for General Electric Company
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ, martin.donnelly-JJi787mZWgc,
peter.stretz-ELdSlb/RfAS1Z/+hSey0Gg,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
This patch adds vendor prefix for General Electric Company
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 5134b24..598154c 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -87,6 +87,7 @@ fcs Fairchild Semiconductor
firefly Firefly
focaltech FocalTech Systems Co.,Ltd
fsl Freescale Semiconductor
+ge General Electric Company
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
geniatech Geniatech, Inc.
--
2.6.3
--
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^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
2015-11-10 18:00 ` Akshay Bhat
@ 2015-11-10 18:00 ` Akshay Bhat
-1 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: linux-arm-kernel
From: Justin Waters <justin.waters@timesys.com>
Add support for Advantech BA-16 module based on iMX6D processor
http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/imx6q-ba16.dtsi | 584 ++++++++++++++++++++++++++++++++++++++
1 file changed, 584 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
new file mode 100644
index 0000000..d0c4568
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -0,0 +1,584 @@
+/*
+ * Support for imx6 based Advantech DMS-BA16 Qseven module
+ *
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ clocks {
+ clk24m: clk24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_usb_otg_vbus: regulator at 1 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator at 2 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_1p8v: regulator at 3 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator at 4 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ lvds_ppen: regulator at 5 {
+ compatible = "regulator-fixed";
+ regulator-name = "lvds_ppen";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ backlight {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_display>;
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100 101 102 103 104 105 106 107 108 109
+ 110 111 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127 128 129
+ 130 131 132 133 134 135 136 137 138 139
+ 140 141 142 143 144 145 146 147 148 149
+ 150 151 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167 168 169
+ 170 171 172 173 174 175 176 177 178 179
+ 180 181 182 183 184 185 186 187 188 189
+ 190 191 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207 208 209
+ 210 211 212 213 214 215 216 217 218 219
+ 220 221 222 223 224 225 226 227 228 229
+ 230 231 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247 248 249
+ 250 251 252 253 254 255>;
+ default-brightness-level = <255>;
+ enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ power-supply = <&lvds_ppen>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: n25q032 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0x0 0xC0000>;
+ };
+ partition at C0000 {
+ label = "env";
+ reg = <0xC0000 0x10000>;
+ };
+ partition at D0000 {
+ label = "spare";
+ reg = <0xD0000 0x130000>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ pmic at 58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <1420000>;
+ regulator-max-microvolt = <1420000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <1420000>;
+ regulator-max-microvolt = <1420000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bio: bio {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_ldo1: ldo1 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1860000>;
+ };
+
+ vdd_ldo2: ldo2 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1860000>;
+ };
+
+ vdd_ldo3: ldo3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3440000>;
+ };
+
+ vdd_ldo4: ldo4 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3440000>;
+ };
+
+ vdd_ldo5: ldo5 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo6: ldo6 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo7: ldo7 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo8: ldo8 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo9: ldo9 {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo10: ldo10 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo11: ldo11 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6q-ba16 {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
+ >;
+ };
+
+ pinctrl_usbhub: usbhubgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
+ >;
+ };
+
+ pinctrl_display: dispgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
+ >;
+ };
+
+ pinctrl_ecspi5: ecspi5rp-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
+ MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
+ MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_reset: usdhc3grp-reset {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
+ >;
+ };
+
+ pinctrl_audmux: audmux {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
+ >;
+ };
+
+ pinctrl_enet: pinctrl_enet {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
+ >;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-master";
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbhub>;
+ vbus-supply = <®_usb_h1_vbus>;
+ reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
+ bus-width = <8>;
+ vmmc-supply = <&vdd_bperi>;
+ vqmmc-supply = <&vdd_bio>;
+ non-removable;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: devicetree
Cc: mark.rutland, justin.waters, linux, Akshay Bhat, ijc+devicetree,
robh+dt, peter.stretz, kernel, galak, l.stach, shawnguo,
linux-arm-kernel, martin.donnelly
From: Justin Waters <justin.waters@timesys.com>
Add support for Advantech BA-16 module based on iMX6D processor
http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/imx6q-ba16.dtsi | 584 ++++++++++++++++++++++++++++++++++++++
1 file changed, 584 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
new file mode 100644
index 0000000..d0c4568
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -0,0 +1,584 @@
+/*
+ * Support for imx6 based Advantech DMS-BA16 Qseven module
+ *
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ clocks {
+ clk24m: clk24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_usb_otg_vbus: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_1p8v: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ lvds_ppen: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "lvds_ppen";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ backlight {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_display>;
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100 101 102 103 104 105 106 107 108 109
+ 110 111 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127 128 129
+ 130 131 132 133 134 135 136 137 138 139
+ 140 141 142 143 144 145 146 147 148 149
+ 150 151 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167 168 169
+ 170 171 172 173 174 175 176 177 178 179
+ 180 181 182 183 184 185 186 187 188 189
+ 190 191 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207 208 209
+ 210 211 212 213 214 215 216 217 218 219
+ 220 221 222 223 224 225 226 227 228 229
+ 230 231 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247 248 249
+ 250 251 252 253 254 255>;
+ default-brightness-level = <255>;
+ enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ power-supply = <&lvds_ppen>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: n25q032@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0xC0000>;
+ };
+ partition@C0000 {
+ label = "env";
+ reg = <0xC0000 0x10000>;
+ };
+ partition@D0000 {
+ label = "spare";
+ reg = <0xD0000 0x130000>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <1420000>;
+ regulator-max-microvolt = <1420000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <1420000>;
+ regulator-max-microvolt = <1420000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bio: bio {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_ldo1: ldo1 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1860000>;
+ };
+
+ vdd_ldo2: ldo2 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1860000>;
+ };
+
+ vdd_ldo3: ldo3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3440000>;
+ };
+
+ vdd_ldo4: ldo4 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3440000>;
+ };
+
+ vdd_ldo5: ldo5 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo6: ldo6 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo7: ldo7 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo8: ldo8 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo9: ldo9 {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo10: ldo10 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo11: ldo11 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6q-ba16 {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
+ >;
+ };
+
+ pinctrl_usbhub: usbhubgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
+ >;
+ };
+
+ pinctrl_display: dispgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
+ >;
+ };
+
+ pinctrl_ecspi5: ecspi5rp-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
+ MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
+ MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_reset: usdhc3grp-reset {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
+ >;
+ };
+
+ pinctrl_audmux: audmux {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
+ >;
+ };
+
+ pinctrl_enet: pinctrl_enet {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
+ >;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-master";
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbhub>;
+ vbus-supply = <®_usb_h1_vbus>;
+ reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
+ bus-width = <8>;
+ vmmc-supply = <&vdd_bperi>;
+ vqmmc-supply = <&vdd_bio>;
+ non-removable;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-11-16 11:16 ` Lucas Stach
0 siblings, 0 replies; 26+ messages in thread
From: Lucas Stach @ 2015-11-16 11:16 UTC (permalink / raw)
To: linux-arm-kernel
Hi Akshay,
another comment below and in the next patch, sorry for not spotting this
in the last round.
Regards,
Lucas
Am Dienstag, den 10.11.2015, 13:00 -0500 schrieb Akshay Bhat:
> From: Justin Waters <justin.waters@timesys.com>
>
> Add support for Advantech BA-16 module based on iMX6D processor
>
> http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
> ---
> arch/arm/boot/dts/imx6q-ba16.dtsi | 584 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 584 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
> new file mode 100644
> index 0000000..d0c4568
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
> @@ -0,0 +1,584 @@
> +/*
> + * Support for imx6 based Advantech DMS-BA16 Qseven module
> + *
> + * Copyright 2015 Timesys Corporation.
> + * Copyright 2015 General Electric Company
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include "imx6q.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + memory {
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + clocks {
> + clk24m: clk24m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> +
The use of a simple-bus, while giving some structure to the DT is
considered bad style as it doesn't reflect any real hardware.
Please remove this, the regulators should be located the same DT level
as the backlight and other board components.
> + reg_usb_otg_vbus: regulator at 1 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_usb_h1_vbus: regulator at 2 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_1p8v: regulator at 3 {
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_3p3v: regulator at 4 {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + lvds_ppen: regulator at 5 {
> + compatible = "regulator-fixed";
> + regulator-name = "lvds_ppen";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> + };
> +
> + backlight {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_display>;
> + compatible = "pwm-backlight";
> + pwms = <&pwm1 0 5000000>;
> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
> + 10 11 12 13 14 15 16 17 18 19
> + 20 21 22 23 24 25 26 27 28 29
> + 30 31 32 33 34 35 36 37 38 39
> + 40 41 42 43 44 45 46 47 48 49
> + 50 51 52 53 54 55 56 57 58 59
> + 60 61 62 63 64 65 66 67 68 69
> + 70 71 72 73 74 75 76 77 78 79
> + 80 81 82 83 84 85 86 87 88 89
> + 90 91 92 93 94 95 96 97 98 99
> + 100 101 102 103 104 105 106 107 108 109
> + 110 111 112 113 114 115 116 117 118 119
> + 120 121 122 123 124 125 126 127 128 129
> + 130 131 132 133 134 135 136 137 138 139
> + 140 141 142 143 144 145 146 147 148 149
> + 150 151 152 153 154 155 156 157 158 159
> + 160 161 162 163 164 165 166 167 168 169
> + 170 171 172 173 174 175 176 177 178 179
> + 180 181 182 183 184 185 186 187 188 189
> + 190 191 192 193 194 195 196 197 198 199
> + 200 201 202 203 204 205 206 207 208 209
> + 210 211 212 213 214 215 216 217 218 219
> + 220 221 222 223 224 225 226 227 228 229
> + 230 231 232 233 234 235 236 237 238 239
> + 240 241 242 243 244 245 246 247 248 249
> + 250 251 252 253 254 255>;
> + default-brightness-level = <255>;
> + enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
> + power-supply = <&lvds_ppen>;
> + };
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux>;
> + status = "okay";
> +};
> +
> +&ecspi1 {
> + fsl,spi-num-chipselects = <1>;
> + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + status = "okay";
> +
> + flash: n25q032 at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <20000000>;
> + reg = <0>;
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0x0 0xC0000>;
> + };
> + partition at C0000 {
> + label = "env";
> + reg = <0xC0000 0x10000>;
> + };
> + partition at D0000 {
> + label = "spare";
> + reg = <0xD0000 0x130000>;
> + };
> + };
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rgmii";
> + status = "okay";
> +};
> +
> +&hdmi {
> + ddc-i2c-bus = <&i2c2>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + status = "okay";
> +
> + pmic at 58 {
> + compatible = "dlg,da9063";
> + reg = <0x58>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio7>;
> + interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> +
> + regulators {
> + vdd_bcore1: bcore1 {
> + regulator-min-microvolt = <1420000>;
> + regulator-max-microvolt = <1420000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bcore2: bcore2 {
> + regulator-min-microvolt = <1420000>;
> + regulator-max-microvolt = <1420000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bpro: bpro {
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bmem: bmem {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bio: bio {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bperi: bperi {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_ldo1: ldo1 {
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1860000>;
> + };
> +
> + vdd_ldo2: ldo2 {
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1860000>;
> + };
> +
> + vdd_ldo3: ldo3 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3440000>;
> + };
> +
> + vdd_ldo4: ldo4 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3440000>;
> + };
> +
> + vdd_ldo5: ldo5 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo6: ldo6 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo7: ldo7 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo8: ldo8 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo9: ldo9 {
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo10: ldo10 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo11: ldo11 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> + };
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
> +
> + imx6q-ba16 {
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
> + >;
> + };
> +
> + pinctrl_pmic: pmicgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
> + >;
> + };
> +
> + pinctrl_usbhub: usbhubgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
> + >;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
> + >;
> + };
> +
> + pinctrl_display: dispgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
> + >;
> + };
> +
> + pinctrl_usdhc4: usdhc4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
> + >;
> + };
> +
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
> + >;
> + };
> +
> + pinctrl_ecspi5: ecspi5rp-1 {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
> + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
> + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_reset: usdhc3grp-reset {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
> + >;
> + };
> +
> + pinctrl_audmux: audmux {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
> + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
> + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
> + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
> + >;
> + };
> +
> + pinctrl_enet: pinctrl_enet {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
> + >;
> + };
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "okay";
> +};
> +
> +&sata {
> + status = "okay";
> +};
> +
> +&ssi1 {
> + fsl,mode = "i2s-master";
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + status = "okay";
> +};
> +
> +&usbh1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbhub>;
> + vbus-supply = <®_usb_h1_vbus>;
> + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&usbotg {
> + vbus-supply = <®_usb_otg_vbus>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + enable-sdio-wakeup;
> + status = "okay";
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
> + bus-width = <8>;
> + vmmc-supply = <&vdd_bperi>;
> + vqmmc-supply = <&vdd_bio>;
> + non-removable;
> + keep-power-in-suspend;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> +};
--
Pengutronix e.K. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v3 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-11-16 11:16 ` Lucas Stach
0 siblings, 0 replies; 26+ messages in thread
From: Lucas Stach @ 2015-11-16 11:16 UTC (permalink / raw)
To: Akshay Bhat
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ, martin.donnelly-JJi787mZWgc,
peter.stretz-ELdSlb/RfAS1Z/+hSey0Gg
Hi Akshay,
another comment below and in the next patch, sorry for not spotting this
in the last round.
Regards,
Lucas
Am Dienstag, den 10.11.2015, 13:00 -0500 schrieb Akshay Bhat:
> From: Justin Waters <justin.waters-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
>
> Add support for Advantech BA-16 module based on iMX6D processor
>
> http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
> Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
> ---
> arch/arm/boot/dts/imx6q-ba16.dtsi | 584 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 584 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
> new file mode 100644
> index 0000000..d0c4568
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
> @@ -0,0 +1,584 @@
> +/*
> + * Support for imx6 based Advantech DMS-BA16 Qseven module
> + *
> + * Copyright 2015 Timesys Corporation.
> + * Copyright 2015 General Electric Company
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include "imx6q.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + memory {
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + clocks {
> + clk24m: clk24m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> +
The use of a simple-bus, while giving some structure to the DT is
considered bad style as it doesn't reflect any real hardware.
Please remove this, the regulators should be located the same DT level
as the backlight and other board components.
> + reg_usb_otg_vbus: regulator@1 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_usb_h1_vbus: regulator@2 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_1p8v: regulator@3 {
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_3p3v: regulator@4 {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + lvds_ppen: regulator@5 {
> + compatible = "regulator-fixed";
> + regulator-name = "lvds_ppen";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> + };
> +
> + backlight {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_display>;
> + compatible = "pwm-backlight";
> + pwms = <&pwm1 0 5000000>;
> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
> + 10 11 12 13 14 15 16 17 18 19
> + 20 21 22 23 24 25 26 27 28 29
> + 30 31 32 33 34 35 36 37 38 39
> + 40 41 42 43 44 45 46 47 48 49
> + 50 51 52 53 54 55 56 57 58 59
> + 60 61 62 63 64 65 66 67 68 69
> + 70 71 72 73 74 75 76 77 78 79
> + 80 81 82 83 84 85 86 87 88 89
> + 90 91 92 93 94 95 96 97 98 99
> + 100 101 102 103 104 105 106 107 108 109
> + 110 111 112 113 114 115 116 117 118 119
> + 120 121 122 123 124 125 126 127 128 129
> + 130 131 132 133 134 135 136 137 138 139
> + 140 141 142 143 144 145 146 147 148 149
> + 150 151 152 153 154 155 156 157 158 159
> + 160 161 162 163 164 165 166 167 168 169
> + 170 171 172 173 174 175 176 177 178 179
> + 180 181 182 183 184 185 186 187 188 189
> + 190 191 192 193 194 195 196 197 198 199
> + 200 201 202 203 204 205 206 207 208 209
> + 210 211 212 213 214 215 216 217 218 219
> + 220 221 222 223 224 225 226 227 228 229
> + 230 231 232 233 234 235 236 237 238 239
> + 240 241 242 243 244 245 246 247 248 249
> + 250 251 252 253 254 255>;
> + default-brightness-level = <255>;
> + enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
> + power-supply = <&lvds_ppen>;
> + };
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux>;
> + status = "okay";
> +};
> +
> +&ecspi1 {
> + fsl,spi-num-chipselects = <1>;
> + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + status = "okay";
> +
> + flash: n25q032@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <20000000>;
> + reg = <0>;
> + partition@0 {
> + label = "U-Boot";
> + reg = <0x0 0xC0000>;
> + };
> + partition@C0000 {
> + label = "env";
> + reg = <0xC0000 0x10000>;
> + };
> + partition@D0000 {
> + label = "spare";
> + reg = <0xD0000 0x130000>;
> + };
> + };
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rgmii";
> + status = "okay";
> +};
> +
> +&hdmi {
> + ddc-i2c-bus = <&i2c2>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + status = "okay";
> +
> + pmic@58 {
> + compatible = "dlg,da9063";
> + reg = <0x58>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio7>;
> + interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> +
> + regulators {
> + vdd_bcore1: bcore1 {
> + regulator-min-microvolt = <1420000>;
> + regulator-max-microvolt = <1420000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bcore2: bcore2 {
> + regulator-min-microvolt = <1420000>;
> + regulator-max-microvolt = <1420000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bpro: bpro {
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bmem: bmem {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bio: bio {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bperi: bperi {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_ldo1: ldo1 {
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1860000>;
> + };
> +
> + vdd_ldo2: ldo2 {
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1860000>;
> + };
> +
> + vdd_ldo3: ldo3 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3440000>;
> + };
> +
> + vdd_ldo4: ldo4 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3440000>;
> + };
> +
> + vdd_ldo5: ldo5 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo6: ldo6 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo7: ldo7 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo8: ldo8 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo9: ldo9 {
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo10: ldo10 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo11: ldo11 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> + };
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
> +
> + imx6q-ba16 {
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
> + >;
> + };
> +
> + pinctrl_pmic: pmicgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
> + >;
> + };
> +
> + pinctrl_usbhub: usbhubgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
> + >;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
> + >;
> + };
> +
> + pinctrl_display: dispgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
> + >;
> + };
> +
> + pinctrl_usdhc4: usdhc4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
> + >;
> + };
> +
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
> + >;
> + };
> +
> + pinctrl_ecspi5: ecspi5rp-1 {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
> + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
> + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_reset: usdhc3grp-reset {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
> + >;
> + };
> +
> + pinctrl_audmux: audmux {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
> + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
> + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
> + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
> + >;
> + };
> +
> + pinctrl_enet: pinctrl_enet {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
> + >;
> + };
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "okay";
> +};
> +
> +&sata {
> + status = "okay";
> +};
> +
> +&ssi1 {
> + fsl,mode = "i2s-master";
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + status = "okay";
> +};
> +
> +&usbh1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbhub>;
> + vbus-supply = <®_usb_h1_vbus>;
> + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&usbotg {
> + vbus-supply = <®_usb_otg_vbus>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + enable-sdio-wakeup;
> + status = "okay";
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
> + bus-width = <8>;
> + vmmc-supply = <&vdd_bperi>;
> + vqmmc-supply = <&vdd_bio>;
> + non-removable;
> + keep-power-in-suspend;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> +};
--
Pengutronix e.K. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 26+ messages in thread* [PATCH v3 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-02 18:40 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-12-02 18:40 UTC (permalink / raw)
To: linux-arm-kernel
On 11/16/2015 06:16 AM, Lucas Stach wrote:
> Hi Akshay,
>
> another comment below and in the next patch, sorry for not spotting this
> in the last round.
>
> Regards,
> Lucas
>
Thanks for the continued feedback :)
> Am Dienstag, den 10.11.2015, 13:00 -0500 schrieb Akshay Bhat:
>> From: Justin Waters <justin.waters@timesys.com>
>>
>> Add support for Advantech BA-16 module based on iMX6D processor
>>
>> http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
>> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
>> ---
>> arch/arm/boot/dts/imx6q-ba16.dtsi | 584 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 584 insertions(+)
>> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
>>
>> diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
>> new file mode 100644
>> index 0000000..d0c4568
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
>> @@ -0,0 +1,584 @@
>> +/*
>> + * Support for imx6 based Advantech DMS-BA16 Qseven module
>> + *
>> + * Copyright 2015 Timesys Corporation.
>> + * Copyright 2015 General Electric Company
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +#include "imx6q.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + memory {
>> + reg = <0x10000000 0x40000000>;
>> + };
>> +
>> + clocks {
>> + clk24m: clk24m {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24000000>;
>> + };
>> + };
>> +
>> + regulators {
>> + compatible = "simple-bus";
>> +
>
> The use of a simple-bus, while giving some structure to the DT is
> considered bad style as it doesn't reflect any real hardware.
>
> Please remove this, the regulators should be located the same DT level
> as the backlight and other board components.
Thanks for the explanation. Fixed in v4 version of patch:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390373.html
>
>> + reg_usb_otg_vbus: regulator at 1 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "usb_otg_vbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +
>> + reg_usb_h1_vbus: regulator at 2 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "usb_h1_vbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +
>> + reg_1p8v: regulator at 3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "1P8V";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + };
>> +
>> + reg_3p3v: regulator at 4 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "3P3V";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + lvds_ppen: regulator at 5 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "lvds_ppen";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> + };
>> +
>> + backlight {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_display>;
>> + compatible = "pwm-backlight";
>> + pwms = <&pwm1 0 5000000>;
>> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
>> + 10 11 12 13 14 15 16 17 18 19
>> + 20 21 22 23 24 25 26 27 28 29
>> + 30 31 32 33 34 35 36 37 38 39
>> + 40 41 42 43 44 45 46 47 48 49
>> + 50 51 52 53 54 55 56 57 58 59
>> + 60 61 62 63 64 65 66 67 68 69
>> + 70 71 72 73 74 75 76 77 78 79
>> + 80 81 82 83 84 85 86 87 88 89
>> + 90 91 92 93 94 95 96 97 98 99
>> + 100 101 102 103 104 105 106 107 108 109
>> + 110 111 112 113 114 115 116 117 118 119
>> + 120 121 122 123 124 125 126 127 128 129
>> + 130 131 132 133 134 135 136 137 138 139
>> + 140 141 142 143 144 145 146 147 148 149
>> + 150 151 152 153 154 155 156 157 158 159
>> + 160 161 162 163 164 165 166 167 168 169
>> + 170 171 172 173 174 175 176 177 178 179
>> + 180 181 182 183 184 185 186 187 188 189
>> + 190 191 192 193 194 195 196 197 198 199
>> + 200 201 202 203 204 205 206 207 208 209
>> + 210 211 212 213 214 215 216 217 218 219
>> + 220 221 222 223 224 225 226 227 228 229
>> + 230 231 232 233 234 235 236 237 238 239
>> + 240 241 242 243 244 245 246 247 248 249
>> + 250 251 252 253 254 255>;
>> + default-brightness-level = <255>;
>> + enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
>> + power-supply = <&lvds_ppen>;
>> + };
>> +};
>> +
>> +&audmux {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_audmux>;
>> + status = "okay";
>> +};
>> +
>> +&ecspi1 {
>> + fsl,spi-num-chipselects = <1>;
>> + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_ecspi1>;
>> + status = "okay";
>> +
>> + flash: n25q032 at 0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "jedec,spi-nor";
>> + spi-max-frequency = <20000000>;
>> + reg = <0>;
>> + partition at 0 {
>> + label = "U-Boot";
>> + reg = <0x0 0xC0000>;
>> + };
>> + partition at C0000 {
>> + label = "env";
>> + reg = <0xC0000 0x10000>;
>> + };
>> + partition at D0000 {
>> + label = "spare";
>> + reg = <0xD0000 0x130000>;
>> + };
>> + };
>> +};
>> +
>> +&fec {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet>;
>> + phy-mode = "rgmii";
>> + status = "okay";
>> +};
>> +
>> +&hdmi {
>> + ddc-i2c-bus = <&i2c2>;
>> + status = "okay";
>> +};
>> +
>> +&i2c1 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c1>;
>> + status = "okay";
>> +};
>> +
>> +&i2c2 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c2>;
>> + status = "okay";
>> +};
>> +
>> +&i2c3 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c3>;
>> + status = "okay";
>> +
>> + pmic at 58 {
>> + compatible = "dlg,da9063";
>> + reg = <0x58>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pmic>;
>> + interrupt-parent = <&gpio7>;
>> + interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
>> +
>> + regulators {
>> + vdd_bcore1: bcore1 {
>> + regulator-min-microvolt = <1420000>;
>> + regulator-max-microvolt = <1420000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bcore2: bcore2 {
>> + regulator-min-microvolt = <1420000>;
>> + regulator-max-microvolt = <1420000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bpro: bpro {
>> + regulator-min-microvolt = <1500000>;
>> + regulator-max-microvolt = <1500000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bmem: bmem {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bio: bio {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bperi: bperi {
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_ldo1: ldo1 {
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <1860000>;
>> + };
>> +
>> + vdd_ldo2: ldo2 {
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <1860000>;
>> + };
>> +
>> + vdd_ldo3: ldo3 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3440000>;
>> + };
>> +
>> + vdd_ldo4: ldo4 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3440000>;
>> + };
>> +
>> + vdd_ldo5: ldo5 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo6: ldo6 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo7: ldo7 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo8: ldo8 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo9: ldo9 {
>> + regulator-min-microvolt = <950000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo10: ldo10 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo11: ldo11 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&iomuxc {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_hog>;
>> +
>> + imx6q-ba16 {
>> + pinctrl_hog: hoggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
>> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
>> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
>> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
>> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
>> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
>> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
>> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
>> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
>> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
>> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
>> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
>> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
>> + >;
>> + };
>> +
>> + pinctrl_wdog: wdoggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
>> + >;
>> + };
>> +
>> + pinctrl_pmic: pmicgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
>> + >;
>> + };
>> +
>> + pinctrl_usbhub: usbhubgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
>> + >;
>> + };
>> +
>> + pinctrl_pcie: pciegrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
>> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
>> + >;
>> + };
>> +
>> + pinctrl_display: dispgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
>> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
>> + >;
>> + };
>> +
>> + pinctrl_usdhc4: usdhc4grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
>> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
>> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
>> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
>> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
>> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
>> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
>> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
>> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
>> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
>> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
>> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
>> + >;
>> + };
>> +
>> + pinctrl_ecspi1: ecspi1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
>> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
>> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
>> + >;
>> + };
>> +
>> + pinctrl_ecspi5: ecspi5rp-1 {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
>> + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
>> + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
>> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
>> + >;
>> + };
>> +
>> + pinctrl_pwm1: pwm1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_pwm2: pwm2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usbotg: usbotggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_i2c1: i2c1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
>> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_i2c2: i2c2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
>> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_i2c3: i2c3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
>> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_uart3: uart3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
>> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
>> + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_uart4: uart4grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
>> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
>> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
>> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
>> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
>> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
>> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3: usdhc3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
>> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
>> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
>> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
>> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
>> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
>> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
>> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
>> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3_reset: usdhc3grp-reset {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
>> + >;
>> + };
>> +
>> + pinctrl_audmux: audmux {
>> + fsl,pins = <
>> + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
>> + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
>> + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
>> + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
>> + >;
>> + };
>> +
>> + pinctrl_enet: pinctrl_enet {
>> + fsl,pins = <
>> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
>> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
>> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
>> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
>> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
>> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
>> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
>> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
>> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
>> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
>> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
>> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
>> + >;
>> + };
>> + };
>> +};
>> +
>> +&pcie {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pcie>;
>> + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> +
>> +&pwm1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm1>;
>> + status = "okay";
>> +};
>> +
>> +&pwm2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm2>;
>> + status = "okay";
>> +};
>> +
>> +&sata {
>> + status = "okay";
>> +};
>> +
>> +&ssi1 {
>> + fsl,mode = "i2s-master";
>> + status = "okay";
>> +};
>> +
>> +&uart3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart3>;
>> + fsl,uart-has-rtscts;
>> + status = "okay";
>> +};
>> +
>> +&uart4 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart4>;
>> + status = "okay";
>> +};
>> +
>> +&usbh1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usbhub>;
>> + vbus-supply = <®_usb_h1_vbus>;
>> + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> +&usbotg {
>> + vbus-supply = <®_usb_otg_vbus>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usbotg>;
>> + disable-over-current;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
>> + no-1-8-v;
>> + keep-power-in-suspend;
>> + enable-sdio-wakeup;
>> + status = "okay";
>> +};
>> +
>> +&usdhc3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
>> + bus-width = <8>;
>> + vmmc-supply = <&vdd_bperi>;
>> + vqmmc-supply = <&vdd_bio>;
>> + non-removable;
>> + keep-power-in-suspend;
>> + status = "okay";
>> +};
>> +
>> +&wdog1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_wdog>;
>> +};
>
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v3 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-02 18:40 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-12-02 18:40 UTC (permalink / raw)
To: Lucas Stach
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ, martin.donnelly-JJi787mZWgc,
peter.stretz-ELdSlb/RfAS1Z/+hSey0Gg
On 11/16/2015 06:16 AM, Lucas Stach wrote:
> Hi Akshay,
>
> another comment below and in the next patch, sorry for not spotting this
> in the last round.
>
> Regards,
> Lucas
>
Thanks for the continued feedback :)
> Am Dienstag, den 10.11.2015, 13:00 -0500 schrieb Akshay Bhat:
>> From: Justin Waters <justin.waters-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
>>
>> Add support for Advantech BA-16 module based on iMX6D processor
>>
>> http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
>> Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
>> ---
>> arch/arm/boot/dts/imx6q-ba16.dtsi | 584 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 584 insertions(+)
>> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
>>
>> diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
>> new file mode 100644
>> index 0000000..d0c4568
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
>> @@ -0,0 +1,584 @@
>> +/*
>> + * Support for imx6 based Advantech DMS-BA16 Qseven module
>> + *
>> + * Copyright 2015 Timesys Corporation.
>> + * Copyright 2015 General Electric Company
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +#include "imx6q.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + memory {
>> + reg = <0x10000000 0x40000000>;
>> + };
>> +
>> + clocks {
>> + clk24m: clk24m {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24000000>;
>> + };
>> + };
>> +
>> + regulators {
>> + compatible = "simple-bus";
>> +
>
> The use of a simple-bus, while giving some structure to the DT is
> considered bad style as it doesn't reflect any real hardware.
>
> Please remove this, the regulators should be located the same DT level
> as the backlight and other board components.
Thanks for the explanation. Fixed in v4 version of patch:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390373.html
>
>> + reg_usb_otg_vbus: regulator@1 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "usb_otg_vbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +
>> + reg_usb_h1_vbus: regulator@2 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "usb_h1_vbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +
>> + reg_1p8v: regulator@3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "1P8V";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + };
>> +
>> + reg_3p3v: regulator@4 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "3P3V";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + lvds_ppen: regulator@5 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "lvds_ppen";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> + };
>> +
>> + backlight {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_display>;
>> + compatible = "pwm-backlight";
>> + pwms = <&pwm1 0 5000000>;
>> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
>> + 10 11 12 13 14 15 16 17 18 19
>> + 20 21 22 23 24 25 26 27 28 29
>> + 30 31 32 33 34 35 36 37 38 39
>> + 40 41 42 43 44 45 46 47 48 49
>> + 50 51 52 53 54 55 56 57 58 59
>> + 60 61 62 63 64 65 66 67 68 69
>> + 70 71 72 73 74 75 76 77 78 79
>> + 80 81 82 83 84 85 86 87 88 89
>> + 90 91 92 93 94 95 96 97 98 99
>> + 100 101 102 103 104 105 106 107 108 109
>> + 110 111 112 113 114 115 116 117 118 119
>> + 120 121 122 123 124 125 126 127 128 129
>> + 130 131 132 133 134 135 136 137 138 139
>> + 140 141 142 143 144 145 146 147 148 149
>> + 150 151 152 153 154 155 156 157 158 159
>> + 160 161 162 163 164 165 166 167 168 169
>> + 170 171 172 173 174 175 176 177 178 179
>> + 180 181 182 183 184 185 186 187 188 189
>> + 190 191 192 193 194 195 196 197 198 199
>> + 200 201 202 203 204 205 206 207 208 209
>> + 210 211 212 213 214 215 216 217 218 219
>> + 220 221 222 223 224 225 226 227 228 229
>> + 230 231 232 233 234 235 236 237 238 239
>> + 240 241 242 243 244 245 246 247 248 249
>> + 250 251 252 253 254 255>;
>> + default-brightness-level = <255>;
>> + enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
>> + power-supply = <&lvds_ppen>;
>> + };
>> +};
>> +
>> +&audmux {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_audmux>;
>> + status = "okay";
>> +};
>> +
>> +&ecspi1 {
>> + fsl,spi-num-chipselects = <1>;
>> + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_ecspi1>;
>> + status = "okay";
>> +
>> + flash: n25q032@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "jedec,spi-nor";
>> + spi-max-frequency = <20000000>;
>> + reg = <0>;
>> + partition@0 {
>> + label = "U-Boot";
>> + reg = <0x0 0xC0000>;
>> + };
>> + partition@C0000 {
>> + label = "env";
>> + reg = <0xC0000 0x10000>;
>> + };
>> + partition@D0000 {
>> + label = "spare";
>> + reg = <0xD0000 0x130000>;
>> + };
>> + };
>> +};
>> +
>> +&fec {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet>;
>> + phy-mode = "rgmii";
>> + status = "okay";
>> +};
>> +
>> +&hdmi {
>> + ddc-i2c-bus = <&i2c2>;
>> + status = "okay";
>> +};
>> +
>> +&i2c1 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c1>;
>> + status = "okay";
>> +};
>> +
>> +&i2c2 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c2>;
>> + status = "okay";
>> +};
>> +
>> +&i2c3 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c3>;
>> + status = "okay";
>> +
>> + pmic@58 {
>> + compatible = "dlg,da9063";
>> + reg = <0x58>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pmic>;
>> + interrupt-parent = <&gpio7>;
>> + interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
>> +
>> + regulators {
>> + vdd_bcore1: bcore1 {
>> + regulator-min-microvolt = <1420000>;
>> + regulator-max-microvolt = <1420000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bcore2: bcore2 {
>> + regulator-min-microvolt = <1420000>;
>> + regulator-max-microvolt = <1420000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bpro: bpro {
>> + regulator-min-microvolt = <1500000>;
>> + regulator-max-microvolt = <1500000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bmem: bmem {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bio: bio {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bperi: bperi {
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_ldo1: ldo1 {
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <1860000>;
>> + };
>> +
>> + vdd_ldo2: ldo2 {
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <1860000>;
>> + };
>> +
>> + vdd_ldo3: ldo3 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3440000>;
>> + };
>> +
>> + vdd_ldo4: ldo4 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3440000>;
>> + };
>> +
>> + vdd_ldo5: ldo5 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo6: ldo6 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo7: ldo7 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo8: ldo8 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo9: ldo9 {
>> + regulator-min-microvolt = <950000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo10: ldo10 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo11: ldo11 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&iomuxc {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_hog>;
>> +
>> + imx6q-ba16 {
>> + pinctrl_hog: hoggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
>> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
>> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
>> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
>> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
>> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
>> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
>> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
>> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
>> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
>> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
>> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
>> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
>> + >;
>> + };
>> +
>> + pinctrl_wdog: wdoggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
>> + >;
>> + };
>> +
>> + pinctrl_pmic: pmicgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
>> + >;
>> + };
>> +
>> + pinctrl_usbhub: usbhubgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
>> + >;
>> + };
>> +
>> + pinctrl_pcie: pciegrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
>> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
>> + >;
>> + };
>> +
>> + pinctrl_display: dispgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
>> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
>> + >;
>> + };
>> +
>> + pinctrl_usdhc4: usdhc4grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
>> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
>> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
>> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
>> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
>> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
>> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
>> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
>> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
>> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
>> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
>> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
>> + >;
>> + };
>> +
>> + pinctrl_ecspi1: ecspi1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
>> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
>> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
>> + >;
>> + };
>> +
>> + pinctrl_ecspi5: ecspi5rp-1 {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
>> + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
>> + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
>> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
>> + >;
>> + };
>> +
>> + pinctrl_pwm1: pwm1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_pwm2: pwm2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usbotg: usbotggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_i2c1: i2c1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
>> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_i2c2: i2c2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
>> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_i2c3: i2c3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
>> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_uart3: uart3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
>> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
>> + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_uart4: uart4grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
>> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
>> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
>> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
>> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
>> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
>> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3: usdhc3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
>> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
>> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
>> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
>> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
>> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
>> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
>> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
>> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3_reset: usdhc3grp-reset {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
>> + >;
>> + };
>> +
>> + pinctrl_audmux: audmux {
>> + fsl,pins = <
>> + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
>> + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
>> + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
>> + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
>> + >;
>> + };
>> +
>> + pinctrl_enet: pinctrl_enet {
>> + fsl,pins = <
>> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
>> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
>> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
>> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
>> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
>> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
>> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
>> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
>> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
>> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
>> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
>> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
>> + >;
>> + };
>> + };
>> +};
>> +
>> +&pcie {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pcie>;
>> + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> +
>> +&pwm1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm1>;
>> + status = "okay";
>> +};
>> +
>> +&pwm2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm2>;
>> + status = "okay";
>> +};
>> +
>> +&sata {
>> + status = "okay";
>> +};
>> +
>> +&ssi1 {
>> + fsl,mode = "i2s-master";
>> + status = "okay";
>> +};
>> +
>> +&uart3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart3>;
>> + fsl,uart-has-rtscts;
>> + status = "okay";
>> +};
>> +
>> +&uart4 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart4>;
>> + status = "okay";
>> +};
>> +
>> +&usbh1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usbhub>;
>> + vbus-supply = <®_usb_h1_vbus>;
>> + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> +&usbotg {
>> + vbus-supply = <®_usb_otg_vbus>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usbotg>;
>> + disable-over-current;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
>> + no-1-8-v;
>> + keep-power-in-suspend;
>> + enable-sdio-wakeup;
>> + status = "okay";
>> +};
>> +
>> +&usdhc3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
>> + bus-width = <8>;
>> + vmmc-supply = <&vdd_bperi>;
>> + vqmmc-supply = <&vdd_bio>;
>> + non-removable;
>> + keep-power-in-suspend;
>> + status = "okay";
>> +};
>> +
>> +&wdog1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_wdog>;
>> +};
>
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^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 4/7] ARM: dts: imx: Add support for Advantech/GE Bx50v3
2015-11-10 18:00 ` Akshay Bhat
@ 2015-11-10 18:00 ` Akshay Bhat
-1 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: linux-arm-kernel
From: Justin Waters <justin.waters@timesys.com>
Advantech has 3 carrier boards (B450v3, B650v3, B850v3) which use
the Advantech BA-16 module (based on iMX6D). This file has the
devicetree entries that are common to all 3 boards.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/imx6q-bx50v3.dtsi | 211 ++++++++++++++++++++++++++++++++++++
1 file changed, 211 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-bx50v3.dtsi
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
new file mode 100644
index 0000000..2715cd9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -0,0 +1,211 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q-ba16.dtsi"
+
+/ {
+ regulators {
+ /* regulator for wl18xx on sdhc4 */
+ wl18xx_vmmc: regulator at 6 {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1807";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ reg_wlan: regulator at 7 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V_wlan";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx6q-ba16-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6q-ba16-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <4>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mclk: clock at 0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ };
+ };
+};
+
+&i2c1 {
+ pca9547: mux at 70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux_i2c3: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ ads7830: ads7830 at 48 {
+ compatible = "ti,ads7830";
+ reg = <0x48>;
+ };
+
+ mma8453: mma8453 at 1c {
+ compatible = "fsl,mma8453";
+ reg = <0x1c>;
+ };
+ };
+
+ mux_i2c4: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+
+ eeprom: eeprom at 50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ };
+
+ mpl3115: mpl3115 at 60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
+ };
+
+ mux_i2c5: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ mux_i2c6: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ codec: sgtl5000 at 0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&mclk>;
+ VDDA-supply = <®_1p8v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+ };
+
+ mux_i2c7: i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ pca9539: pca9539 at 74 {
+ compatible = "nxp,pca9539";
+ reg = <0x74>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio2>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ mux_i2c8: i2c at 5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+
+ igb at 49 {
+ compatible = "intel,igb";
+ reg = <0x49>;
+ };
+
+ igb at 61 {
+ compatible = "intel,igb";
+ reg = <0x61>;
+ };
+ };
+
+ mux_i2c9: i2c at 6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
+
+ mux_i2c10: i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7>;
+ };
+ };
+};
+
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <4>;
+ vmmc-supply = <&wl18xx_vmmc>;
+ no-1-8-v;
+ non-removable;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ cap-power-off-card;
+ max-frequency = <25000000>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore at 0 {
+ compatible = "ti,wl1837";
+ reg = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+&ecspi5 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi5>;
+ status = "okay";
+
+ m25_eeprom: m25p80 at 0 {
+ compatible = "atmel,at25";
+ spi-max-frequency = <20000000>;
+ size = <0x8000>;
+ pagesize = <64>;
+ reg = <0>;
+ address-width = <16>;
+ };
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 4/7] ARM: dts: imx: Add support for Advantech/GE Bx50v3
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: devicetree
Cc: mark.rutland, justin.waters, linux, Akshay Bhat, ijc+devicetree,
robh+dt, peter.stretz, kernel, galak, l.stach, shawnguo,
linux-arm-kernel, martin.donnelly
From: Justin Waters <justin.waters@timesys.com>
Advantech has 3 carrier boards (B450v3, B650v3, B850v3) which use
the Advantech BA-16 module (based on iMX6D). This file has the
devicetree entries that are common to all 3 boards.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/imx6q-bx50v3.dtsi | 211 ++++++++++++++++++++++++++++++++++++
1 file changed, 211 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-bx50v3.dtsi
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
new file mode 100644
index 0000000..2715cd9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -0,0 +1,211 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q-ba16.dtsi"
+
+/ {
+ regulators {
+ /* regulator for wl18xx on sdhc4 */
+ wl18xx_vmmc: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1807";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ reg_wlan: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V_wlan";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx6q-ba16-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6q-ba16-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <4>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mclk: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ };
+ };
+};
+
+&i2c1 {
+ pca9547: mux@70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux_i2c3: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ ads7830: ads7830@48 {
+ compatible = "ti,ads7830";
+ reg = <0x48>;
+ };
+
+ mma8453: mma8453@1c {
+ compatible = "fsl,mma8453";
+ reg = <0x1c>;
+ };
+ };
+
+ mux_i2c4: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ };
+
+ mpl3115: mpl3115@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
+ };
+
+ mux_i2c5: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ mux_i2c6: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&mclk>;
+ VDDA-supply = <®_1p8v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+ };
+
+ mux_i2c7: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ pca9539: pca9539@74 {
+ compatible = "nxp,pca9539";
+ reg = <0x74>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio2>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ mux_i2c8: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+
+ igb@49 {
+ compatible = "intel,igb";
+ reg = <0x49>;
+ };
+
+ igb@61 {
+ compatible = "intel,igb";
+ reg = <0x61>;
+ };
+ };
+
+ mux_i2c9: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
+
+ mux_i2c10: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7>;
+ };
+ };
+};
+
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <4>;
+ vmmc-supply = <&wl18xx_vmmc>;
+ no-1-8-v;
+ non-removable;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ cap-power-off-card;
+ max-frequency = <25000000>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@0 {
+ compatible = "ti,wl1837";
+ reg = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+&ecspi5 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi5>;
+ status = "okay";
+
+ m25_eeprom: m25p80@0 {
+ compatible = "atmel,at25";
+ spi-max-frequency = <20000000>;
+ size = <0x8000>;
+ pagesize = <64>;
+ reg = <0>;
+ address-width = <16>;
+ };
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 5/7] ARM: dts: imx: Add support for Advantech/GE B450v3
2015-11-10 18:00 ` Akshay Bhat
@ 2015-11-10 18:00 ` Akshay Bhat
-1 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: linux-arm-kernel
Add support for Advantech/GE B450v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b450v3.dts | 75 ++++++++++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..b3330fe 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -310,6 +310,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-wandboard-revb1.dtb \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
+ imx6q-b450v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
new file mode 100644
index 0000000..919e4a4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "Advantech MX6Q B450V3 QSeven Board";
+ compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ status = "okay";
+
+ lvds0: lvds-channel at 0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: G121X1-L03 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <320>;
+ hfront-porch = <0>;
+ vback-porch = <0>;
+ vfront-porch = <38>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
+ lvds1: lvds-channel at 1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing1>;
+ timing1: G121X1-L03 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <320>;
+ hfront-porch = <0>;
+ vback-porch = <0>;
+ vfront-porch = <38>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 5/7] ARM: dts: imx: Add support for Advantech/GE B450v3
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: devicetree
Cc: mark.rutland, justin.waters, linux, Akshay Bhat, ijc+devicetree,
robh+dt, peter.stretz, kernel, galak, l.stach, shawnguo,
linux-arm-kernel, martin.donnelly
Add support for Advantech/GE B450v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b450v3.dts | 75 ++++++++++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..b3330fe 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -310,6 +310,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-wandboard-revb1.dtb \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
+ imx6q-b450v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
new file mode 100644
index 0000000..919e4a4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "Advantech MX6Q B450V3 QSeven Board";
+ compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: G121X1-L03 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <320>;
+ hfront-porch = <0>;
+ vback-porch = <0>;
+ vfront-porch = <38>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
+ lvds1: lvds-channel@1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing1>;
+ timing1: G121X1-L03 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <320>;
+ hfront-porch = <0>;
+ vback-porch = <0>;
+ vfront-porch = <38>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 5/7] ARM: dts: imx: Add support for Advantech/GE B450v3
@ 2015-11-16 11:19 ` Lucas Stach
0 siblings, 0 replies; 26+ messages in thread
From: Lucas Stach @ 2015-11-16 11:19 UTC (permalink / raw)
To: linux-arm-kernel
Am Dienstag, den 10.11.2015, 13:00 -0500 schrieb Akshay Bhat:
> Add support for Advantech/GE B450v3 board.
>
> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/imx6q-b450v3.dts | 75 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 76 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 30bbc37..b3330fe 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -310,6 +310,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> imx6dl-wandboard-revb1.dtb \
> imx6q-apf6dev.dtb \
> imx6q-arm2.dtb \
> + imx6q-b450v3.dtb \
> imx6q-cm-fx6.dtb \
> imx6q-cubox-i.dtb \
> imx6q-dfi-fs700-m60.dtb \
> diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
> new file mode 100644
> index 0000000..919e4a4
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-b450v3.dts
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright 2015 Timesys Corporation.
> + * Copyright 2015 General Electric Company
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6q-bx50v3.dtsi"
> +
> +/ {
> + model = "Advantech MX6Q B450V3 QSeven Board";
> + compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
> +
> + chosen {
> + stdout-path = &uart3;
> + };
> +};
> +
> +&ldb {
> + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> + <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
> + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
> + <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> + status = "okay";
> +
> + lvds0: lvds-channel at 0 {
> + fsl,data-mapping = "spwg";
> + fsl,data-width = <24>;
> + status = "okay";
> +
> + display-timings {
> + native-mode = <&timing0>;
> + timing0: G121X1-L03 {
> + clock-frequency = <65000000>;
> + hactive = <1024>;
> + vactive = <768>;
> + hback-porch = <320>;
> + hfront-porch = <0>;
> + vback-porch = <0>;
> + vfront-porch = <38>;
> + hsync-len = <1>;
> + vsync-len = <1>;
> + };
> + };
Display timings in DT are deprecated and new boards should add the
display with a specific compatible to the simple-panel driver and then
link a panel node to the LVDS channels. Take a look at the i.MX6
Nitrogen DTs for an example on how to do this.
Same comment applies to the next patches as well.
> + };
> +
> + lvds1: lvds-channel at 1 {
> + fsl,data-mapping = "spwg";
> + fsl,data-width = <24>;
> + status = "okay";
> +
> + display-timings {
> + native-mode = <&timing1>;
> + timing1: G121X1-L03 {
> + clock-frequency = <65000000>;
> + hactive = <1024>;
> + vactive = <768>;
> + hback-porch = <320>;
> + hfront-porch = <0>;
> + vback-porch = <0>;
> + vfront-porch = <38>;
> + hsync-len = <1>;
> + vsync-len = <1>;
> + };
> + };
> + };
> +
> +};
--
Pengutronix e.K. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v3 5/7] ARM: dts: imx: Add support for Advantech/GE B450v3
@ 2015-11-16 11:19 ` Lucas Stach
0 siblings, 0 replies; 26+ messages in thread
From: Lucas Stach @ 2015-11-16 11:19 UTC (permalink / raw)
To: Akshay Bhat
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ, martin.donnelly-JJi787mZWgc,
peter.stretz-ELdSlb/RfAS1Z/+hSey0Gg
Am Dienstag, den 10.11.2015, 13:00 -0500 schrieb Akshay Bhat:
> Add support for Advantech/GE B450v3 board.
>
> Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/imx6q-b450v3.dts | 75 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 76 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 30bbc37..b3330fe 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -310,6 +310,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> imx6dl-wandboard-revb1.dtb \
> imx6q-apf6dev.dtb \
> imx6q-arm2.dtb \
> + imx6q-b450v3.dtb \
> imx6q-cm-fx6.dtb \
> imx6q-cubox-i.dtb \
> imx6q-dfi-fs700-m60.dtb \
> diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
> new file mode 100644
> index 0000000..919e4a4
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-b450v3.dts
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright 2015 Timesys Corporation.
> + * Copyright 2015 General Electric Company
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6q-bx50v3.dtsi"
> +
> +/ {
> + model = "Advantech MX6Q B450V3 QSeven Board";
> + compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
> +
> + chosen {
> + stdout-path = &uart3;
> + };
> +};
> +
> +&ldb {
> + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> + <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
> + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
> + <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> + status = "okay";
> +
> + lvds0: lvds-channel@0 {
> + fsl,data-mapping = "spwg";
> + fsl,data-width = <24>;
> + status = "okay";
> +
> + display-timings {
> + native-mode = <&timing0>;
> + timing0: G121X1-L03 {
> + clock-frequency = <65000000>;
> + hactive = <1024>;
> + vactive = <768>;
> + hback-porch = <320>;
> + hfront-porch = <0>;
> + vback-porch = <0>;
> + vfront-porch = <38>;
> + hsync-len = <1>;
> + vsync-len = <1>;
> + };
> + };
Display timings in DT are deprecated and new boards should add the
display with a specific compatible to the simple-panel driver and then
link a panel node to the LVDS channels. Take a look at the i.MX6
Nitrogen DTs for an example on how to do this.
Same comment applies to the next patches as well.
> + };
> +
> + lvds1: lvds-channel@1 {
> + fsl,data-mapping = "spwg";
> + fsl,data-width = <24>;
> + status = "okay";
> +
> + display-timings {
> + native-mode = <&timing1>;
> + timing1: G121X1-L03 {
> + clock-frequency = <65000000>;
> + hactive = <1024>;
> + vactive = <768>;
> + hback-porch = <320>;
> + hfront-porch = <0>;
> + vback-porch = <0>;
> + vfront-porch = <38>;
> + hsync-len = <1>;
> + vsync-len = <1>;
> + };
> + };
> + };
> +
> +};
--
Pengutronix e.K. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
--
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^ permalink raw reply [flat|nested] 26+ messages in thread* [PATCH v3 5/7] ARM: dts: imx: Add support for Advantech/GE B450v3
@ 2015-12-02 18:34 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-12-02 18:34 UTC (permalink / raw)
To: linux-arm-kernel
On 11/16/2015 06:19 AM, Lucas Stach wrote:
> Am Dienstag, den 10.11.2015, 13:00 -0500 schrieb Akshay Bhat:
>> Add support for Advantech/GE B450v3 board.
>>
>> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/imx6q-b450v3.dts | 75 ++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 76 insertions(+)
>> create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 30bbc37..b3330fe 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -310,6 +310,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
>> imx6dl-wandboard-revb1.dtb \
>> imx6q-apf6dev.dtb \
>> imx6q-arm2.dtb \
>> + imx6q-b450v3.dtb \
>> imx6q-cm-fx6.dtb \
>> imx6q-cubox-i.dtb \
>> imx6q-dfi-fs700-m60.dtb \
>> diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
>> new file mode 100644
>> index 0000000..919e4a4
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6q-b450v3.dts
>> @@ -0,0 +1,75 @@
>> +/*
>> + * Copyright 2015 Timesys Corporation.
>> + * Copyright 2015 General Electric Company
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "imx6q-bx50v3.dtsi"
>> +
>> +/ {
>> + model = "Advantech MX6Q B450V3 QSeven Board";
>> + compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
>> +
>> + chosen {
>> + stdout-path = &uart3;
>> + };
>> +};
>> +
>> +&ldb {
>> + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
>> + <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
>> + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
>> + <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
>> + status = "okay";
>> +
>> + lvds0: lvds-channel at 0 {
>> + fsl,data-mapping = "spwg";
>> + fsl,data-width = <24>;
>> + status = "okay";
>> +
>> + display-timings {
>> + native-mode = <&timing0>;
>> + timing0: G121X1-L03 {
>> + clock-frequency = <65000000>;
>> + hactive = <1024>;
>> + vactive = <768>;
>> + hback-porch = <320>;
>> + hfront-porch = <0>;
>> + vback-porch = <0>;
>> + vfront-porch = <38>;
>> + hsync-len = <1>;
>> + vsync-len = <1>;
>> + };
>> + };
>
> Display timings in DT are deprecated and new boards should add the
> display with a specific compatible to the simple-panel driver and then
> link a panel node to the LVDS channels. Take a look at the i.MX6
> Nitrogen DTs for an example on how to do this.
>
> Same comment applies to the next patches as well.
Thanks for the example Lucas. Added G121X1-L03 panel which is now in
linux-next
(https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/drivers/gpu/drm/panel?h=next-20151127&id=f8fa17ba812b7df1535f6bb75d7264670f5997a6)
v4 patch now uses simple-panel:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390373.html
>
>> + };
>> +
>> + lvds1: lvds-channel at 1 {
>> + fsl,data-mapping = "spwg";
>> + fsl,data-width = <24>;
>> + status = "okay";
>> +
>> + display-timings {
>> + native-mode = <&timing1>;
>> + timing1: G121X1-L03 {
>> + clock-frequency = <65000000>;
>> + hactive = <1024>;
>> + vactive = <768>;
>> + hback-porch = <320>;
>> + hfront-porch = <0>;
>> + vback-porch = <0>;
>> + vfront-porch = <38>;
>> + hsync-len = <1>;
>> + vsync-len = <1>;
>> + };
>> + };
>> + };
>> +
>> +};
>
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v3 5/7] ARM: dts: imx: Add support for Advantech/GE B450v3
@ 2015-12-02 18:34 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-12-02 18:34 UTC (permalink / raw)
To: Lucas Stach
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ, martin.donnelly-JJi787mZWgc,
peter.stretz-ELdSlb/RfAS1Z/+hSey0Gg
On 11/16/2015 06:19 AM, Lucas Stach wrote:
> Am Dienstag, den 10.11.2015, 13:00 -0500 schrieb Akshay Bhat:
>> Add support for Advantech/GE B450v3 board.
>>
>> Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/imx6q-b450v3.dts | 75 ++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 76 insertions(+)
>> create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 30bbc37..b3330fe 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -310,6 +310,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
>> imx6dl-wandboard-revb1.dtb \
>> imx6q-apf6dev.dtb \
>> imx6q-arm2.dtb \
>> + imx6q-b450v3.dtb \
>> imx6q-cm-fx6.dtb \
>> imx6q-cubox-i.dtb \
>> imx6q-dfi-fs700-m60.dtb \
>> diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
>> new file mode 100644
>> index 0000000..919e4a4
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6q-b450v3.dts
>> @@ -0,0 +1,75 @@
>> +/*
>> + * Copyright 2015 Timesys Corporation.
>> + * Copyright 2015 General Electric Company
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "imx6q-bx50v3.dtsi"
>> +
>> +/ {
>> + model = "Advantech MX6Q B450V3 QSeven Board";
>> + compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
>> +
>> + chosen {
>> + stdout-path = &uart3;
>> + };
>> +};
>> +
>> +&ldb {
>> + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
>> + <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
>> + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
>> + <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
>> + status = "okay";
>> +
>> + lvds0: lvds-channel@0 {
>> + fsl,data-mapping = "spwg";
>> + fsl,data-width = <24>;
>> + status = "okay";
>> +
>> + display-timings {
>> + native-mode = <&timing0>;
>> + timing0: G121X1-L03 {
>> + clock-frequency = <65000000>;
>> + hactive = <1024>;
>> + vactive = <768>;
>> + hback-porch = <320>;
>> + hfront-porch = <0>;
>> + vback-porch = <0>;
>> + vfront-porch = <38>;
>> + hsync-len = <1>;
>> + vsync-len = <1>;
>> + };
>> + };
>
> Display timings in DT are deprecated and new boards should add the
> display with a specific compatible to the simple-panel driver and then
> link a panel node to the LVDS channels. Take a look at the i.MX6
> Nitrogen DTs for an example on how to do this.
>
> Same comment applies to the next patches as well.
Thanks for the example Lucas. Added G121X1-L03 panel which is now in
linux-next
(https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/drivers/gpu/drm/panel?h=next-20151127&id=f8fa17ba812b7df1535f6bb75d7264670f5997a6)
v4 patch now uses simple-panel:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390373.html
>
>> + };
>> +
>> + lvds1: lvds-channel@1 {
>> + fsl,data-mapping = "spwg";
>> + fsl,data-width = <24>;
>> + status = "okay";
>> +
>> + display-timings {
>> + native-mode = <&timing1>;
>> + timing1: G121X1-L03 {
>> + clock-frequency = <65000000>;
>> + hactive = <1024>;
>> + vactive = <768>;
>> + hback-porch = <320>;
>> + hfront-porch = <0>;
>> + vback-porch = <0>;
>> + vfront-porch = <38>;
>> + hsync-len = <1>;
>> + vsync-len = <1>;
>> + };
>> + };
>> + };
>> +
>> +};
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 6/7] ARM: dts: imx: Add support for Advantech/GE B650v3
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: linux-arm-kernel
Add support for Advantech/GE B650v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b650v3.dts | 74 ++++++++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b650v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b3330fe..e2df9f8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -311,6 +311,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
+ imx6q-b650v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
new file mode 100644
index 0000000..fa9e0e0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "Advantech MX6Q B650V3 QSeven Board";
+ compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ status = "okay";
+
+ lvds0: lvds-channel at 0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: G121X1-L03 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <320>;
+ hfront-porch = <0>;
+ vback-porch = <0>;
+ vfront-porch = <38>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
+ lvds1: lvds-channel at 1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing1>;
+ timing1: G121X1-L03 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <320>;
+ hfront-porch = <0>;
+ vback-porch = <0>;
+ vfront-porch = <38>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ };
+ };
+ };
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 6/7] ARM: dts: imx: Add support for Advantech/GE B650v3
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ, martin.donnelly-JJi787mZWgc,
peter.stretz-ELdSlb/RfAS1Z/+hSey0Gg,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
Add support for Advantech/GE B650v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b650v3.dts | 74 ++++++++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b650v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b3330fe..e2df9f8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -311,6 +311,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
+ imx6q-b650v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
new file mode 100644
index 0000000..fa9e0e0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "Advantech MX6Q B650V3 QSeven Board";
+ compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: G121X1-L03 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <320>;
+ hfront-porch = <0>;
+ vback-porch = <0>;
+ vfront-porch = <38>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
+ lvds1: lvds-channel@1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing1>;
+ timing1: G121X1-L03 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <320>;
+ hfront-porch = <0>;
+ vback-porch = <0>;
+ vfront-porch = <38>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ };
+ };
+ };
+};
--
2.6.3
--
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^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 7/7] ARM: dts: imx: Add support for Advantech/GE B850v3
2015-11-10 18:00 ` Akshay Bhat
@ 2015-11-10 18:00 ` Akshay Bhat
-1 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: linux-arm-kernel
Add support for Advantech/GE B850v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b850v3.dts | 122 +++++++++++++++++++++++++++++++++++++
2 files changed, 123 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b850v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e2df9f8..7ad1eb8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -312,6 +312,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
imx6q-b650v3.dtb \
+ imx6q-b850v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
new file mode 100644
index 0000000..2dbcf71
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "Advantech MX6Q B850V3 QSeven Board";
+ compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ fsl,dual-channel;
+ status = "okay";
+
+ lvds0: lvds-channel at 0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: stdp4028 {
+ clock-frequency = <137143857>;
+ hactive = <1920>;
+ vactive = <1080>;
+ hback-porch = <100>;
+ hfront-porch = <40>;
+ vback-porch = <30>;
+ vfront-porch = <3>;
+ hsync-len = <10>;
+ vsync-len = <2>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pca9547_ddc: mux at 70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux_i2c11: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ };
+
+ mux_i2c12: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ };
+
+ mux_i2c13: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ mux_i2c14: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+ };
+
+ mux_i2c15: i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+ };
+
+ mux_i2c16: i2c at 5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+ };
+
+ mux_i2c17: i2c at 6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
+
+ mux_i2c18: i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7>;
+ };
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&mux_i2c11>;
+};
+
+&mux_i2c3 {
+ ads7830_2: ads7830 at 4a {
+ compatible = "ti,ads7830";
+ reg = <0x4a>;
+ };
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 7/7] ARM: dts: imx: Add support for Advantech/GE B850v3
@ 2015-11-10 18:00 ` Akshay Bhat
0 siblings, 0 replies; 26+ messages in thread
From: Akshay Bhat @ 2015-11-10 18:00 UTC (permalink / raw)
To: devicetree
Cc: mark.rutland, justin.waters, linux, Akshay Bhat, ijc+devicetree,
robh+dt, peter.stretz, kernel, galak, l.stach, shawnguo,
linux-arm-kernel, martin.donnelly
Add support for Advantech/GE B850v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b850v3.dts | 122 +++++++++++++++++++++++++++++++++++++
2 files changed, 123 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b850v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e2df9f8..7ad1eb8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -312,6 +312,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
imx6q-b650v3.dtb \
+ imx6q-b850v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
new file mode 100644
index 0000000..2dbcf71
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "Advantech MX6Q B850V3 QSeven Board";
+ compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ fsl,dual-channel;
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: stdp4028 {
+ clock-frequency = <137143857>;
+ hactive = <1920>;
+ vactive = <1080>;
+ hback-porch = <100>;
+ hfront-porch = <40>;
+ vback-porch = <30>;
+ vfront-porch = <3>;
+ hsync-len = <10>;
+ vsync-len = <2>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pca9547_ddc: mux@70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux_i2c11: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ };
+
+ mux_i2c12: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ };
+
+ mux_i2c13: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ mux_i2c14: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+ };
+
+ mux_i2c15: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+ };
+
+ mux_i2c16: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+ };
+
+ mux_i2c17: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
+
+ mux_i2c18: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7>;
+ };
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&mux_i2c11>;
+};
+
+&mux_i2c3 {
+ ads7830_2: ads7830@4a {
+ compatible = "ti,ads7830";
+ reg = <0x4a>;
+ };
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 26+ messages in thread