Re: [PATCH (v6) 1/2] mtd: brcmnand: Add brcm,bcm63268-nand device tree binding

[Simon Arlott <simon@fire.lp0.eu>]

On 02/12/15 19:38, Florian Fainelli wrote:
> 2015-12-02 11:05 GMT-08:00 Brian Norris <computersforpeace@gmail.com>:
>> + Broadcom list + Kamal
>>
>> On Tue, Nov 24, 2015 at 08:19:37PM -0000, Simon Arlott wrote:
>>> Add device tree binding for NAND on the BCM63268.
>>>
>>> The BCM63268 has a NAND interrupt register with combined status and enable
>>> registers.
>>>
>>> Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
>>> ---
>>>  .../devicetree/bindings/mtd/brcm,brcmnand.txt      | 35 ++++++++++++++++++++++
>>>  1 file changed, 35 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
>>> b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
>>> index 4ff7128..f2a71c8 100644
>>> --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
>>> +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
>>> @@ -72,6 +72,14 @@ we define additional 'compatible' properties and associated register resources w
>>>         and enable registers
>>>       - reg-names: (required) "nand-int-base"
>>>
>>> +   * "brcm,nand-bcm63268"
>>> +     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm63268"
>>
>> Looks like you're aiming to support bcm63168? Is bcm63268 the first
>> chip to include this style of register then? The numbering seems
>> backwards, but that may just be reality.
> 
> 6362 (NAND rev 2.1, ann. Sep 8, 2009), 6368 (v0.1?!?, ann. Jan 7,
> 2009) and 6328 (v2.1, can't find release date) are earlier chips that
> have an identical combined interrupt enable + status register and a
> NAND controller within the same 32-bits word, so these would qualify
> as a better compatible string for this specific addition integration
> stub here. I would gowith 6368 here then?
> 

I could change it to 6368 but there's no documented NAND_INTR_BASE for
it. Only the 63268 and 6818 have a #define for NAND_INTR_BASE.

-- 
Simon Arlott