[PATCH v4 02/20] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver

[PATCH v4 02/20] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver

[Chanwoo Choi]

This patch adds the documentation for generic exynos bus frequency
driver.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
 .../devicetree/bindings/devfreq/exynos-bus.txt     | 93 ++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt

diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
new file mode 100644
index 000000000000..e32daef328da
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -0,0 +1,93 @@
+* Generic Exynos Bus frequency device
+
+The Samsung Exynos SoC have many buses for data transfer between DRAM
+and sub-blocks in SoC. Almost Exynos SoC have the common architecture
+for buses. Generally, the each bus of Exynos SoC includes the source clock
+and power line and then is able to change the clock according to the usage
+of each buses on runtime. When gathering the usage of each buses on runtime,
+the driver uses the PPMU (Platform Performance Monitoring Unit) which
+is able to measure the current load of sub-blocks.
+
+There are a little different composition among Exynos SoC because each Exynos
+SoC has the different sub-blocks. So, this difference should be specified
+in devicetree file instead of each device driver. In result, this driver
+is able to support the bus frequency for all Exynos SoCs.
+
+Required properties for bus device:
+- compatible: Should be "samsung,exynos-bus".
+- clock-names : the name of clock used by the bus, "bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- operating-points-v2: the OPP table including frequency/voltage information
+  to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- vdd-supply: the regulator to provide the buses with the voltage.
+- devfreq-events: the devfreq-event device to monitor the current utilization
+  of buses.
+
+Optional properties for bus device:
+- exynos,saturation-ratio: the percentage value which is used to calibrate
+                   the performance count against total cycle count.
+
+Example1:
+	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
+	power line (regulator). The MIF (Memory Interface) AXI bus is used to
+	transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
+
+	- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
+
+	- MIF bus's frequency/voltage table
+	-----------------------
+	|Lv| Freq   | Voltage |
+	-----------------------
+	|L1| 50000  |800000   |
+	|L2| 100000 |800000   |
+	|L3| 134000 |800000   |
+	|L4| 200000 |825000   |
+	|L5| 400000 |875000   |
+	-----------------------
+
+Example2 :
+	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
+	is listed below:
+
+	bus_dmc: bus_dmc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu_dmc CLK_DIV_DMC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_dmc_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@50000000 {
+			opp-hz = /bits/ 64 <50000000>;
+			opp-microvolt = <800000>;
+		};
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <800000>;
+		};
+		opp@134000000 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <800000>;
+		};
+		opp@200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <825000>;
+		};
+		opp@400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <875000>;
+		};
+	};
+
+	Usage case to handle the frequency and voltage of bus on runtime
+	in exynos3250-rinato.dts is listed below:
+
+	&bus_dmc {
+		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+		vdd-supply = <&buck1_reg>;	/* VDD_MIF */
+		status = "okay";
+	};
-- 
1.9.1

Re: [PATCH v4 02/20] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver

[MyungJoo Ham]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=utf-8, Size: 2387 bytes --]

>   
>  This patch adds the documentation for generic exynos bus frequency
> driver.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

A little changes following:

> ---
>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 93 ++++++++++++++++++++++
>  1 file changed, 93 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> new file mode 100644
> index 000000000000..e32daef328da
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> @@ -0,0 +1,93 @@
> +* Generic Exynos Bus frequency device
> +
> +The Samsung Exynos SoC have many buses for data transfer between DRAM

+The Samsung Exynos SoC has many buses for data transfer between DRAM

or

+The Samsung Exynos SoCs have many buses for data transfer between DRAM
(because you intend to support mulitple Exynos SoCs)

> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture

+and sub-blocks in SoC. Most Exynos SoCs share the common architecture

> +for buses. Generally, the each bus of Exynos SoC includes the source clock

+for buses. Generally, each bus of Exynos SoC includes a source clock

> +and power line and then is able to change the clock according to the usage

+and a power line, which are able to change the clock frequency 

> +of each buses on runtime. When gathering the usage of each buses on runtime,

+of the bus in runtime. To monitor the usage of each bus in runtime,

> +the driver uses the PPMU (Platform Performance Monitoring Unit) which

+the driver uses the PPMU (Platform Performance Monitoring Unit), which

> +is able to measure the current load of sub-blocks.
> +
> +There are a little different composition among Exynos SoC because each Exynos
> +SoC has the different sub-blocks. So, this difference should be specified

+SoC has different sub-blocks. Therefore, such difference should be specified

> +in devicetree file instead of each device driver. In result, this driver
> +is able to support the bus frequency for all Exynos SoCs.
> +
[]
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Re: [PATCH v4 02/20] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver

[MyungJoo Ham]

>   
>  This patch adds the documentation for generic exynos bus frequency
> driver.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

A little changes following:

> ---
>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 93 ++++++++++++++++++++++
>  1 file changed, 93 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> new file mode 100644
> index 000000000000..e32daef328da
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> @@ -0,0 +1,93 @@
> +* Generic Exynos Bus frequency device
> +
> +The Samsung Exynos SoC have many buses for data transfer between DRAM

+The Samsung Exynos SoC has many buses for data transfer between DRAM

or

+The Samsung Exynos SoCs have many buses for data transfer between DRAM
(because you intend to support mulitple Exynos SoCs)

> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture

+and sub-blocks in SoC. Most Exynos SoCs share the common architecture

> +for buses. Generally, the each bus of Exynos SoC includes the source clock

+for buses. Generally, each bus of Exynos SoC includes a source clock

> +and power line and then is able to change the clock according to the usage

+and a power line, which are able to change the clock frequency 

> +of each buses on runtime. When gathering the usage of each buses on runtime,

+of the bus in runtime. To monitor the usage of each bus in runtime,

> +the driver uses the PPMU (Platform Performance Monitoring Unit) which

+the driver uses the PPMU (Platform Performance Monitoring Unit), which

> +is able to measure the current load of sub-blocks.
> +
> +There are a little different composition among Exynos SoC because each Exynos
> +SoC has the different sub-blocks. So, this difference should be specified

+SoC has different sub-blocks. Therefore, such difference should be specified

> +in devicetree file instead of each device driver. In result, this driver
> +is able to support the bus frequency for all Exynos SoCs.
> +
[]

Re: [PATCH v4 02/20] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver

[Chanwoo Choi]

On 2015년 12월 14일 17:40, MyungJoo Ham wrote:
>>   
>>  This patch adds the documentation for generic exynos bus frequency
>> driver.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> 
> A little changes following:
> 
>> ---
>>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 93 ++++++++++++++++++++++
>>  1 file changed, 93 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> new file mode 100644
>> index 000000000000..e32daef328da
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> @@ -0,0 +1,93 @@
>> +* Generic Exynos Bus frequency device
>> +
>> +The Samsung Exynos SoC have many buses for data transfer between DRAM
> 
> +The Samsung Exynos SoC has many buses for data transfer between DRAM
> 
> or
> 
> +The Samsung Exynos SoCs have many buses for data transfer between DRAM
> (because you intend to support mulitple Exynos SoCs)
> 
>> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture
> 
> +and sub-blocks in SoC. Most Exynos SoCs share the common architecture
> 
>> +for buses. Generally, the each bus of Exynos SoC includes the source clock
> 
> +for buses. Generally, each bus of Exynos SoC includes a source clock
> 
>> +and power line and then is able to change the clock according to the usage
> 
> +and a power line, which are able to change the clock frequency 
> 
>> +of each buses on runtime. When gathering the usage of each buses on runtime,
> 
> +of the bus in runtime. To monitor the usage of each bus in runtime,
> 
>> +the driver uses the PPMU (Platform Performance Monitoring Unit) which
> 
> +the driver uses the PPMU (Platform Performance Monitoring Unit), which
> 
>> +is able to measure the current load of sub-blocks.
>> +
>> +There are a little different composition among Exynos SoC because each Exynos
>> +SoC has the different sub-blocks. So, this difference should be specified
> 
> +SoC has different sub-blocks. Therefore, such difference should be specified
> 
>> +in devicetree file instead of each device driver. In result, this driver
>> +is able to support the bus frequency for all Exynos SoCs.
>> +

Okay. I'll modify it.

Regards,
Chanwoo Choi