From: Dirk Behme <dirk.behme@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/3] arm64: dts: r8a7795: Add Cortex-A57 CPU cores
Date: Tue, 15 Dec 2015 06:31:31 +0000 [thread overview]
Message-ID: <566FB3C3.3060504@gmail.com> (raw)
In-Reply-To: <20151215051243.GA29362@verge.net.au>
On 15.12.2015 06:12, Simon Horman wrote:
> On Sat, Dec 12, 2015 at 08:07:51AM +0900, Simon Horman wrote:
>> On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote:
>>> From: Gaku Inami <gaku.inami.xw@bp.renesas.com>
>>>
>>> Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.
>>>
>>> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
>>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>> Sigend-off-by: Dirk Behme <dirk.behme@gmail.com>
>>
>> Thanks, I have queued this up for v4.5.
>
> I meant to test this earlier but somehow it slopped my mind.
>
> With this patch applied I still only see one CPU brought up
> whereas I was expecting 4. Are more patches needed in order to
> get more CPUs operating?
Hmm, I don't think so (?).
I tested this with
https://github.com/dirkbehme/linux-renesas-rcar-gen3/commits/dirk/gen3-latest-update
and got (including the A53 patch)
...
ASID allocator initialised with 65536 entries
Detected PIPT I-cache on CPU1
CPU1: Booted secondary processor [411fd073]
Detected PIPT I-cache on CPU2
CPU2: Booted secondary processor [411fd073]
Detected PIPT I-cache on CPU3
CPU3: Booted secondary processor [411fd073]
Detected VIPT I-cache on CPU4
CPU features: enabling workaround for ARM erratum 845719
CPU4: Booted secondary processor [410fd034]
Detected VIPT I-cache on CPU5
CPU5: Booted secondary processor [410fd034]
Detected VIPT I-cache on CPU6
CPU6: Booted secondary processor [410fd034]
Detected VIPT I-cache on CPU7
CPU7: Booted secondary processor [410fd034]
Brought up 8 CPUs
SMP: Total of 8 processors activated.
CPU: All CPU(s) started at EL1
...
This is based on last weeks renesas-drivers-2015-12-08-v4.4-rc4 and
besides the patches for SDHI/eMMC I don't think it contains anything
additional regarding the number of CPU cores.
Best regards
Dirk
WARNING: multiple messages have this Message-ID (diff)
From: dirk.behme@gmail.com (Dirk Behme)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] arm64: dts: r8a7795: Add Cortex-A57 CPU cores
Date: Tue, 15 Dec 2015 07:31:31 +0100 [thread overview]
Message-ID: <566FB3C3.3060504@gmail.com> (raw)
In-Reply-To: <20151215051243.GA29362@verge.net.au>
On 15.12.2015 06:12, Simon Horman wrote:
> On Sat, Dec 12, 2015 at 08:07:51AM +0900, Simon Horman wrote:
>> On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote:
>>> From: Gaku Inami <gaku.inami.xw@bp.renesas.com>
>>>
>>> Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.
>>>
>>> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
>>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>> Sigend-off-by: Dirk Behme <dirk.behme@gmail.com>
>>
>> Thanks, I have queued this up for v4.5.
>
> I meant to test this earlier but somehow it slopped my mind.
>
> With this patch applied I still only see one CPU brought up
> whereas I was expecting 4. Are more patches needed in order to
> get more CPUs operating?
Hmm, I don't think so (?).
I tested this with
https://github.com/dirkbehme/linux-renesas-rcar-gen3/commits/dirk/gen3-latest-update
and got (including the A53 patch)
...
ASID allocator initialised with 65536 entries
Detected PIPT I-cache on CPU1
CPU1: Booted secondary processor [411fd073]
Detected PIPT I-cache on CPU2
CPU2: Booted secondary processor [411fd073]
Detected PIPT I-cache on CPU3
CPU3: Booted secondary processor [411fd073]
Detected VIPT I-cache on CPU4
CPU features: enabling workaround for ARM erratum 845719
CPU4: Booted secondary processor [410fd034]
Detected VIPT I-cache on CPU5
CPU5: Booted secondary processor [410fd034]
Detected VIPT I-cache on CPU6
CPU6: Booted secondary processor [410fd034]
Detected VIPT I-cache on CPU7
CPU7: Booted secondary processor [410fd034]
Brought up 8 CPUs
SMP: Total of 8 processors activated.
CPU: All CPU(s) started at EL1
...
This is based on last weeks renesas-drivers-2015-12-08-v4.4-rc4 and
besides the patches for SDHI/eMMC I don't think it contains anything
additional regarding the number of CPU cores.
Best regards
Dirk
WARNING: multiple messages have this Message-ID (diff)
From: Dirk Behme <dirk.behme@gmail.com>
To: Simon Horman <horms@verge.net.au>
Cc: linux-sh@vger.kernel.org, geert+renesas@glider.be,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Gaku Inami <gaku.inami.xw@bp.renesas.com>,
Takeshi Kihara <takeshi.kihara.df@renesas.com>
Subject: Re: [PATCH 2/3] arm64: dts: r8a7795: Add Cortex-A57 CPU cores
Date: Tue, 15 Dec 2015 07:31:31 +0100 [thread overview]
Message-ID: <566FB3C3.3060504@gmail.com> (raw)
In-Reply-To: <20151215051243.GA29362@verge.net.au>
On 15.12.2015 06:12, Simon Horman wrote:
> On Sat, Dec 12, 2015 at 08:07:51AM +0900, Simon Horman wrote:
>> On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote:
>>> From: Gaku Inami <gaku.inami.xw@bp.renesas.com>
>>>
>>> Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.
>>>
>>> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
>>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>> Sigend-off-by: Dirk Behme <dirk.behme@gmail.com>
>>
>> Thanks, I have queued this up for v4.5.
>
> I meant to test this earlier but somehow it slopped my mind.
>
> With this patch applied I still only see one CPU brought up
> whereas I was expecting 4. Are more patches needed in order to
> get more CPUs operating?
Hmm, I don't think so (?).
I tested this with
https://github.com/dirkbehme/linux-renesas-rcar-gen3/commits/dirk/gen3-latest-update
and got (including the A53 patch)
...
ASID allocator initialised with 65536 entries
Detected PIPT I-cache on CPU1
CPU1: Booted secondary processor [411fd073]
Detected PIPT I-cache on CPU2
CPU2: Booted secondary processor [411fd073]
Detected PIPT I-cache on CPU3
CPU3: Booted secondary processor [411fd073]
Detected VIPT I-cache on CPU4
CPU features: enabling workaround for ARM erratum 845719
CPU4: Booted secondary processor [410fd034]
Detected VIPT I-cache on CPU5
CPU5: Booted secondary processor [410fd034]
Detected VIPT I-cache on CPU6
CPU6: Booted secondary processor [410fd034]
Detected VIPT I-cache on CPU7
CPU7: Booted secondary processor [410fd034]
Brought up 8 CPUs
SMP: Total of 8 processors activated.
CPU: All CPU(s) started at EL1
...
This is based on last weeks renesas-drivers-2015-12-08-v4.4-rc4 and
besides the patches for SDHI/eMMC I don't think it contains anything
additional regarding the number of CPU cores.
Best regards
Dirk
next prev parent reply other threads:[~2015-12-15 6:31 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-04 13:38 [PATCH 1/3] arm64: dts: r8a7795: Add PSCI node Dirk Behme
2015-12-04 13:38 ` Dirk Behme
2015-12-04 13:38 ` Dirk Behme
2015-12-04 13:38 ` [PATCH 2/3] arm64: dts: r8a7795: Add Cortex-A57 CPU cores Dirk Behme
2015-12-04 13:38 ` Dirk Behme
2015-12-04 13:38 ` Dirk Behme
2015-12-11 23:07 ` Simon Horman
2015-12-11 23:07 ` Simon Horman
2015-12-11 23:07 ` Simon Horman
2015-12-15 5:12 ` Simon Horman
2015-12-15 5:12 ` Simon Horman
2015-12-15 5:12 ` Simon Horman
2015-12-15 6:31 ` Dirk Behme [this message]
2015-12-15 6:31 ` Dirk Behme
2015-12-15 6:31 ` Dirk Behme
2015-12-15 8:23 ` Geert Uytterhoeven
2015-12-15 8:23 ` Geert Uytterhoeven
2015-12-15 8:23 ` Geert Uytterhoeven
2015-12-15 8:38 ` Magnus Damm
2015-12-15 8:38 ` Magnus Damm
2015-12-15 8:38 ` Magnus Damm
2015-12-15 8:48 ` Dirk Behme
2015-12-15 8:48 ` Dirk Behme
2015-12-15 8:48 ` Dirk Behme
2015-12-15 8:55 ` Magnus Damm
2015-12-15 8:55 ` Magnus Damm
2015-12-15 8:55 ` Magnus Damm
2016-03-16 1:19 ` Simon Horman
2016-03-16 1:19 ` Simon Horman
2016-03-16 1:19 ` Simon Horman
2016-03-16 3:45 ` Khiem Nguyen
2016-03-16 3:45 ` Khiem Nguyen
2016-03-16 3:45 ` Khiem Nguyen
2016-03-16 5:36 ` Simon Horman
2016-03-16 5:36 ` Simon Horman
2016-03-16 5:36 ` Simon Horman
2015-12-04 13:38 ` [PATCH 3/3] arm64: dts: r8a7795: Add pmu device nodes Dirk Behme
2015-12-04 13:38 ` Dirk Behme
2015-12-04 13:38 ` Dirk Behme
2015-12-11 23:07 ` Simon Horman
2015-12-11 23:07 ` Simon Horman
2015-12-11 23:07 ` Simon Horman
2015-12-14 14:36 ` Sudeep Holla
2015-12-14 14:36 ` Sudeep Holla
2015-12-14 14:36 ` Sudeep Holla
2015-12-15 8:33 ` Geert Uytterhoeven
2015-12-15 8:33 ` Geert Uytterhoeven
2015-12-15 8:33 ` Geert Uytterhoeven
2015-12-15 9:50 ` Sudeep Holla
2015-12-15 9:50 ` Sudeep Holla
2015-12-15 9:50 ` Sudeep Holla
2015-12-11 23:07 ` [PATCH 1/3] arm64: dts: r8a7795: Add PSCI node Simon Horman
2015-12-11 23:07 ` Simon Horman
2015-12-11 23:07 ` Simon Horman
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