From: walter harms <wharms@bfs.de>
To: Yang Pingchao <pingchao.yang@intel.com>
Cc: herbert@gondor.apana.org.au, dan.carpenter@oracle.com,
tadeusz.struk@intel.com, linux-crypto@vger.kernel.org,
qat-linux@intel.com, kernel-janitors@vger.kernel.org
Subject: Re: [PATCH] crypto: qat - fix CTX_ENABLES bits shift direction issue
Date: Wed, 16 Dec 2015 08:09:34 +0000 [thread overview]
Message-ID: <56711C3E.6070302@bfs.de> (raw)
In-Reply-To: <1450233580-58266-1-git-send-email-pingchao.yang@intel.com>
Am 16.12.2015 03:39, schrieb Yang Pingchao:
> AE CTX bits should be 8-15 in CTX_ENABLES, so the mask
> value 0xff should be left shifted 0x8.
>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> Signed-off-by: Yang Pingchao <pingchao.yang@intel.com>
> ---
> drivers/crypto/qat/qat_common/qat_hal.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c
> index 45c1739..81bd1fe 100644
> --- a/drivers/crypto/qat/qat_common/qat_hal.c
> +++ b/drivers/crypto/qat/qat_common/qat_hal.c
> @@ -418,7 +418,7 @@ int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle,
>
> qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &enable);
> qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &active);
> - if ((enable & (0xff >> CE_ENABLE_BITPOS)) ||
> + if ((enable & (0xff << CE_ENABLE_BITPOS)) ||
> (active & (1 << ACS_ABO_BITPOS)))
> return 1;
> else
Is there any reason for using 0xff << CE_ENABLE_BITPOS instead of 0xff00 ?
re,
wh
WARNING: multiple messages have this Message-ID (diff)
From: walter harms <wharms@bfs.de>
To: Yang Pingchao <pingchao.yang@intel.com>
Cc: herbert@gondor.apana.org.au, dan.carpenter@oracle.com,
tadeusz.struk@intel.com, linux-crypto@vger.kernel.org,
qat-linux@intel.com, kernel-janitors@vger.kernel.org
Subject: Re: [PATCH] crypto: qat - fix CTX_ENABLES bits shift direction issue
Date: Wed, 16 Dec 2015 09:09:34 +0100 [thread overview]
Message-ID: <56711C3E.6070302@bfs.de> (raw)
In-Reply-To: <1450233580-58266-1-git-send-email-pingchao.yang@intel.com>
Am 16.12.2015 03:39, schrieb Yang Pingchao:
> AE CTX bits should be 8-15 in CTX_ENABLES, so the mask
> value 0xff should be left shifted 0x8.
>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> Signed-off-by: Yang Pingchao <pingchao.yang@intel.com>
> ---
> drivers/crypto/qat/qat_common/qat_hal.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c
> index 45c1739..81bd1fe 100644
> --- a/drivers/crypto/qat/qat_common/qat_hal.c
> +++ b/drivers/crypto/qat/qat_common/qat_hal.c
> @@ -418,7 +418,7 @@ int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle,
>
> qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &enable);
> qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &active);
> - if ((enable & (0xff >> CE_ENABLE_BITPOS)) ||
> + if ((enable & (0xff << CE_ENABLE_BITPOS)) ||
> (active & (1 << ACS_ABO_BITPOS)))
> return 1;
> else
Is there any reason for using 0xff << CE_ENABLE_BITPOS instead of 0xff00 ?
re,
wh
next prev parent reply other threads:[~2015-12-16 8:09 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-16 2:39 [PATCH] crypto: qat - fix CTX_ENABLES bits shift direction issue Yang Pingchao
2015-12-16 2:39 ` Yang Pingchao
2015-12-16 8:09 ` walter harms [this message]
2015-12-16 8:09 ` walter harms
2015-12-16 8:22 ` Yang, Pingchao
2015-12-16 8:22 ` Yang, Pingchao
2015-12-22 13:22 ` Herbert Xu
2015-12-22 13:22 ` Herbert Xu
[not found] <1449812574-35124-1-git-send-email-pingchao.yang@intel.com>
2015-12-11 15:22 ` Tadeusz Struk
2015-12-12 5:46 ` Herbert Xu
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