* [U-Boot] [PATCH v2 1/4] mips: add base support for atheros ath79 based SOCs [not found] <1450770285-14566-1-git-send-email-wills.wang@live.com> @ 2015-12-22 7:44 ` Wills Wang 2015-12-22 14:34 ` Daniel Schwierzeck 2015-12-22 7:44 ` [U-Boot] [PATCH v2 2/4] mips: ath79: add spi driver Wills Wang ` (2 subsequent siblings) 3 siblings, 1 reply; 8+ messages in thread From: Wills Wang @ 2015-12-22 7:44 UTC (permalink / raw) To: u-boot This patch enable work for ar933x SOC, tested on ar9331 board. Signed-off-by: Wills Wang <wills.wang@live.com> --- arch/mips/Makefile | 1 + arch/mips/include/asm/arch-ath79/ar71xx_regs.h | 1143 ++++++++++++++++++++++++ arch/mips/include/asm/arch-ath79/ar933x_uart.h | 67 ++ arch/mips/include/asm/arch-ath79/ath79.h | 145 +++ arch/mips/mach-ath79/Makefile | 12 + arch/mips/mach-ath79/ar933x/Makefile | 9 + arch/mips/mach-ath79/ar933x/ddr_tap.S | 272 ++++++ arch/mips/mach-ath79/ar933x/lowlevel_init.S | 534 +++++++++++ arch/mips/mach-ath79/config.mk | 8 + arch/mips/mach-ath79/cpu.c | 274 ++++++ arch/mips/mach-ath79/dram.c | 27 + arch/mips/mach-ath79/reset.c | 55 ++ 12 files changed, 2547 insertions(+) create mode 100644 arch/mips/include/asm/arch-ath79/ar71xx_regs.h create mode 100644 arch/mips/include/asm/arch-ath79/ar933x_uart.h create mode 100644 arch/mips/include/asm/arch-ath79/ath79.h create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/ddr_tap.S create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/config.mk create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/reset.c diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 43f0f5c..e2dd729 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/ +libs-$(CONFIG_SOC_ATH79) += arch/mips/mach-ath79/ diff --git a/arch/mips/include/asm/arch-ath79/ar71xx_regs.h b/arch/mips/include/asm/arch-ath79/ar71xx_regs.h new file mode 100644 index 0000000..56c0d36 --- /dev/null +++ b/arch/mips/include/asm/arch-ath79/ar71xx_regs.h @@ -0,0 +1,1143 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) +#define AR933X_RTC_SIZE 0x1000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 +#define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR933X_SRIF_SIZE 0x1000 + +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 +#define AR934X_NFC_BASE 0x1b000200 +#define AR934X_NFC_SIZE 0xb8 +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 + +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA953X_GMAC_SIZE 0x14 +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA953X_WMAC_SIZE 0x20000 +#define QCA953X_EHCI_BASE 0x1b000000 +#define QCA953X_EHCI_SIZE 0x200 +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define QCA953X_SRIF_SIZE 0x1000 + +#define QCA953X_PCI_CFG_BASE0 0x14000000 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA953X_PCI_MEM_BASE0 0x10000000 +#define QCA953X_PCI_MEM_SIZE 0x02000000 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 + +#define QCA956X_PCI_MEM_BASE1 0x12000000 +#define QCA956X_PCI_MEM_SIZE 0x02000000 +#define QCA956X_PCI_CFG_BASE1 0x16000000 +#define QCA956X_PCI_CFG_SIZE 0x1000 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA956X_PCI_CRP_SIZE 0x1000 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA956X_PCI_CTRL_SIZE 0x100 + +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA956X_WMAC_SIZE 0x20000 +#define QCA956X_EHCI0_BASE 0x1b000000 +#define QCA956X_EHCI1_BASE 0x1b400000 +#define QCA956X_EHCI_SIZE 0x200 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA956X_GMAC_SIZE 0x64 + +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 +#define AR9300_OTP_STATUS_TYPE 0x7 +#define AR9300_OTP_STATUS_VALID 0x4 +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 +#define AR9300_OTP_STATUS_SM_BUSY 0x1 +#define AR9300_OTP_READ_DATA 0x15f1c + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_CONFIG 0x00 +#define AR71XX_DDR_REG_CONFIG2 0x04 +#define AR71XX_DDR_REG_MODE 0x08 +#define AR71XX_DDR_REG_EMR 0x0c +#define AR71XX_DDR_REG_CONTROL 0x10 +#define AR71XX_DDR_REG_REFRESH 0x14 +#define AR71XX_DDR_REG_RD_CYCLE 0x18 +#define AR71XX_DDR_REG_TAP_CTRL0 0x1c +#define AR71XX_DDR_REG_TAP_CTRL1 0x20 + +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_DDR2_CONFIG 0x8c +#define AR933X_DDR_REG_EMR2 0x90 +#define AR933X_DDR_REG_EMR3 0x94 +#define AR933X_DDR_REG_BURST 0x98 +#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c +#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c +#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) + +#define QCA953X_PLL_CPU_CONFIG_REG 0x00 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04 +#define QCA953X_PLL_CLK_CTRL_REG 0x08 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA956X_PLL_CPU_CONFIG_REG 0x00 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c +#define QCA956X_PLL_CLK_CTRL_REG 0x10 + +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA953X_RESET_REG_RESET_MODULE 0x1c +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_RESET_MODULE 0x1c +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define QCA956X_RESET_REG_RESET_MODULE 0x1c +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define QCA953X_RESET_USB_EXT_PWR BIT(29) +#define QCA953X_RESET_EXTERNAL BIT(28) +#define QCA953X_RESET_RTC BIT(27) +#define QCA953X_RESET_FULL_CHIP BIT(24) +#define QCA953X_RESET_GE1_MDIO BIT(23) +#define QCA953X_RESET_GE0_MDIO BIT(22) +#define QCA953X_RESET_CPU_NMI BIT(21) +#define QCA953X_RESET_CPU_COLD BIT(20) +#define QCA953X_RESET_DDR BIT(16) +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA953X_RESET_GE1_MAC BIT(13) +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA953X_RESET_GE0_MAC BIT(9) +#define QCA953X_RESET_ETH_SWITCH BIT(8) +#define QCA953X_RESET_PCIE_PHY BIT(7) +#define QCA953X_RESET_PCIE BIT(6) +#define QCA953X_RESET_USB_HOST BIT(5) +#define QCA953X_RESET_USB_PHY BIT(4) +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) +#define QCA955X_RESET_EXTERNAL BIT(28) +#define QCA955X_RESET_RTC BIT(27) +#define QCA955X_RESET_PCIE_EP_INT BIT(26) +#define QCA955X_RESET_CHKSUM_ACC BIT(25) +#define QCA955X_RESET_FULL_CHIP BIT(24) +#define QCA955X_RESET_GE1_MDIO BIT(23) +#define QCA955X_RESET_GE0_MDIO BIT(22) +#define QCA955X_RESET_CPU_NMI BIT(21) +#define QCA955X_RESET_CPU_COLD BIT(20) +#define QCA955X_RESET_HOST_RESET_INT BIT(19) +#define QCA955X_RESET_PCIE_EP BIT(18) +#define QCA955X_RESET_UART1 BIT(17) +#define QCA955X_RESET_DDR BIT(16) +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA955X_RESET_NANDF BIT(14) +#define QCA955X_RESET_GE1_MAC BIT(13) +#define QCA955X_RESET_SGMII_ANALOG BIT(12) +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA955X_RESET_HOST_DMA_INT BIT(10) +#define QCA955X_RESET_GE0_MAC BIT(9) +#define QCA955X_RESET_SGMII BIT(8) +#define QCA955X_RESET_PCIE_PHY BIT(7) +#define QCA955X_RESET_PCIE BIT(6) +#define QCA955X_RESET_USB_HOST BIT(5) +#define QCA955X_RESET_USB_PHY BIT(4) +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define QCA953X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) + +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define QCA956X_EXT_INT_WMAC_MISC BIT(0) +#define QCA956X_EXT_INT_WMAC_TX BIT(1) +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA956X_EXT_INT_USB1 BIT(24) +#define QCA956X_EXT_INT_USB2 BIT(28) + +#define QCA956X_EXT_INT_WMAC_ALL \ + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) + +#define QCA956X_EXT_INT_PCIE_RC1_ALL \ + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ + QCA956X_EXT_INT_PCIE_RC1_INT3) + +#define QCA956X_EXT_INT_PCIE_RC2_ALL \ + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ + QCA956X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9533 0x0140 +#define REV_ID_MAJOR_QCA9533_V2 0x0160 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 +#define REV_ID_MAJOR_TP9343 0x0150 +#define REV_ID_MAJOR_QCA9561 0x1150 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR933X_REV_ID_REVISION_MASK 0x3 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +#define AR934X_REV_ID_REVISION_MASK 0xf + +#define QCA953X_REV_ID_REVISION_MASK 0xf + +#define QCA955X_REV_ID_REVISION_MASK 0xf + +#define QCA956X_REV_ID_REVISION_MASK 0xf + +/* + * RTC block + */ +#define AR933X_RTC_REG_RESET 0x40 +#define AR933X_RTC_REG_STATUS 0x44 +#define AR933X_RTC_REG_DERIVED 0x48 +#define AR933X_RTC_REG_FORCE_WAKE 0x4c +#define AR933X_RTC_REG_INT_CAUSE 0x50 +#define AR933X_RTC_REG_CAUSE_CLR 0x50 +#define AR933X_RTC_REG_INT_ENABLE 0x54 +#define AR933X_RTC_REG_INT_MASKE 0x58 + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 +#define AR933X_GPIO_REG_FUNC 0x30 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA953X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 +#define QCA956X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 + +#define AR71XX_GPIO_COUNT 16 +#define AR7240_GPIO_COUNT 18 +#define AR7241_GPIO_COUNT 20 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA953X_GPIO_COUNT 18 +#define QCA955X_GPIO_COUNT 24 +#define QCA956X_GPIO_COUNT 23 + +/* + * SRIF block + */ +#define AR933X_SRIF_DDR_DPLL1_REG 0x240 +#define AR933X_SRIF_DDR_DPLL2_REG 0x244 +#define AR933X_SRIF_DDR_DPLL3_REG 0x248 +#define AR933X_SRIF_DDR_DPLL4_REG 0x24c + +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 + +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 + +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) + +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +#define AR934X_GPIO_OUT_GPIO 0 +#define AR934X_GPIO_OUT_SPI_CS1 7 +#define AR934X_GPIO_OUT_LED_LINK0 41 +#define AR934X_GPIO_OUT_LED_LINK1 42 +#define AR934X_GPIO_OUT_LED_LINK2 43 +#define AR934X_GPIO_OUT_LED_LINK3 44 +#define AR934X_GPIO_OUT_LED_LINK4 45 +#define AR934X_GPIO_OUT_EXT_LNA0 46 +#define AR934X_GPIO_OUT_EXT_LNA1 47 + +#define QCA955X_GPIO_OUT_GPIO 0 + +/* + * MII_CTRL block + */ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* + * AR933X GMAC interface + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* + * AR934X GMAC Interface + */ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define AR934X_ETH_CFG_RXD_DELAY BIT(14) +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16) +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 + +/* + * QCA953X GMAC Interface + */ +#define QCA953X_GMAC_REG_ETH_CFG 0x00 + +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* + * QCA955X GMAC Interface + */ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) + +#endif /* __ASM_AR71XX_H */ diff --git a/arch/mips/include/asm/arch-ath79/ar933x_uart.h b/arch/mips/include/asm/arch-ath79/ar933x_uart.h new file mode 100644 index 0000000..22be22e --- /dev/null +++ b/arch/mips/include/asm/arch-ath79/ar933x_uart.h @@ -0,0 +1,67 @@ +/* + * Atheros AR933X UART defines + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __AR933X_UART_H +#define __AR933X_UART_H + +#define AR933X_UART_REGS_SIZE 20 +#define AR933X_UART_FIFO_SIZE 16 + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLOCK_REG 0x08 +#define AR933X_UART_INT_REG 0x0c +#define AR933X_UART_INT_EN_REG 0x10 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR BIT(8) +#define AR933X_UART_DATA_TX_CSR BIT(9) + +#define AR933X_UART_CS_PARITY_S 0 +#define AR933X_UART_CS_PARITY_M 0x3 +#define AR933X_UART_CS_PARITY_NONE 0 +#define AR933X_UART_CS_PARITY_ODD 1 +#define AR933X_UART_CS_PARITY_EVEN 2 +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_NONE 0 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_FLOW_CTRL_S 4 +#define AR933X_UART_CS_FLOW_CTRL_M 0x3 +#define AR933X_UART_CS_DMA_EN BIT(6) +#define AR933X_UART_CS_TX_READY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_READY_ORIDE BIT(8) +#define AR933X_UART_CS_TX_READY BIT(9) +#define AR933X_UART_CS_RX_BREAK BIT(10) +#define AR933X_UART_CS_TX_BREAK BIT(11) +#define AR933X_UART_CS_HOST_INT BIT(12) +#define AR933X_UART_CS_HOST_INT_EN BIT(13) +#define AR933X_UART_CS_TX_BUSY BIT(14) +#define AR933X_UART_CS_RX_BUSY BIT(15) + +#define AR933X_UART_CLOCK_STEP_M 0xffff +#define AR933X_UART_CLOCK_SCALE_M 0xfff +#define AR933X_UART_CLOCK_SCALE_S 16 +#define AR933X_UART_CLOCK_STEP_S 0 + +#define AR933X_UART_INT_RX_VALID BIT(0) +#define AR933X_UART_INT_TX_READY BIT(1) +#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2) +#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3) +#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4) +#define AR933X_UART_INT_RX_PARITY_ERR BIT(5) +#define AR933X_UART_INT_RX_BREAK_ON BIT(6) +#define AR933X_UART_INT_RX_BREAK_OFF BIT(7) +#define AR933X_UART_INT_RX_FULL BIT(8) +#define AR933X_UART_INT_TX_EMPTY BIT(9) +#define AR933X_UART_INT_ALLINTS 0x3ff + +#endif /* __AR933X_UART_H */ diff --git a/arch/mips/include/asm/arch-ath79/ath79.h b/arch/mips/include/asm/arch-ath79/ath79.h new file mode 100644 index 0000000..0ad97c0 --- /dev/null +++ b/arch/mips/include/asm/arch-ath79/ath79.h @@ -0,0 +1,145 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include <linux/types.h> + +enum ath79_soc_type { + ATH79_SOC_UNKNOWN, + ATH79_SOC_AR7130, + ATH79_SOC_AR7141, + ATH79_SOC_AR7161, + ATH79_SOC_AR7240, + ATH79_SOC_AR7241, + ATH79_SOC_AR7242, + ATH79_SOC_AR9130, + ATH79_SOC_AR9132, + ATH79_SOC_AR9330, + ATH79_SOC_AR9331, + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, + ATH79_SOC_QCA9533, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, + ATH79_SOC_TP9343, + ATH79_SOC_QCA9561, +}; + +extern enum ath79_soc_type get_soc_type(void); +static inline int soc_is_ar71xx(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7130 || + soc == ATH79_SOC_AR7141 || + soc == ATH79_SOC_AR7161; +} + +static inline int soc_is_ar724x(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7240 || + soc == ATH79_SOC_AR7241 || + soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar7240(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7240; +} + +static inline int soc_is_ar7241(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7241; +} + +static inline int soc_is_ar7242(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar913x(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9130 || + soc == ATH79_SOC_AR9132; +} + +static inline int soc_is_ar933x(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9330 || + soc == ATH79_SOC_AR9331; +} + +static inline int soc_is_ar9341(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9341; +} + +static inline int soc_is_ar9342(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9342; +} + +static inline int soc_is_ar9344(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9344; +} + +static inline int soc_is_ar934x(enum ath79_soc_type soc) +{ + return soc_is_ar9341(soc) || + soc_is_ar9342(soc) || + soc_is_ar9344(soc); +} + +static inline int soc_is_qca9533(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9533; +} + +static inline int soc_is_qca953x(enum ath79_soc_type soc) +{ + return soc_is_qca9533(soc); +} + +static inline int soc_is_qca9556(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9556; +} + +static inline int soc_is_qca9558(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9558; +} + +static inline int soc_is_qca955x(enum ath79_soc_type soc) +{ + return soc_is_qca9556(soc) || soc_is_qca9558(soc); +} + +static inline int soc_is_tp9343(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_TP9343; +} + +static inline int soc_is_qca9561(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9561; +} + +static inline int soc_is_qca956x(enum ath79_soc_type soc) +{ + return soc_is_tp9343(soc) || soc_is_qca9561(soc); +} + +#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile new file mode 100644 index 0000000..d042b47 --- /dev/null +++ b/arch/mips/mach-ath79/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += cpu.o +obj-y += dram.o + +obj-$(CONFIG_SOC_AR933X) += ar933x/ diff --git a/arch/mips/mach-ath79/ar933x/Makefile b/arch/mips/mach-ath79/ar933x/Makefile new file mode 100644 index 0000000..7739f22 --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lowlevel_init.o +obj-y += ddr_tap.o diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..34a4613 --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S @@ -0,0 +1,272 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h> + +#define DDR_TAP_CTRL0 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_TAP_CTRL0) +#define DDR_TAP_CTRL1 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_TAP_CTRL1) +#define DRAM_K0(x) KSEG0ADDR(x) +#define DRAM_K1(x) KSEG1ADDR(x) + + .text + .set noreorder + .set mips32 + + .globl ddr_tap_init +ddr_tap_init: + /* Tap settings for the DDR */ + li t0, 0xffffffff + li t1, DRAM_K0(0x500000) + sw t0, 0x0(t1) + sw t0, 0x4(t1) + sw t0, 0x8(t1) + sw t0, 0xc(t1) + nop + nop + + li t8, DRAM_K1(0x2000) + li t0, 0x00 + li t1, 0x100 +0: + andi t2, t0, 0x03 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x01 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x02 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x03 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0x0(t8) +2: + andi t2, t0, 0x0c + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x04 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x08 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x0c + bne t2, t3,2f + li t9, 0xffffffff + sw t9, 0x4(t8) +2: + andi t2, t0, 0x30 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x10 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x20 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x30 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0x8(t8) +2: + andi t2, t0, 0xc0 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0x40 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0x80 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0xc0 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0xc(t8) +2: + addiu t0, t0, 0x1 + addiu t8, t8, 0x10 + bne t0, t1, 0b + nop + + li a0, DRAM_K1(0x2000) # Start address + li a1, DRAM_K0(0x2000) # Start address of the pattern 200 + li a2, DRAM_K0(0x3000) # End Address of the pattern 220 + li t0, KSEG1ADDR(DDR_TAP_CTRL0) + lw a3, 0x0(t0) # loading default tap value + nop + ori t0, a3, 0x0 + + /* $t1=1 indicates increasing tap value, 0 = decreasing */ + li t1, 0x1 +0: + li t7, 0x2 + li t8, KSEG1ADDR(DDR_TAP_CTRL0) + sw t0, 0x0(t8) + nop + li t8, KSEG1ADDR(DDR_TAP_CTRL1) + sw t0, 0x0(t8) + nop + + /* t0 stores current tap setting under test + t1 indicates increment or decrement of tap */ +1: + ori t2, a0, 0x0 + ori t3, a1, 0x0 + ori t4, a2, 0x0 +2: + lw t5, 0x0(t2) # upper and lower limit detection + lw t6, 0x0(t3) + bne t5, t6, 3f + nop + addiu t2, t2, 0x4 + addiu t3, t3, 0x4 + bne t3, t4, 2b + nop + addiu t7, t7, -1 + bnez t7, 1b + nop + + bnez t1, 2f # increment tap if t1 = 1 + nop + bnez t0, 1f # tap=0 works so low limit=0, + nop # else decrement tap value + + li t8, DRAM_K0(0x500000) # assigning lower limit = 0 + sw t0, 0x0(t8) + nop + add t9, t9, t0 # adding lower limit to upper limit + b 4f # used to calc mid value + nop +1: + addiu t0, t0 , -1 # decrement and loading this new tap + b 0b + nop +2: + addiu t0, t0, 0x1 + xori v1, t0, 0x20 # limiting upper limit to 0x20 + bnez v1, 0b + nop + b 1f + nop +3: + bnez t1, 1f # t1=1 fail for upper limit + nop # t1=0 fail for lower limit + addiu t0, t0, 0x1 + nop + li t8, DRAM_K0(0x500000) # storing lower limit + sw t0, 0x0(t8) + nop + add t9, t9, t0 # adding lower limit and upper limit + b 4f + nop +1: + addiu t0, t0, -1 + li t1, 0x0 # changing to decreasing tap mode + li t8, DRAM_K0(0x500000) # storing upper limit + sw t0, 0x4(t8) + nop + ori t9, t0, 0x0 + ori t0, a3, 0x0 # loading default tap value + b 0b + nop + + /* calculating mid value of the tap, storing DQS0, DQS1 in + 0x80500008, 0x8050000c resp */ +4: + li t7, 0x2 + div t9, t7 + nop + mfhi t6 + mflo t5 + add t6, t6, t5 + li t8, DRAM_K0(0x500000) + sw t5, 0x8(t8) + nop + sw t6, 0xc(t8) + nop + li t8, KSEG1ADDR(DDR_TAP_CTRL0) + sw t5, 0x0(t8) + nop + li t8, KSEG1ADDR(DDR_TAP_CTRL1) + sw t6, 0x0(t8) + nop + + nop + jr ra + nop diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..57a8b43 --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S @@ -0,0 +1,534 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h> + +#define BOOT_STRAP (AR71XX_RESET_BASE + AR933X_RESET_REG_BOOTSTRAP) +#define RST_RESET (AR71XX_RESET_BASE + AR933X_RESET_REG_RESET_MODULE) +#define PLL_CPU_CONF (AR71XX_PLL_BASE + AR933X_PLL_CPU_CONFIG_REG) +#define PLL_SEC_CONF (AR71XX_PLL_BASE + AR71XX_PLL_REG_SEC_CONFIG) +#define PLL_CLK_CTRL (AR71XX_PLL_BASE + AR933X_PLL_CLOCK_CTRL_REG) +#define PLL_DITH_FRAC (AR71XX_PLL_BASE + AR71XX_PLL_REG_ETH0_INT_CLOCK) +#define DDR_CONFIG (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_CONFIG) +#define DDR_CONFIG2 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_CONFIG2) +#define DDR_MODE (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_MODE) +#define DDR_EMR (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_EMR) +#define DDR_CONTROL (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_CONTROL) +#define DDR_REFRESH (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_REFRESH) +#define DDR_RD_CYCLE (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_RD_CYCLE) +#define DDR_TAP_CTRL0 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_TAP_CTRL0) +#define DDR_TAP_CTRL1 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_TAP_CTRL1) +#define DDR_DDR2_CONF (AR71XX_DDR_CTRL_BASE + AR933X_DDR_REG_DDR2_CONFIG) +#define DDR_EMR2 (AR71XX_DDR_CTRL_BASE + AR933X_DDR_REG_EMR2) +#define DDR_EMR3 (AR71XX_DDR_CTRL_BASE + AR933X_DDR_REG_EMR3) +#define DDR_TO_MAX (AR71XX_DDR_CTRL_BASE + AR933X_DDR_REG_TIMEOUT_MAX) +#define RTC_RESET (AR933X_RTC_BASE + AR933X_RTC_REG_RESET) +#define RTC_STATUS (AR933X_RTC_BASE + AR933X_RTC_REG_STATUS) +#define RTC_FORCE_WAKE (AR933X_RTC_BASE + AR933X_RTC_REG_FORCE_WAKE) +#define DDR_DPLL2 (AR933X_SRIF_BASE + AR933X_SRIF_DDR_DPLL2_REG) +#define DDR_DPLL3 (AR933X_SRIF_BASE + AR933X_SRIF_DDR_DPLL3_REG) +#define DDR_DPLL4 (AR933X_SRIF_BASE + AR933X_SRIF_DDR_DPLL4_REG) + +#define SET_BIT(val, bit) ((val) | (1 << (bit))) +#define SET_PLL_PD(val) SET_BIT(val, 30) +#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) +#define PLL_BYPASS(val) SET_BIT(val, 2) + +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ + (((0x3F & divint) << 10) | \ + ((0x1F & refdiv) << 16) | \ + ((0x1 & range) << 21) | \ + ((0x7 & outdiv) << 23) ) + +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ + (((0x3 & (cpudiv - 1)) << 5) | \ + ((0x3 & (ddrdiv - 1)) << 10) | \ + ((0x3 & (ahbdiv - 1)) << 15) ) + +/* + * PLL_CPU_CONFIG_VAL + * + * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU PLL Configuration (CPU_PLL_CONFIG) + * + * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL) + * => 32 (0x20) VCOOUT = XTAL * DIV_INT + * bits 16..20 (5bit) REFDIV (Reference clock divider) + * => 1 (0x1) [Must start at values 1] + * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL) + * => 0 (0x0) [Doesn't impact clock values] + * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output) + * => 1 (0x1) [0 is illegal!] + * PLLOUT = VCOOUT * (1/2^OUTDIV) + */ +/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1) + +/* + * PLL_CLK_CONTROL_VAL + * + * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU Clock Control Register CLOCK_CONTROL + * + * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test. + * Software must enable the CPU PLL for normal and + * then set this bit to 0) + * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) + * CPU_CLK = PLLOUT / CPU_POST_DIV + * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) + * DDR_CLK = PLLOUT / DDR_POST_DIV + * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) + * AHB_CLK = PLLOUT / AHB_POST_DIV + * + */ +#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2) + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + /* These three WLAN_RESET will avoid original issue */ + li t3, 0x03 +1: + li t0, KSEG1ADDR(RST_RESET) + lw t1, 0x0(t0) + ori t1, t1, 0x0800 + sw t1, 0x0(t0) + nop + lw t1, 0x0(t0) + li t2, 0xfffff7ff + and t1, t1, t2 + sw t1, 0x0(t0) + nop + addi t3, t3, -1 + bnez t3, 1b + nop + + li t2, 0x20 +2: + beqz t2, 1b + nop + addi t2, t2, -1 + li t0, KSEG1ADDR(BOOT_STRAP) + lw t5, 0x0(t0) + andi t1, t5, 0x10 + bnez t1, 2b + nop + + li t1, 0x02110E + sw t1, 0x0(t0) + nop + + /* RTC Force Wake */ + li t0, KSEG1ADDR(RTC_FORCE_WAKE) + li t1, 0x03 + sw t1, 0x0(t0) + nop + nop + + /* RTC Reset */ + li t0, KSEG1ADDR(RTC_RESET) + li t1, 0x00 + sw t1, 0x0(t0) + nop + nop + + li t0, KSEG1ADDR(RTC_RESET) + li t1, 0x01 + sw t1, 0x0(t0) + nop + nop + + /* Wait for RTC in on state */ + li t0, KSEG1ADDR(RTC_STATUS) +1: + lw t1, 0x0(t0) + andi t1, t1, 0x02 + beqz t1, 1b + nop + + /* Program ki/kd */ + li t0, KSEG1ADDR(DDR_DPLL2) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x19e82f01 + b 2f + nop +1: + li t1, 0x18e82f01 +2: + sw t1, 0x0(t0) + + /* Program phase shift */ + li t0, KSEG1ADDR(DDR_DPLL3) + lw t1, 0x0(t0) + li t2, 0xc07fffff + and t1, t1, t2 + li t2, 0x800000 # meas_at_txon + or t1, t1, t2 + sw t1, 0x0(t0) + nop + + /* Max AHB Master wait time out ... */ + li t0, KSEG1ADDR(DDR_TO_MAX) + li t1, 0xfffff + sw t1, 0x0(t0) + nop + + /* in some cases, the SoC doesn't start with higher clock on AHB */ + li t0, KSEG1ADDR(PLL_CLK_CTRL) + li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL)) + sw t1, 0x0(t0) + nop + + /* Set SETTLE_TIME in CPU PLL */ + li t0, KSEG1ADDR(PLL_SEC_CONF) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x0352 + b 2f + nop +1: + li t1, 0x0550 +2: + sw t1, 0x0(t0) + nop + + /* Set nint, frac, refdiv, outdiv, range according to xtal */ +0: + li t0, KSEG1ADDR(PLL_CPU_CONF) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M) + b 2f + nop +1: + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M) +2: + sw t1, 0x0(t0) + nop +1: + lw t1, 0x0(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Put frac bit19:10 configuration */ + li t0, KSEG1ADDR(PLL_DITH_FRAC) + li t1, 0x1003E8 + sw t1, 0x0(t0) + nop + + /* Clear PLL power down bit in CPU PLL configuration */ + li t0, KSEG1ADDR(PLL_CPU_CONF) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, PLL_CPU_CONFIG_VAL_25M + b 2f + nop +1: + li t1, PLL_CPU_CONFIG_VAL_40M +2: + sw t1, 0x0(t0) + nop + + /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */ +1: + lw t1, 0x0(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Confirm DDR PLL lock */ + li t3, 100 + li t4, 0 + +2: + addi t4, t4, 1 + bgt t4, t3, 0b + nop + + li t3, 5 +3: + /* Clear do_meas */ + li t6, KSEG1ADDR(DDR_DPLL3) + lw t7, 0x0(t6) + li t8, 0xBFFFFFFF + and t7, t7, t8 + sw t7, 0x0(t6) + nop + + li t9, 10 +1: + subu t9, t9, 1 + bnez t9, 1b + nop + + /* Set do_meas */ + li t8, 0x40000000 + or t7, t7, t8 + sw t7, 0x0(t6) + nop + + /* Check meas_done */ +1: + li t6, KSEG1ADDR(DDR_DPLL4) + lw t7, 0x0(t6) + andi t7, t7, 0x8 + beqz t7, 1b + nop + + li t6, KSEG1ADDR(DDR_DPLL3) + lw t7, 0x0(t6) + li t8, 0x007FFFF8 + and t7, t7, t8 + srl t7, t7, 3 + li t8, 0x4000 + bgt t7, t8, 2b + nop + addi t3, t3, -1 + bnez t3, 3b + nop + + /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ + li t0, KSEG1ADDR(PLL_CLK_CTRL) + li t1, PLL_CLK_CONTROL_VAL + sw t1, 0x0(t0) + nop + + li t0, KSEG1ADDR(DDR_CONFIG) + li t1, 0x7fbc8cd0 + sw t1, 0x0(t0) + + li t0, KSEG1ADDR(DDR_CONFIG2) + li t1, 0x9dd0e6a8 + sw t1, 0x0(t0) + + andi t1, t5, 0x2000 # t5 BOOT_STRAP + beqz t1, 3f + nop + + /* Enable DDR2 */ + li t0, KSEG1ADDR(DDR_DDR2_CONF) + li t1, 0xA59 + sw t1, 0x0(t0) + + /* Precharge All */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x08 + sw t1, 0x0(t0) + + /* Disable High Temperature Self-Refresh Rate */ + li t0, KSEG1ADDR(DDR_EMR2) + li t1, 0x00 + sw t1, 0x0(t0) + + /* Extended Mode Register 2 Set (EMR2S) */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x10 + sw t1, 0x0(t0) + + li t0, KSEG1ADDR(DDR_EMR3) + li t1, 0x00 + sw t1, 0x0(t0) + + /* Extended Mode Register 3 Set (EMR3S) */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x20 + sw t1, 0x0(t0) + + /* Enable DLL */ + li t0, KSEG1ADDR(DDR_EMR) + li t1, 0x00 + sw t1, 0x0(t0) + + /* Extended Mode Register Set (EMRS) */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x02 + sw t1, 0x0(t0) + + /* Reset DLL */ + li t0, KSEG1ADDR(DDR_MODE) + li t1, 0x100 + sw t1, 0x0(t0) + + /* Mode Register Set (MRS) */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x01 + sw t1, 0x0(t0) + + /* Precharge All */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x08 + sw t1, 0x0(t0) + + /* Auto Refresh */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x04 + sw t1, 0x0(t0) + + /* Auto Refresh */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x04 + sw t1, 0x0(t0) + + /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */ + li t0, KSEG1ADDR(DDR_MODE) + li t1, 0xa33 + sw t1, 0x0(t0) + + /* Mode Register Set (MRS) */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x01 + sw t1, 0x0(t0) + + /* E7,E8,E9 equal to 1(Enable OCD defaults), Enable DLL, + Reduced Drive Strength */ + li t0, KSEG1ADDR(DDR_EMR) + li t1, 0x382 + sw t1, 0x0(t0) + + /* Extended Mode Register Set (EMRS) */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x02 + sw t1, 0x0(t0) + + /* E7,E8,E9 equal to 0(OCD exit), Enable DLL, + Reduced Drive Strength */ + li t0, KSEG1ADDR(DDR_EMR) + li t1, 0x402 + sw t1, 0x0(t0) + + /* Extended Mode Register Set (EMRS) */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x02 + sw t1, 0x0(t0) + + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ + li t0, KSEG1ADDR(DDR_REFRESH) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x4186 + b 2f + nop +1: + li t1, 0x4270 +2: + sw t1, 0x0(t2) + + /* DQS 0 Tap Control (needs tuning) */ + li t0, KSEG1ADDR(DDR_TAP_CTRL0) + li t1, 0x08 + sw t1, 0x0(t0) + + /* DQS 1 Tap Control (needs tuning) */ + li t0, KSEG1ADDR(DDR_TAP_CTRL1) + li t1, 0x09 + sw t1, 0x0(t0) + + /* For 16-bit DDR */ + li t0, KSEG1ADDR(DDR_RD_CYCLE) + li t1, 0xff + sw t1, 0x0(t0) + + nop + b 4f + nop + + /* DDR1 config */ +3: + /* Precharge All */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x08 + sw t1, 0x0(t0) + + /* Write Mode Word */ + li t0, KSEG1ADDR(DDR_MODE) + li t1, 0x133 + sw t1, 0x0(t0) + + /* Forces an MRS update cycle in DDR */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x01 + sw t1, 0x0(t0) + + /* Enable DLL, High drive strength from DDR */ + li t0, KSEG1ADDR(DDR_EMR) + li t1, 0x02 + sw t1, 0x0(t0) + + /* Write Extended Mode Word of DDR */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x02 + sw t1, 0x0(t0) + + /* Precharge All */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x08 + sw t1, 0x0(t0) + + /* DLL out of reset, CAS Latency 3 */ + li t0, KSEG1ADDR(DDR_MODE) + li t1, 0x33 + sw t1, 0x0(t0) + + /* Write mode word */ + li t0, KSEG1ADDR(DDR_CONTROL) + li t1, 0x01 + sw t1, 0x0(t0) + + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ + li t0, KSEG1ADDR(DDR_REFRESH) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x4270 + b 2f + nop +1: + li t1, 0x4186 +2: + sw t1, 0x0(t0) + + /* DQS 0 Tap Control (needs tuning) */ + li t0, KSEG1ADDR(DDR_TAP_CTRL0) + li t1, 0x08 + sw t1, 0x0(t0) + + /* DQS 1 Tap Control (needs tuning) */ + li t0, KSEG1ADDR(DDR_TAP_CTRL1) + li t1, 0x09 + sw t1, 0x0(t0) + + /* For 16-bit DDR */ + li t0, KSEG1ADDR(DDR_RD_CYCLE) + li t1, 0xff + sw t1, 0x0(t0) + +4: + nop + jr ra + nop diff --git a/arch/mips/mach-ath79/config.mk b/arch/mips/mach-ath79/config.mk new file mode 100644 index 0000000..cc76d3b --- /dev/null +++ b/arch/mips/mach-ath79/config.mk @@ -0,0 +1,8 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -mtune=24kc diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c new file mode 100644 index 0000000..295e11e --- /dev/null +++ b/arch/mips/mach-ath79/cpu.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h> + +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) +#define RST_READ(a) REG_READ(AR71XX_RESET_BASE, a) +#define RST_WRITE(a, v) REG_WRITE(AR71XX_RESET_BASE, a, v) + +DECLARE_GLOBAL_DATA_PTR; + +enum ath79_soc_type get_soc_type(void) +{ + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; + u32 id, major, minor; + + id = RST_READ(AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + soc = ATH79_SOC_AR7130; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + soc = ATH79_SOC_AR7141; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + soc = ATH79_SOC_AR7161; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + soc = ATH79_SOC_AR7240; + break; + + case REV_ID_MAJOR_AR7241: + soc = ATH79_SOC_AR7241; + break; + + case REV_ID_MAJOR_AR7242: + soc = ATH79_SOC_AR7242; + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + soc = ATH79_SOC_AR9130; + break; + + case AR913X_REV_ID_MINOR_AR9132: + soc = ATH79_SOC_AR9132; + break; + } + break; + + case REV_ID_MAJOR_AR9330: + soc = ATH79_SOC_AR9330; + break; + + case REV_ID_MAJOR_AR9331: + soc = ATH79_SOC_AR9331; + break; + + case REV_ID_MAJOR_AR9341: + soc = ATH79_SOC_AR9341; + break; + + case REV_ID_MAJOR_AR9342: + soc = ATH79_SOC_AR9342; + break; + + case REV_ID_MAJOR_AR9344: + soc = ATH79_SOC_AR9344; + break; + + case REV_ID_MAJOR_QCA9533_V2: + /* drop through */ + + case REV_ID_MAJOR_QCA9533: + soc = ATH79_SOC_QCA9533; + break; + + case REV_ID_MAJOR_QCA9556: + soc = ATH79_SOC_QCA9556; + break; + + case REV_ID_MAJOR_QCA9558: + soc = ATH79_SOC_QCA9558; + break; + + case REV_ID_MAJOR_TP9343: + soc = ATH79_SOC_TP9343; + break; + + case REV_ID_MAJOR_QCA9561: + soc = ATH79_SOC_QCA9561; + break; + default: + break; + } + + return soc; +} + +int print_cpuinfo(void) +{ + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; + char *chip = "????"; + u32 id, major, minor; + u32 rev = 0; + u32 ver = 1; + + id = RST_READ(AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + soc = ATH79_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + soc = ATH79_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + soc = ATH79_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + soc = ATH79_SOC_AR7240; + chip = "7240"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR7241: + soc = ATH79_SOC_AR7241; + chip = "7241"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR7242: + soc = ATH79_SOC_AR7242; + chip = "7242"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; + rev &= AR913X_REV_ID_REVISION_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + soc = ATH79_SOC_AR9130; + chip = "9130"; + break; + + case AR913X_REV_ID_MINOR_AR9132: + soc = ATH79_SOC_AR9132; + chip = "9132"; + break; + } + break; + + case REV_ID_MAJOR_AR9330: + soc = ATH79_SOC_AR9330; + chip = "9330"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9331: + soc = ATH79_SOC_AR9331; + chip = "9331"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9341: + soc = ATH79_SOC_AR9341; + chip = "9341"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9342: + soc = ATH79_SOC_AR9342; + chip = "9342"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9344: + soc = ATH79_SOC_AR9344; + chip = "9344"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9533_V2: + ver = 2; + /* drop through */ + + case REV_ID_MAJOR_QCA9533: + soc = ATH79_SOC_QCA9533; + chip = "9533"; + rev = id & QCA953X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9556: + soc = ATH79_SOC_QCA9556; + chip = "9556"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9558: + soc = ATH79_SOC_QCA9558; + chip = "9558"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_TP9343: + soc = ATH79_SOC_TP9343; + chip = "9343"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9561: + soc = ATH79_SOC_QCA9561; + chip = "9561"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + } + + puts("SoC: "); + switch (soc) { + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip, ver, rev); + break; + case ATH79_SOC_TP9343: + printf("Qualcomm Atheros TP%s rev %u\n", chip, rev); + break; + case ATH79_SOC_UNKNOWN: + printf("ATH79: unknown SoC, id:0x%08x", id); + default: + printf("Atheros AR%s rev %u\n", chip, rev); + } + + return 0; +} diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c new file mode 100644 index 0000000..a9bc945 --- /dev/null +++ b/arch/mips/mach-ath79/dram.c @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/addrspace.h> + +extern void ddr_tap_init(void); +phys_size_t initdram(int board_type) +{ + uint8_t *addr, *p; + int i; + + ddr_tap_init(); + addr = (uint8_t *)KSEG1; + *addr = 0x77; + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { + p += 0x1000000; + *p = i; + if (*addr != 0x77) + break; + } + return (phys_size_t)(p - addr); +} diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c new file mode 100644 index 0000000..0ace05d --- /dev/null +++ b/arch/mips/mach-ath79/reset.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h> + +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) +#define RST_READ(a) REG_READ(AR71XX_RESET_BASE, a) +#define RST_WRITE(a, v) REG_WRITE(AR71XX_RESET_BASE, a, v) + +DECLARE_GLOBAL_DATA_PTR; + +void _machine_restart(void) +{ + enum ath79_soc_type soc; + u32 val, reg = 0; + + soc = get_soc_type(); + if (soc_is_ar71xx(soc)) + reg = AR71XX_RESET_REG_RESET_MODULE; + else if (soc_is_ar724x(soc)) + reg = AR724X_RESET_REG_RESET_MODULE; + else if (soc_is_ar913x(soc)) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x(soc)) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x(soc)) + reg = AR934X_RESET_REG_RESET_MODULE; + else if (soc_is_qca953x(soc)) + reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x(soc)) + reg = QCA955X_RESET_REG_RESET_MODULE; + else if (soc_is_qca956x(soc)) + reg = QCA956X_RESET_REG_RESET_MODULE; + else + puts("Reset register not defined for this SOC\n"); + + if (reg) { + val = RST_READ(reg); + val |= AR71XX_RESET_FULL_CHIP; + RST_WRITE(reg, val); + } + + while (1) + /* NOP */; +} -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 1/4] mips: add base support for atheros ath79 based SOCs 2015-12-22 7:44 ` [U-Boot] [PATCH v2 1/4] mips: add base support for atheros ath79 based SOCs Wills Wang @ 2015-12-22 14:34 ` Daniel Schwierzeck 0 siblings, 0 replies; 8+ messages in thread From: Daniel Schwierzeck @ 2015-12-22 14:34 UTC (permalink / raw) To: u-boot looks better now, but there are still some issues Am 22.12.2015 um 08:44 schrieb Wills Wang: > This patch enable work for ar933x SOC, tested on ar9331 board. > > Signed-off-by: Wills Wang <wills.wang@live.com> > --- > > arch/mips/Makefile | 1 + > arch/mips/include/asm/arch-ath79/ar71xx_regs.h | 1143 ++++++++++++++++++++++++ > arch/mips/include/asm/arch-ath79/ar933x_uart.h | 67 ++ > arch/mips/include/asm/arch-ath79/ath79.h | 145 +++ > arch/mips/mach-ath79/Makefile | 12 + > arch/mips/mach-ath79/ar933x/Makefile | 9 + > arch/mips/mach-ath79/ar933x/ddr_tap.S | 272 ++++++ > arch/mips/mach-ath79/ar933x/lowlevel_init.S | 534 +++++++++++ > arch/mips/mach-ath79/config.mk | 8 + > arch/mips/mach-ath79/cpu.c | 274 ++++++ > arch/mips/mach-ath79/dram.c | 27 + > arch/mips/mach-ath79/reset.c | 55 ++ > 12 files changed, 2547 insertions(+) > create mode 100644 arch/mips/include/asm/arch-ath79/ar71xx_regs.h > create mode 100644 arch/mips/include/asm/arch-ath79/ar933x_uart.h > create mode 100644 arch/mips/include/asm/arch-ath79/ath79.h I've recently noticed that this include path is going to be deprecated in the future. All SoC specific header files should go to arch/*/mach-*/include/mach/ and a driver should use "include <mach/file.h>". I've sent a patch [1] to enable this for MIPS arch. If you rebase your patches to current next branch in u-boot-mips repo, you are having this patch included. So please use the new path. [1] http://patchwork.ozlabs.org/patch/559581/ > create mode 100644 arch/mips/mach-ath79/Makefile > create mode 100644 arch/mips/mach-ath79/ar933x/Makefile > create mode 100644 arch/mips/mach-ath79/ar933x/ddr_tap.S > create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S > create mode 100644 arch/mips/mach-ath79/config.mk > create mode 100644 arch/mips/mach-ath79/cpu.c > create mode 100644 arch/mips/mach-ath79/dram.c > create mode 100644 arch/mips/mach-ath79/reset.c > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index 43f0f5c..e2dd729 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/ > libs-y += arch/mips/lib/ > > libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/ > +libs-$(CONFIG_SOC_ATH79) += arch/mips/mach-ath79/ please use CONFIG_ARCH_ATH79 as Kconfig symbol. Also with the patch mentioned above, this should be look like this: mach-$(CONFIG_ARCH_ATH79) += ath79 > diff --git a/arch/mips/include/asm/arch-ath79/ar71xx_regs.h b/arch/mips/include/asm/arch-ath79/ar71xx_regs.h > new file mode 100644 > index 0000000..56c0d36 > --- /dev/null > +++ b/arch/mips/include/asm/arch-ath79/ar71xx_regs.h > @@ -0,0 +1,1143 @@ > +/* > + * Atheros AR71XX/AR724X/AR913X SoC register definitions > + * > + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> > + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> > + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> > + * > + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. replace the license text with a SPDX tag SPDX-License-Identifier: GPL-2.0 or SPDX-License-Identifier: GPL-2.0+ That is a requirement for all source files. Thus please check all your source files. > + */ > + > +#ifndef __ASM_MACH_AR71XX_REGS_H > +#define __ASM_MACH_AR71XX_REGS_H > + > +#ifndef BIT > +#define BIT(nr) (1UL << (nr)) > +#endif you can drop this, the BIT macro is available in U-Boot > + > +#define AR71XX_APB_BASE 0x18000000 > +#define AR71XX_GE0_BASE 0x19000000 > +#define AR71XX_GE0_SIZE 0x10000 > +#define AR71XX_GE1_BASE 0x1a000000 > +#define AR71XX_GE1_SIZE 0x10000 > +#define AR71XX_EHCI_BASE 0x1b000000 > +#define AR71XX_EHCI_SIZE 0x1000 > +#define AR71XX_OHCI_BASE 0x1c000000 > +#define AR71XX_OHCI_SIZE 0x1000 > +#define AR71XX_SPI_BASE 0x1f000000 > +#define AR71XX_SPI_SIZE 0x01000000 > + > +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) > +#define AR71XX_DDR_CTRL_SIZE 0x100 > +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) > +#define AR71XX_UART_SIZE 0x100 > +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) > +#define AR71XX_USB_CTRL_SIZE 0x100 > +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) > +#define AR71XX_GPIO_SIZE 0x100 > +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) > +#define AR71XX_PLL_SIZE 0x100 > +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) > +#define AR71XX_RESET_SIZE 0x100 > +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) > +#define AR71XX_MII_SIZE 0x100 > + > +#define AR71XX_PCI_MEM_BASE 0x10000000 > +#define AR71XX_PCI_MEM_SIZE 0x07000000 > + > +#define AR71XX_PCI_WIN0_OFFS 0x10000000 > +#define AR71XX_PCI_WIN1_OFFS 0x11000000 > +#define AR71XX_PCI_WIN2_OFFS 0x12000000 > +#define AR71XX_PCI_WIN3_OFFS 0x13000000 > +#define AR71XX_PCI_WIN4_OFFS 0x14000000 > +#define AR71XX_PCI_WIN5_OFFS 0x15000000 > +#define AR71XX_PCI_WIN6_OFFS 0x16000000 > +#define AR71XX_PCI_WIN7_OFFS 0x07000000 > + > +#define AR71XX_PCI_CFG_BASE \ > + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) > +#define AR71XX_PCI_CFG_SIZE 0x100 > + > +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) > +#define AR7240_USB_CTRL_SIZE 0x100 > +#define AR7240_OHCI_BASE 0x1b000000 > +#define AR7240_OHCI_SIZE 0x1000 > + > +#define AR724X_PCI_MEM_BASE 0x10000000 > +#define AR724X_PCI_MEM_SIZE 0x04000000 > + > +#define AR724X_PCI_CFG_BASE 0x14000000 > +#define AR724X_PCI_CFG_SIZE 0x1000 > +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) > +#define AR724X_PCI_CRP_SIZE 0x1000 > +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) > +#define AR724X_PCI_CTRL_SIZE 0x100 > + > +#define AR724X_EHCI_BASE 0x1b000000 > +#define AR724X_EHCI_SIZE 0x1000 > + > +#define AR913X_EHCI_BASE 0x1b000000 > +#define AR913X_EHCI_SIZE 0x1000 > +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) > +#define AR913X_WMAC_SIZE 0x30000 > + > +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) > +#define AR933X_UART_SIZE 0x14 > +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) > +#define AR933X_GMAC_SIZE 0x04 > +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) > +#define AR933X_WMAC_SIZE 0x20000 > +#define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) > +#define AR933X_RTC_SIZE 0x1000 > +#define AR933X_EHCI_BASE 0x1b000000 > +#define AR933X_EHCI_SIZE 0x1000 > +#define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) > +#define AR933X_SRIF_SIZE 0x1000 > + > +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) > +#define AR934X_GMAC_SIZE 0x14 > +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) > +#define AR934X_WMAC_SIZE 0x20000 > +#define AR934X_EHCI_BASE 0x1b000000 > +#define AR934X_EHCI_SIZE 0x200 > +#define AR934X_NFC_BASE 0x1b000200 > +#define AR934X_NFC_SIZE 0xb8 > +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) > +#define AR934X_SRIF_SIZE 0x1000 > + > +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) > +#define QCA953X_GMAC_SIZE 0x14 > +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) > +#define QCA953X_WMAC_SIZE 0x20000 > +#define QCA953X_EHCI_BASE 0x1b000000 > +#define QCA953X_EHCI_SIZE 0x200 > +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) > +#define QCA953X_SRIF_SIZE 0x1000 > + > +#define QCA953X_PCI_CFG_BASE0 0x14000000 > +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) > +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) > +#define QCA953X_PCI_MEM_BASE0 0x10000000 > +#define QCA953X_PCI_MEM_SIZE 0x02000000 > + > +#define QCA955X_PCI_MEM_BASE0 0x10000000 > +#define QCA955X_PCI_MEM_BASE1 0x12000000 > +#define QCA955X_PCI_MEM_SIZE 0x02000000 > +#define QCA955X_PCI_CFG_BASE0 0x14000000 > +#define QCA955X_PCI_CFG_BASE1 0x16000000 > +#define QCA955X_PCI_CFG_SIZE 0x1000 > +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) > +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) > +#define QCA955X_PCI_CRP_SIZE 0x1000 > +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) > +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) > +#define QCA955X_PCI_CTRL_SIZE 0x100 > + > +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) > +#define QCA955X_GMAC_SIZE 0x40 > +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) > +#define QCA955X_WMAC_SIZE 0x20000 > +#define QCA955X_EHCI0_BASE 0x1b000000 > +#define QCA955X_EHCI1_BASE 0x1b400000 > +#define QCA955X_EHCI_SIZE 0x1000 > +#define QCA955X_NFC_BASE 0x1b800200 > +#define QCA955X_NFC_SIZE 0xb8 > + > +#define QCA956X_PCI_MEM_BASE1 0x12000000 > +#define QCA956X_PCI_MEM_SIZE 0x02000000 > +#define QCA956X_PCI_CFG_BASE1 0x16000000 > +#define QCA956X_PCI_CFG_SIZE 0x1000 > +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) > +#define QCA956X_PCI_CRP_SIZE 0x1000 > +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) > +#define QCA956X_PCI_CTRL_SIZE 0x100 > + > +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) > +#define QCA956X_WMAC_SIZE 0x20000 > +#define QCA956X_EHCI0_BASE 0x1b000000 > +#define QCA956X_EHCI1_BASE 0x1b400000 > +#define QCA956X_EHCI_SIZE 0x200 > +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) > +#define QCA956X_GMAC_SIZE 0x64 > + > +#define AR9300_OTP_BASE 0x14000 > +#define AR9300_OTP_STATUS 0x15f18 > +#define AR9300_OTP_STATUS_TYPE 0x7 > +#define AR9300_OTP_STATUS_VALID 0x4 > +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 > +#define AR9300_OTP_STATUS_SM_BUSY 0x1 > +#define AR9300_OTP_READ_DATA 0x15f1c > + > +/* > + * DDR_CTRL block > + */ > +#define AR71XX_DDR_REG_CONFIG 0x00 > +#define AR71XX_DDR_REG_CONFIG2 0x04 > +#define AR71XX_DDR_REG_MODE 0x08 > +#define AR71XX_DDR_REG_EMR 0x0c > +#define AR71XX_DDR_REG_CONTROL 0x10 > +#define AR71XX_DDR_REG_REFRESH 0x14 > +#define AR71XX_DDR_REG_RD_CYCLE 0x18 > +#define AR71XX_DDR_REG_TAP_CTRL0 0x1c > +#define AR71XX_DDR_REG_TAP_CTRL1 0x20 > + > +#define AR71XX_DDR_REG_PCI_WIN0 0x7c > +#define AR71XX_DDR_REG_PCI_WIN1 0x80 > +#define AR71XX_DDR_REG_PCI_WIN2 0x84 > +#define AR71XX_DDR_REG_PCI_WIN3 0x88 > +#define AR71XX_DDR_REG_PCI_WIN4 0x8c > +#define AR71XX_DDR_REG_PCI_WIN5 0x90 > +#define AR71XX_DDR_REG_PCI_WIN6 0x94 > +#define AR71XX_DDR_REG_PCI_WIN7 0x98 > +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c > +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 > +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 > +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 > + > +#define AR724X_DDR_REG_FLUSH_GE0 0x7c > +#define AR724X_DDR_REG_FLUSH_GE1 0x80 > +#define AR724X_DDR_REG_FLUSH_USB 0x84 > +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 > + > +#define AR913X_DDR_REG_FLUSH_GE0 0x7c > +#define AR913X_DDR_REG_FLUSH_GE1 0x80 > +#define AR913X_DDR_REG_FLUSH_USB 0x84 > +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 > + > +#define AR933X_DDR_REG_FLUSH_GE0 0x7c > +#define AR933X_DDR_REG_FLUSH_GE1 0x80 > +#define AR933X_DDR_REG_FLUSH_USB 0x84 > +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 > +#define AR933X_DDR_REG_DDR2_CONFIG 0x8c > +#define AR933X_DDR_REG_EMR2 0x90 > +#define AR933X_DDR_REG_EMR3 0x94 > +#define AR933X_DDR_REG_BURST 0x98 > +#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c > +#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c > +#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c > + > +#define AR934X_DDR_REG_FLUSH_GE0 0x9c > +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 > +#define AR934X_DDR_REG_FLUSH_USB 0xa4 > +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 > +#define AR934X_DDR_REG_FLUSH_WMAC 0xac > + > +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c > +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 > +#define QCA953X_DDR_REG_FLUSH_USB 0xa4 > +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 > +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac > + > +/* > + * PLL block > + */ > +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 > +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 > +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 > +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 > + > +#define AR71XX_PLL_DIV_SHIFT 3 > +#define AR71XX_PLL_DIV_MASK 0x1f > +#define AR71XX_CPU_DIV_SHIFT 16 > +#define AR71XX_CPU_DIV_MASK 0x3 > +#define AR71XX_DDR_DIV_SHIFT 18 > +#define AR71XX_DDR_DIV_MASK 0x3 > +#define AR71XX_AHB_DIV_SHIFT 20 > +#define AR71XX_AHB_DIV_MASK 0x7 > + > +#define AR71XX_ETH0_PLL_SHIFT 17 > +#define AR71XX_ETH1_PLL_SHIFT 19 > + > +#define AR724X_PLL_REG_CPU_CONFIG 0x00 > +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 > + > +#define AR724X_PLL_DIV_SHIFT 0 > +#define AR724X_PLL_DIV_MASK 0x3ff > +#define AR724X_PLL_REF_DIV_SHIFT 10 > +#define AR724X_PLL_REF_DIV_MASK 0xf > +#define AR724X_AHB_DIV_SHIFT 19 > +#define AR724X_AHB_DIV_MASK 0x1 > +#define AR724X_DDR_DIV_SHIFT 22 > +#define AR724X_DDR_DIV_MASK 0x3 > + > +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c > + > +#define AR913X_PLL_REG_CPU_CONFIG 0x00 > +#define AR913X_PLL_REG_ETH_CONFIG 0x04 > +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 > +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 > + > +#define AR913X_PLL_DIV_SHIFT 0 > +#define AR913X_PLL_DIV_MASK 0x3ff > +#define AR913X_DDR_DIV_SHIFT 22 > +#define AR913X_DDR_DIV_MASK 0x3 > +#define AR913X_AHB_DIV_SHIFT 19 > +#define AR913X_AHB_DIV_MASK 0x1 > + > +#define AR913X_ETH0_PLL_SHIFT 20 > +#define AR913X_ETH1_PLL_SHIFT 22 > + > +#define AR933X_PLL_CPU_CONFIG_REG 0x00 > +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 > + > +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 > +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f > +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 > +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f > +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 > +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 > + > +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) > +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 > +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 > +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 > +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 > +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 > +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 > + > +#define AR934X_PLL_CPU_CONFIG_REG 0x00 > +#define AR934X_PLL_DDR_CONFIG_REG 0x04 > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 > +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 > +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c > + > +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 > +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f > +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 > +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f > +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 > +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f > +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 > +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 > + > +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 > +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff > +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 > +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f > +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 > +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f > +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 > +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 > + > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) > +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) > + > +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) > + > +#define QCA953X_PLL_CPU_CONFIG_REG 0x00 > +#define QCA953X_PLL_DDR_CONFIG_REG 0x04 > +#define QCA953X_PLL_CLK_CTRL_REG 0x08 > +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 > +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c > +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 > + > +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 > +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f > +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 > +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f > +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 > +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f > +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 > +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 > + > +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 > +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff > +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 > +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f > +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 > +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f > +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 > +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 > + > +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) > +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) > +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) > +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 > +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f > +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 > +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f > +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 > +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f > +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) > +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) > +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) > + > +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 > +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 > +#define QCA955X_PLL_CLK_CTRL_REG 0x08 > +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 > +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 > + > +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 > +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f > +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 > +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f > +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 > +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f > +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 > +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 > + > +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 > +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff > +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 > +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f > +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 > +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f > +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 > +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 > + > +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) > +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) > +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) > +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 > +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f > +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 > +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f > +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 > +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f > +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) > +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) > +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) > + > +#define QCA956X_PLL_CPU_CONFIG_REG 0x00 > +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 > +#define QCA956X_PLL_DDR_CONFIG_REG 0x08 > +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c > +#define QCA956X_PLL_CLK_CTRL_REG 0x10 > + > +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 > +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f > +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 > +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 > + > +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 > +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f > +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 > +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff > +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 > +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff > + > +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 > +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f > +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 > +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 > + > +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 > +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f > +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 > +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff > +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 > +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff > + > +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) > +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) > +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) > +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 > +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f > +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 > +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f > +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 > +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f > +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) > +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) > +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) > + > +/* > + * USB_CONFIG block > + */ > +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 > +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 > + > +/* > + * RESET block > + */ > +#define AR71XX_RESET_REG_TIMER 0x00 > +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 > +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 > +#define AR71XX_RESET_REG_WDOG 0x0c > +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 > +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 > +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 > +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c > +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 > +#define AR71XX_RESET_REG_RESET_MODULE 0x24 > +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c > +#define AR71XX_RESET_REG_PERFC0 0x30 > +#define AR71XX_RESET_REG_PERFC1 0x34 > +#define AR71XX_RESET_REG_REV_ID 0x90 > + > +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 > +#define AR913X_RESET_REG_RESET_MODULE 0x1c > +#define AR913X_RESET_REG_PERF_CTRL 0x20 > +#define AR913X_RESET_REG_PERFC0 0x24 > +#define AR913X_RESET_REG_PERFC1 0x28 > + > +#define AR724X_RESET_REG_RESET_MODULE 0x1c > + > +#define AR933X_RESET_REG_RESET_MODULE 0x1c > +#define AR933X_RESET_REG_BOOTSTRAP 0xac > + > +#define AR934X_RESET_REG_RESET_MODULE 0x1c > +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 > +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac > + > +#define QCA953X_RESET_REG_RESET_MODULE 0x1c > +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 > +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac > + > +#define QCA955X_RESET_REG_RESET_MODULE 0x1c > +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 > +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac > + > +#define QCA956X_RESET_REG_RESET_MODULE 0x1c > +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 > +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac > + > +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) > +#define MISC_INT_ETHSW BIT(12) > +#define MISC_INT_TIMER4 BIT(10) > +#define MISC_INT_TIMER3 BIT(9) > +#define MISC_INT_TIMER2 BIT(8) > +#define MISC_INT_DMA BIT(7) > +#define MISC_INT_OHCI BIT(6) > +#define MISC_INT_PERFC BIT(5) > +#define MISC_INT_WDOG BIT(4) > +#define MISC_INT_UART BIT(3) > +#define MISC_INT_GPIO BIT(2) > +#define MISC_INT_ERROR BIT(1) > +#define MISC_INT_TIMER BIT(0) > + > +#define AR71XX_RESET_EXTERNAL BIT(28) > +#define AR71XX_RESET_FULL_CHIP BIT(24) > +#define AR71XX_RESET_CPU_NMI BIT(21) > +#define AR71XX_RESET_CPU_COLD BIT(20) > +#define AR71XX_RESET_DMA BIT(19) > +#define AR71XX_RESET_SLIC BIT(18) > +#define AR71XX_RESET_STEREO BIT(17) > +#define AR71XX_RESET_DDR BIT(16) > +#define AR71XX_RESET_GE1_MAC BIT(13) > +#define AR71XX_RESET_GE1_PHY BIT(12) > +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) > +#define AR71XX_RESET_GE0_MAC BIT(9) > +#define AR71XX_RESET_GE0_PHY BIT(8) > +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) > +#define AR71XX_RESET_USB_HOST BIT(5) > +#define AR71XX_RESET_USB_PHY BIT(4) > +#define AR71XX_RESET_PCI_BUS BIT(1) > +#define AR71XX_RESET_PCI_CORE BIT(0) > + > +#define AR7240_RESET_USB_HOST BIT(5) > +#define AR7240_RESET_OHCI_DLL BIT(3) > + > +#define AR724X_RESET_GE1_MDIO BIT(23) > +#define AR724X_RESET_GE0_MDIO BIT(22) > +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) > +#define AR724X_RESET_PCIE_PHY BIT(7) > +#define AR724X_RESET_PCIE BIT(6) > +#define AR724X_RESET_USB_HOST BIT(5) > +#define AR724X_RESET_USB_PHY BIT(4) > +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) > + > +#define AR913X_RESET_AMBA2WMAC BIT(22) > +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) > +#define AR913X_RESET_USB_HOST BIT(5) > +#define AR913X_RESET_USB_PHY BIT(4) > + > +#define AR933X_RESET_GE1_MDIO BIT(23) > +#define AR933X_RESET_GE0_MDIO BIT(22) > +#define AR933X_RESET_GE1_MAC BIT(13) > +#define AR933X_RESET_WMAC BIT(11) > +#define AR933X_RESET_GE0_MAC BIT(9) > +#define AR933X_RESET_USB_HOST BIT(5) > +#define AR933X_RESET_USB_PHY BIT(4) > +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) > + > +#define AR934X_RESET_HOST BIT(31) > +#define AR934X_RESET_SLIC BIT(30) > +#define AR934X_RESET_HDMA BIT(29) > +#define AR934X_RESET_EXTERNAL BIT(28) > +#define AR934X_RESET_RTC BIT(27) > +#define AR934X_RESET_PCIE_EP_INT BIT(26) > +#define AR934X_RESET_CHKSUM_ACC BIT(25) > +#define AR934X_RESET_FULL_CHIP BIT(24) > +#define AR934X_RESET_GE1_MDIO BIT(23) > +#define AR934X_RESET_GE0_MDIO BIT(22) > +#define AR934X_RESET_CPU_NMI BIT(21) > +#define AR934X_RESET_CPU_COLD BIT(20) > +#define AR934X_RESET_HOST_RESET_INT BIT(19) > +#define AR934X_RESET_PCIE_EP BIT(18) > +#define AR934X_RESET_UART1 BIT(17) > +#define AR934X_RESET_DDR BIT(16) > +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) > +#define AR934X_RESET_NANDF BIT(14) > +#define AR934X_RESET_GE1_MAC BIT(13) > +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) > +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) > +#define AR934X_RESET_HOST_DMA_INT BIT(10) > +#define AR934X_RESET_GE0_MAC BIT(9) > +#define AR934X_RESET_ETH_SWITCH BIT(8) > +#define AR934X_RESET_PCIE_PHY BIT(7) > +#define AR934X_RESET_PCIE BIT(6) > +#define AR934X_RESET_USB_HOST BIT(5) > +#define AR934X_RESET_USB_PHY BIT(4) > +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) > +#define AR934X_RESET_LUT BIT(2) > +#define AR934X_RESET_MBOX BIT(1) > +#define AR934X_RESET_I2S BIT(0) > + > +#define QCA953X_RESET_USB_EXT_PWR BIT(29) > +#define QCA953X_RESET_EXTERNAL BIT(28) > +#define QCA953X_RESET_RTC BIT(27) > +#define QCA953X_RESET_FULL_CHIP BIT(24) > +#define QCA953X_RESET_GE1_MDIO BIT(23) > +#define QCA953X_RESET_GE0_MDIO BIT(22) > +#define QCA953X_RESET_CPU_NMI BIT(21) > +#define QCA953X_RESET_CPU_COLD BIT(20) > +#define QCA953X_RESET_DDR BIT(16) > +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) > +#define QCA953X_RESET_GE1_MAC BIT(13) > +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) > +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) > +#define QCA953X_RESET_GE0_MAC BIT(9) > +#define QCA953X_RESET_ETH_SWITCH BIT(8) > +#define QCA953X_RESET_PCIE_PHY BIT(7) > +#define QCA953X_RESET_PCIE BIT(6) > +#define QCA953X_RESET_USB_HOST BIT(5) > +#define QCA953X_RESET_USB_PHY BIT(4) > +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) > + > +#define QCA955X_RESET_HOST BIT(31) > +#define QCA955X_RESET_SLIC BIT(30) > +#define QCA955X_RESET_HDMA BIT(29) > +#define QCA955X_RESET_EXTERNAL BIT(28) > +#define QCA955X_RESET_RTC BIT(27) > +#define QCA955X_RESET_PCIE_EP_INT BIT(26) > +#define QCA955X_RESET_CHKSUM_ACC BIT(25) > +#define QCA955X_RESET_FULL_CHIP BIT(24) > +#define QCA955X_RESET_GE1_MDIO BIT(23) > +#define QCA955X_RESET_GE0_MDIO BIT(22) > +#define QCA955X_RESET_CPU_NMI BIT(21) > +#define QCA955X_RESET_CPU_COLD BIT(20) > +#define QCA955X_RESET_HOST_RESET_INT BIT(19) > +#define QCA955X_RESET_PCIE_EP BIT(18) > +#define QCA955X_RESET_UART1 BIT(17) > +#define QCA955X_RESET_DDR BIT(16) > +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) > +#define QCA955X_RESET_NANDF BIT(14) > +#define QCA955X_RESET_GE1_MAC BIT(13) > +#define QCA955X_RESET_SGMII_ANALOG BIT(12) > +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) > +#define QCA955X_RESET_HOST_DMA_INT BIT(10) > +#define QCA955X_RESET_GE0_MAC BIT(9) > +#define QCA955X_RESET_SGMII BIT(8) > +#define QCA955X_RESET_PCIE_PHY BIT(7) > +#define QCA955X_RESET_PCIE BIT(6) > +#define QCA955X_RESET_USB_HOST BIT(5) > +#define QCA955X_RESET_USB_PHY BIT(4) > +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) > +#define QCA955X_RESET_LUT BIT(2) > +#define QCA955X_RESET_MBOX BIT(1) > +#define QCA955X_RESET_I2S BIT(0) > + > +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) > +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) > +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) > + > +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) > +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) > +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) > +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) > +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) > +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) > +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) > +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) > +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) > +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) > +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) > +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) > +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) > +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) > +#define AR934X_BOOTSTRAP_DDR1 BIT(0) > + > +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) > +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) > +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) > +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) > +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) > +#define QCA953X_BOOTSTRAP_DDR1 BIT(0) > + > +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) > + > +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) > + > +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) > +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) > +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) > +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) > +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) > +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) > +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) > +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) > +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) > +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ > + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ > + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) > + > +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ > + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ > + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ > + AR934X_PCIE_WMAC_INT_PCIE_RC3) > + > +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) > +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) > +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) > +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) > +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) > +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) > +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) > +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) > +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) > +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ > + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ > + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) > + > +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ > + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ > + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ > + QCA953X_PCIE_WMAC_INT_PCIE_RC3) > + > +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) > +#define QCA955X_EXT_INT_WMAC_TX BIT(1) > +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) > +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) > +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) > +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) > +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) > +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) > +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) > +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) > +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) > +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) > +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) > +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) > +#define QCA955X_EXT_INT_USB1 BIT(24) > +#define QCA955X_EXT_INT_USB2 BIT(28) > + > +#define QCA955X_EXT_INT_WMAC_ALL \ > + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ > + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) > + > +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ > + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ > + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ > + QCA955X_EXT_INT_PCIE_RC1_INT3) > + > +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ > + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ > + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ > + QCA955X_EXT_INT_PCIE_RC2_INT3) > + > +#define QCA956X_EXT_INT_WMAC_MISC BIT(0) > +#define QCA956X_EXT_INT_WMAC_TX BIT(1) > +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) > +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) > +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) > +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) > +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) > +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) > +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) > +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) > +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) > +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) > +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) > +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) > +#define QCA956X_EXT_INT_USB1 BIT(24) > +#define QCA956X_EXT_INT_USB2 BIT(28) > + > +#define QCA956X_EXT_INT_WMAC_ALL \ > + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ > + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) > + > +#define QCA956X_EXT_INT_PCIE_RC1_ALL \ > + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ > + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ > + QCA956X_EXT_INT_PCIE_RC1_INT3) > + > +#define QCA956X_EXT_INT_PCIE_RC2_ALL \ > + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ > + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ > + QCA956X_EXT_INT_PCIE_RC2_INT3) > + > +#define REV_ID_MAJOR_MASK 0xfff0 > +#define REV_ID_MAJOR_AR71XX 0x00a0 > +#define REV_ID_MAJOR_AR913X 0x00b0 > +#define REV_ID_MAJOR_AR7240 0x00c0 > +#define REV_ID_MAJOR_AR7241 0x0100 > +#define REV_ID_MAJOR_AR7242 0x1100 > +#define REV_ID_MAJOR_AR9330 0x0110 > +#define REV_ID_MAJOR_AR9331 0x1110 > +#define REV_ID_MAJOR_AR9341 0x0120 > +#define REV_ID_MAJOR_AR9342 0x1120 > +#define REV_ID_MAJOR_AR9344 0x2120 > +#define REV_ID_MAJOR_QCA9533 0x0140 > +#define REV_ID_MAJOR_QCA9533_V2 0x0160 > +#define REV_ID_MAJOR_QCA9556 0x0130 > +#define REV_ID_MAJOR_QCA9558 0x1130 > +#define REV_ID_MAJOR_TP9343 0x0150 > +#define REV_ID_MAJOR_QCA9561 0x1150 > + > +#define AR71XX_REV_ID_MINOR_MASK 0x3 > +#define AR71XX_REV_ID_MINOR_AR7130 0x0 > +#define AR71XX_REV_ID_MINOR_AR7141 0x1 > +#define AR71XX_REV_ID_MINOR_AR7161 0x2 > +#define AR71XX_REV_ID_REVISION_MASK 0x3 > +#define AR71XX_REV_ID_REVISION_SHIFT 2 > + > +#define AR913X_REV_ID_MINOR_MASK 0x3 > +#define AR913X_REV_ID_MINOR_AR9130 0x0 > +#define AR913X_REV_ID_MINOR_AR9132 0x1 > +#define AR913X_REV_ID_REVISION_MASK 0x3 > +#define AR913X_REV_ID_REVISION_SHIFT 2 > + > +#define AR933X_REV_ID_REVISION_MASK 0x3 > + > +#define AR724X_REV_ID_REVISION_MASK 0x3 > + > +#define AR934X_REV_ID_REVISION_MASK 0xf > + > +#define QCA953X_REV_ID_REVISION_MASK 0xf > + > +#define QCA955X_REV_ID_REVISION_MASK 0xf > + > +#define QCA956X_REV_ID_REVISION_MASK 0xf > + > +/* > + * RTC block > + */ > +#define AR933X_RTC_REG_RESET 0x40 > +#define AR933X_RTC_REG_STATUS 0x44 > +#define AR933X_RTC_REG_DERIVED 0x48 > +#define AR933X_RTC_REG_FORCE_WAKE 0x4c > +#define AR933X_RTC_REG_INT_CAUSE 0x50 > +#define AR933X_RTC_REG_CAUSE_CLR 0x50 > +#define AR933X_RTC_REG_INT_ENABLE 0x54 > +#define AR933X_RTC_REG_INT_MASKE 0x58 > + > +/* > + * SPI block > + */ > +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ > +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ > +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ > +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ > + > +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ > + > +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ > +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f > + > +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ > +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ > +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) > +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) > +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) > +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) > +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ > + AR71XX_SPI_IOC_CS2) > + > +/* > + * GPIO block > + */ > +#define AR71XX_GPIO_REG_OE 0x00 > +#define AR71XX_GPIO_REG_IN 0x04 > +#define AR71XX_GPIO_REG_OUT 0x08 > +#define AR71XX_GPIO_REG_SET 0x0c > +#define AR71XX_GPIO_REG_CLEAR 0x10 > +#define AR71XX_GPIO_REG_INT_MODE 0x14 > +#define AR71XX_GPIO_REG_INT_TYPE 0x18 > +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c > +#define AR71XX_GPIO_REG_INT_PENDING 0x20 > +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 > +#define AR71XX_GPIO_REG_FUNC 0x28 > +#define AR933X_GPIO_REG_FUNC 0x30 > + > +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c > +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 > +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 > +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 > +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c > +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 > +#define AR934X_GPIO_REG_FUNC 0x6c > + > +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c > +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 > +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 > +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 > +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c > +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 > +#define QCA953X_GPIO_REG_FUNC 0x6c > + > +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 > +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 > +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 > +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 > +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 > +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 > +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 > +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 > +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 > +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 > + > +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c > +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 > +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 > +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 > +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c > +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 > +#define QCA955X_GPIO_REG_FUNC 0x6c > + > +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c > +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 > +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 > +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 > +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c > +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 > +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 > +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 > +#define QCA956X_GPIO_REG_FUNC 0x6c > + > +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 > +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 > + > +#define AR71XX_GPIO_COUNT 16 > +#define AR7240_GPIO_COUNT 18 > +#define AR7241_GPIO_COUNT 20 > +#define AR913X_GPIO_COUNT 22 > +#define AR933X_GPIO_COUNT 30 > +#define AR934X_GPIO_COUNT 23 > +#define QCA953X_GPIO_COUNT 18 > +#define QCA955X_GPIO_COUNT 24 > +#define QCA956X_GPIO_COUNT 23 > + > +/* > + * SRIF block > + */ > +#define AR933X_SRIF_DDR_DPLL1_REG 0x240 > +#define AR933X_SRIF_DDR_DPLL2_REG 0x244 > +#define AR933X_SRIF_DDR_DPLL3_REG 0x248 > +#define AR933X_SRIF_DDR_DPLL4_REG 0x24c > + > +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 > +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 > +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 > + > +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 > +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 > +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 > + > +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 > +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f > +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 > +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff > +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff > + > +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) > +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 > +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 > + > +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 > +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 > +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 > + > +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 > +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 > +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 > + > +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 > +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f > +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 > +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff > +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff > + > +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) > +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 > +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 > + > +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) > +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) > +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) > +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) > +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) > +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) > +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) > + > +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) > +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) > +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) > +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) > +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) > +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) > +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) > +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) > +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) > +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) > +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) > +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) > +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) > +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) > +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) > +#define AR724X_GPIO_FUNC_UART_EN BIT(1) > +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) > + > +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) > +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) > +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) > +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) > +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) > +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) > +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) > +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) > +#define AR913X_GPIO_FUNC_UART_EN BIT(8) > +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) > + > +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) > +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) > +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) > +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) > +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) > +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) > +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) > +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) > +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) > +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) > +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) > +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) > +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) > +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) > +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) > +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) > +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) > +#define AR933X_GPIO_FUNC_UART_EN BIT(1) > +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) > + > +#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) > + > +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) > +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) > +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) > +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) > +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) > +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) > +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) > +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) > +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) > + > +#define AR934X_GPIO_OUT_GPIO 0 > +#define AR934X_GPIO_OUT_SPI_CS1 7 > +#define AR934X_GPIO_OUT_LED_LINK0 41 > +#define AR934X_GPIO_OUT_LED_LINK1 42 > +#define AR934X_GPIO_OUT_LED_LINK2 43 > +#define AR934X_GPIO_OUT_LED_LINK3 44 > +#define AR934X_GPIO_OUT_LED_LINK4 45 > +#define AR934X_GPIO_OUT_EXT_LNA0 46 > +#define AR934X_GPIO_OUT_EXT_LNA1 47 > + > +#define QCA955X_GPIO_OUT_GPIO 0 > + > +/* > + * MII_CTRL block > + */ > +#define AR71XX_MII_REG_MII0_CTRL 0x00 > +#define AR71XX_MII_REG_MII1_CTRL 0x04 > + > +#define AR71XX_MII_CTRL_IF_MASK 3 > +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 > +#define AR71XX_MII_CTRL_SPEED_MASK 3 > +#define AR71XX_MII_CTRL_SPEED_10 0 > +#define AR71XX_MII_CTRL_SPEED_100 1 > +#define AR71XX_MII_CTRL_SPEED_1000 2 > + > +#define AR71XX_MII0_CTRL_IF_GMII 0 > +#define AR71XX_MII0_CTRL_IF_MII 1 > +#define AR71XX_MII0_CTRL_IF_RGMII 2 > +#define AR71XX_MII0_CTRL_IF_RMII 3 > + > +#define AR71XX_MII1_CTRL_IF_RGMII 0 > +#define AR71XX_MII1_CTRL_IF_RMII 1 > + > +/* > + * AR933X GMAC interface > + */ > +#define AR933X_GMAC_REG_ETH_CFG 0x00 > + > +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) > +#define AR933X_ETH_CFG_MII_GE0 BIT(1) > +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) > +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) > +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) > +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) > +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) > +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) > +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) > +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 > +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) > + > +/* > + * AR934X GMAC Interface > + */ > +#define AR934X_GMAC_REG_ETH_CFG 0x00 > + > +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) > +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) > +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) > +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) > +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) > +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) > +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) > +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) > +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) > +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) > +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) > +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) > +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) > +#define AR934X_ETH_CFG_RXD_DELAY BIT(14) > +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 > +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 > +#define AR934X_ETH_CFG_RDV_DELAY BIT(16) > +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 > +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 > + > +/* > + * QCA953X GMAC Interface > + */ > +#define QCA953X_GMAC_REG_ETH_CFG 0x00 > + > +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) > +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) > +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) > +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) > + > +/* > + * QCA955X GMAC Interface > + */ > + > +#define QCA955X_GMAC_REG_ETH_CFG 0x00 > + > +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) > +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) > + > +#endif /* __ASM_AR71XX_H */ > diff --git a/arch/mips/include/asm/arch-ath79/ar933x_uart.h b/arch/mips/include/asm/arch-ath79/ar933x_uart.h > new file mode 100644 > index 0000000..22be22e > --- /dev/null > +++ b/arch/mips/include/asm/arch-ath79/ar933x_uart.h > @@ -0,0 +1,67 @@ > +/* > + * Atheros AR933X UART defines > + * > + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + */ > + > +#ifndef __AR933X_UART_H > +#define __AR933X_UART_H > + > +#define AR933X_UART_REGS_SIZE 20 > +#define AR933X_UART_FIFO_SIZE 16 > + > +#define AR933X_UART_DATA_REG 0x00 > +#define AR933X_UART_CS_REG 0x04 > +#define AR933X_UART_CLOCK_REG 0x08 > +#define AR933X_UART_INT_REG 0x0c > +#define AR933X_UART_INT_EN_REG 0x10 > + > +#define AR933X_UART_DATA_TX_RX_MASK 0xff > +#define AR933X_UART_DATA_RX_CSR BIT(8) > +#define AR933X_UART_DATA_TX_CSR BIT(9) > + > +#define AR933X_UART_CS_PARITY_S 0 > +#define AR933X_UART_CS_PARITY_M 0x3 > +#define AR933X_UART_CS_PARITY_NONE 0 > +#define AR933X_UART_CS_PARITY_ODD 1 > +#define AR933X_UART_CS_PARITY_EVEN 2 > +#define AR933X_UART_CS_IF_MODE_S 2 > +#define AR933X_UART_CS_IF_MODE_M 0x3 > +#define AR933X_UART_CS_IF_MODE_NONE 0 > +#define AR933X_UART_CS_IF_MODE_DTE 1 > +#define AR933X_UART_CS_IF_MODE_DCE 2 > +#define AR933X_UART_CS_FLOW_CTRL_S 4 > +#define AR933X_UART_CS_FLOW_CTRL_M 0x3 > +#define AR933X_UART_CS_DMA_EN BIT(6) > +#define AR933X_UART_CS_TX_READY_ORIDE BIT(7) > +#define AR933X_UART_CS_RX_READY_ORIDE BIT(8) > +#define AR933X_UART_CS_TX_READY BIT(9) > +#define AR933X_UART_CS_RX_BREAK BIT(10) > +#define AR933X_UART_CS_TX_BREAK BIT(11) > +#define AR933X_UART_CS_HOST_INT BIT(12) > +#define AR933X_UART_CS_HOST_INT_EN BIT(13) > +#define AR933X_UART_CS_TX_BUSY BIT(14) > +#define AR933X_UART_CS_RX_BUSY BIT(15) > + > +#define AR933X_UART_CLOCK_STEP_M 0xffff > +#define AR933X_UART_CLOCK_SCALE_M 0xfff > +#define AR933X_UART_CLOCK_SCALE_S 16 > +#define AR933X_UART_CLOCK_STEP_S 0 > + > +#define AR933X_UART_INT_RX_VALID BIT(0) > +#define AR933X_UART_INT_TX_READY BIT(1) > +#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2) > +#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3) > +#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4) > +#define AR933X_UART_INT_RX_PARITY_ERR BIT(5) > +#define AR933X_UART_INT_RX_BREAK_ON BIT(6) > +#define AR933X_UART_INT_RX_BREAK_OFF BIT(7) > +#define AR933X_UART_INT_RX_FULL BIT(8) > +#define AR933X_UART_INT_TX_EMPTY BIT(9) > +#define AR933X_UART_INT_ALLINTS 0x3ff > + > +#endif /* __AR933X_UART_H */ > diff --git a/arch/mips/include/asm/arch-ath79/ath79.h b/arch/mips/include/asm/arch-ath79/ath79.h > new file mode 100644 > index 0000000..0ad97c0 > --- /dev/null > +++ b/arch/mips/include/asm/arch-ath79/ath79.h > @@ -0,0 +1,145 @@ > +/* > + * Atheros AR71XX/AR724X/AR913X common definitions > + * > + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> > + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> > + * > + * Parts of this file are based on Atheros' 2.6.15 BSP > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + */ > + > +#ifndef __ASM_MACH_ATH79_H > +#define __ASM_MACH_ATH79_H > + > +#include <linux/types.h> > + > +enum ath79_soc_type { > + ATH79_SOC_UNKNOWN, > + ATH79_SOC_AR7130, > + ATH79_SOC_AR7141, > + ATH79_SOC_AR7161, > + ATH79_SOC_AR7240, > + ATH79_SOC_AR7241, > + ATH79_SOC_AR7242, > + ATH79_SOC_AR9130, > + ATH79_SOC_AR9132, > + ATH79_SOC_AR9330, > + ATH79_SOC_AR9331, > + ATH79_SOC_AR9341, > + ATH79_SOC_AR9342, > + ATH79_SOC_AR9344, > + ATH79_SOC_QCA9533, > + ATH79_SOC_QCA9556, > + ATH79_SOC_QCA9558, > + ATH79_SOC_TP9343, > + ATH79_SOC_QCA9561, > +}; > + > +extern enum ath79_soc_type get_soc_type(void); add one empty line and you can drop the 'extern' > +static inline int soc_is_ar71xx(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR7130 || > + soc == ATH79_SOC_AR7141 || > + soc == ATH79_SOC_AR7161; > +} > + > +static inline int soc_is_ar724x(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR7240 || > + soc == ATH79_SOC_AR7241 || > + soc == ATH79_SOC_AR7242; > +} > + > +static inline int soc_is_ar7240(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR7240; > +} > + > +static inline int soc_is_ar7241(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR7241; > +} > + > +static inline int soc_is_ar7242(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR7242; > +} > + > +static inline int soc_is_ar913x(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR9130 || > + soc == ATH79_SOC_AR9132; > +} > + > +static inline int soc_is_ar933x(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR9330 || > + soc == ATH79_SOC_AR9331; > +} > + > +static inline int soc_is_ar9341(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR9341; > +} > + > +static inline int soc_is_ar9342(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR9342; > +} > + > +static inline int soc_is_ar9344(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_AR9344; > +} > + > +static inline int soc_is_ar934x(enum ath79_soc_type soc) > +{ > + return soc_is_ar9341(soc) || > + soc_is_ar9342(soc) || > + soc_is_ar9344(soc); > +} > + > +static inline int soc_is_qca9533(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_QCA9533; > +} > + > +static inline int soc_is_qca953x(enum ath79_soc_type soc) > +{ > + return soc_is_qca9533(soc); > +} > + > +static inline int soc_is_qca9556(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_QCA9556; > +} > + > +static inline int soc_is_qca9558(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_QCA9558; > +} > + > +static inline int soc_is_qca955x(enum ath79_soc_type soc) > +{ > + return soc_is_qca9556(soc) || soc_is_qca9558(soc); > +} > + > +static inline int soc_is_tp9343(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_TP9343; > +} > + > +static inline int soc_is_qca9561(enum ath79_soc_type soc) > +{ > + return soc == ATH79_SOC_QCA9561; > +} > + > +static inline int soc_is_qca956x(enum ath79_soc_type soc) > +{ > + return soc_is_tp9343(soc) || soc_is_qca9561(soc); > +} > + > +#endif /* __ASM_MACH_ATH79_H */ > diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile > new file mode 100644 > index 0000000..d042b47 > --- /dev/null > +++ b/arch/mips/mach-ath79/Makefile > @@ -0,0 +1,12 @@ > +# > +# (C) Copyright 2011 > +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. there is no need to keep old copyright references in Makefile's. With Kbuild there is no real code in it anymore. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += reset.o > +obj-y += cpu.o > +obj-y += dram.o > + > +obj-$(CONFIG_SOC_AR933X) += ar933x/ > diff --git a/arch/mips/mach-ath79/ar933x/Makefile b/arch/mips/mach-ath79/ar933x/Makefile > new file mode 100644 > index 0000000..7739f22 > --- /dev/null > +++ b/arch/mips/mach-ath79/ar933x/Makefile > @@ -0,0 +1,9 @@ > +# > +# (C) Copyright 2011 > +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += lowlevel_init.o > +obj-y += ddr_tap.o > diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S b/arch/mips/mach-ath79/ar933x/ddr_tap.S > new file mode 100644 > index 0000000..34a4613 > --- /dev/null > +++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S > @@ -0,0 +1,272 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <config.h> > +#include <asm/regdef.h> > +#include <asm/mipsregs.h> > +#include <asm/addrspace.h> > +#include <asm/arch/ar71xx_regs.h> > + > +#define DDR_TAP_CTRL0 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_TAP_CTRL0) > +#define DDR_TAP_CTRL1 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_TAP_CTRL1) > +#define DRAM_K0(x) KSEG0ADDR(x) > +#define DRAM_K1(x) KSEG1ADDR(x) > + > + .text > + .set noreorder > + .set mips32 you only need .set noreorder > + > + .globl ddr_tap_init > +ddr_tap_init: use LEAF() and END() macros example: LEAF(ddr_tap_init) > + /* Tap settings for the DDR */ > + li t0, 0xffffffff > + li t1, DRAM_K0(0x500000) > + sw t0, 0x0(t1) > + sw t0, 0x4(t1) > + sw t0, 0x8(t1) > + sw t0, 0xc(t1) > + nop > + nop > + > + li t8, DRAM_K1(0x2000) > + li t0, 0x00 > + li t1, 0x100 > +0: > + andi t2, t0, 0x03 > + li t3, 0x00 > + bne t2, t3,1f > + nop in MIPS assembly code in U-Boot all instructions in the branch delay slots are indented with an extra space character. example: bne t2, t3,1f nop > + li t9, 0x00000000 > + sw t9, 0x0(t8) > + b 2f > + nop > +1: > + li t3, 0x01 > + bne t2, t3,1f > + nop > + li t9, 0x0000ffff > + sw t9, 0x0(t8) > + b 2f > + nop > +1: > + li t3, 0x02 > + bne t2, t3,1f > + nop > + li t9, 0xffff0000 > + sw t9, 0x0(t8) > + b 2f > + nop > +1: > + li t3, 0x03 > + bne t2, t3,2f > + nop > + li t9, 0xffffffff > + sw t9, 0x0(t8) > +2: > + andi t2, t0, 0x0c > + li t3, 0x00 > + bne t2, t3,1f > + nop > + li t9, 0x00000000 > + sw t9, 0x4(t8) > + b 2f > + nop > +1: > + li t3, 0x04 > + bne t2, t3,1f > + nop > + li t9, 0x0000ffff > + sw t9, 0x4(t8) > + b 2f > + nop > +1: > + li t3, 0x08 > + bne t2, t3,1f > + nop > + li t9, 0xffff0000 > + sw t9, 0x4(t8) > + b 2f > + nop > +1: > + li t3, 0x0c > + bne t2, t3,2f > + li t9, 0xffffffff > + sw t9, 0x4(t8) > +2: > + andi t2, t0, 0x30 > + li t3, 0x00 > + bne t2, t3,1f > + nop > + li t9, 0x00000000 > + sw t9, 0x8(t8) > + b 2f > + nop > +1: > + li t3, 0x10 > + bne t2, t3,1f > + nop > + li t9, 0x0000ffff > + sw t9, 0x8(t8) > + b 2f > + nop > +1: > + li t3, 0x20 > + bne t2, t3,1f > + nop > + li t9, 0xffff0000 > + sw t9, 0x8(t8) > + b 2f > + nop > +1: > + li t3, 0x30 > + bne t2, t3,2f > + nop > + li t9, 0xffffffff > + sw t9, 0x8(t8) > +2: > + andi t2, t0, 0xc0 > + li t3, 0x00 > + bne t2, t3,1f > + nop > + li t9, 0x00000000 > + sw t9, 0xc(t8) > + b 2f > + nop > +1: > + li t3, 0x40 > + bne t2, t3,1f > + nop > + li t9, 0x0000ffff > + sw t9, 0xc(t8) > + b 2f > + nop > +1: > + li t3, 0x80 > + bne t2, t3,1f > + nop > + li t9, 0xffff0000 > + sw t9, 0xc(t8) > + b 2f > + nop > +1: > + li t3, 0xc0 > + bne t2, t3,2f > + nop > + li t9, 0xffffffff > + sw t9, 0xc(t8) > +2: > + addiu t0, t0, 0x1 > + addiu t8, t8, 0x10 > + bne t0, t1, 0b > + nop > + > + li a0, DRAM_K1(0x2000) # Start address > + li a1, DRAM_K0(0x2000) # Start address of the pattern 200 > + li a2, DRAM_K0(0x3000) # End Address of the pattern 220 > + li t0, KSEG1ADDR(DDR_TAP_CTRL0) > + lw a3, 0x0(t0) # loading default tap value > + nop > + ori t0, a3, 0x0 > + > + /* $t1=1 indicates increasing tap value, 0 = decreasing */ > + li t1, 0x1 > +0: > + li t7, 0x2 > + li t8, KSEG1ADDR(DDR_TAP_CTRL0) > + sw t0, 0x0(t8) > + nop > + li t8, KSEG1ADDR(DDR_TAP_CTRL1) > + sw t0, 0x0(t8) > + nop > + > + /* t0 stores current tap setting under test > + t1 indicates increment or decrement of tap */ wrongly formatted multi-line comment > +1: > + ori t2, a0, 0x0 > + ori t3, a1, 0x0 > + ori t4, a2, 0x0 > +2: > + lw t5, 0x0(t2) # upper and lower limit detection > + lw t6, 0x0(t3) > + bne t5, t6, 3f > + nop > + addiu t2, t2, 0x4 > + addiu t3, t3, 0x4 > + bne t3, t4, 2b > + nop > + addiu t7, t7, -1 > + bnez t7, 1b > + nop > + > + bnez t1, 2f # increment tap if t1 = 1 > + nop > + bnez t0, 1f # tap=0 works so low limit=0, > + nop # else decrement tap value > + > + li t8, DRAM_K0(0x500000) # assigning lower limit = 0 > + sw t0, 0x0(t8) > + nop > + add t9, t9, t0 # adding lower limit to upper limit > + b 4f # used to calc mid value > + nop > +1: > + addiu t0, t0 , -1 # decrement and loading this new tap > + b 0b > + nop > +2: > + addiu t0, t0, 0x1 > + xori v1, t0, 0x20 # limiting upper limit to 0x20 > + bnez v1, 0b > + nop > + b 1f > + nop > +3: > + bnez t1, 1f # t1=1 fail for upper limit > + nop # t1=0 fail for lower limit > + addiu t0, t0, 0x1 > + nop > + li t8, DRAM_K0(0x500000) # storing lower limit > + sw t0, 0x0(t8) > + nop > + add t9, t9, t0 # adding lower limit and upper limit > + b 4f > + nop > +1: > + addiu t0, t0, -1 > + li t1, 0x0 # changing to decreasing tap mode > + li t8, DRAM_K0(0x500000) # storing upper limit > + sw t0, 0x4(t8) > + nop > + ori t9, t0, 0x0 > + ori t0, a3, 0x0 # loading default tap value > + b 0b > + nop > + > + /* calculating mid value of the tap, storing DQS0, DQS1 in > + 0x80500008, 0x8050000c resp */ wrongly formatted multi-line comment > +4: > + li t7, 0x2 > + div t9, t7 > + nop > + mfhi t6 > + mflo t5 > + add t6, t6, t5 > + li t8, DRAM_K0(0x500000) > + sw t5, 0x8(t8) > + nop > + sw t6, 0xc(t8) > + nop > + li t8, KSEG1ADDR(DDR_TAP_CTRL0) > + sw t5, 0x0(t8) > + nop > + li t8, KSEG1ADDR(DDR_TAP_CTRL1) > + sw t6, 0x0(t8) > + nop > + > + nop > + jr ra > + nop > diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S > new file mode 100644 > index 0000000..57a8b43 > --- /dev/null > +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S > @@ -0,0 +1,534 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <config.h> > +#include <asm/regdef.h> > +#include <asm/mipsregs.h> > +#include <asm/addrspace.h> > +#include <asm/arch/ar71xx_regs.h> > + > +#define BOOT_STRAP (AR71XX_RESET_BASE + AR933X_RESET_REG_BOOTSTRAP) > +#define RST_RESET (AR71XX_RESET_BASE + AR933X_RESET_REG_RESET_MODULE) > +#define PLL_CPU_CONF (AR71XX_PLL_BASE + AR933X_PLL_CPU_CONFIG_REG) > +#define PLL_SEC_CONF (AR71XX_PLL_BASE + AR71XX_PLL_REG_SEC_CONFIG) > +#define PLL_CLK_CTRL (AR71XX_PLL_BASE + AR933X_PLL_CLOCK_CTRL_REG) > +#define PLL_DITH_FRAC (AR71XX_PLL_BASE + AR71XX_PLL_REG_ETH0_INT_CLOCK) > +#define DDR_CONFIG (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_CONFIG) > +#define DDR_CONFIG2 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_CONFIG2) > +#define DDR_MODE (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_MODE) > +#define DDR_EMR (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_EMR) > +#define DDR_CONTROL (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_CONTROL) > +#define DDR_REFRESH (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_REFRESH) > +#define DDR_RD_CYCLE (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_RD_CYCLE) > +#define DDR_TAP_CTRL0 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_TAP_CTRL0) > +#define DDR_TAP_CTRL1 (AR71XX_DDR_CTRL_BASE + AR71XX_DDR_REG_TAP_CTRL1) > +#define DDR_DDR2_CONF (AR71XX_DDR_CTRL_BASE + AR933X_DDR_REG_DDR2_CONFIG) > +#define DDR_EMR2 (AR71XX_DDR_CTRL_BASE + AR933X_DDR_REG_EMR2) > +#define DDR_EMR3 (AR71XX_DDR_CTRL_BASE + AR933X_DDR_REG_EMR3) > +#define DDR_TO_MAX (AR71XX_DDR_CTRL_BASE + AR933X_DDR_REG_TIMEOUT_MAX) > +#define RTC_RESET (AR933X_RTC_BASE + AR933X_RTC_REG_RESET) > +#define RTC_STATUS (AR933X_RTC_BASE + AR933X_RTC_REG_STATUS) > +#define RTC_FORCE_WAKE (AR933X_RTC_BASE + AR933X_RTC_REG_FORCE_WAKE) > +#define DDR_DPLL2 (AR933X_SRIF_BASE + AR933X_SRIF_DDR_DPLL2_REG) > +#define DDR_DPLL3 (AR933X_SRIF_BASE + AR933X_SRIF_DDR_DPLL3_REG) > +#define DDR_DPLL4 (AR933X_SRIF_BASE + AR933X_SRIF_DDR_DPLL4_REG) you can drop all those defines. You only need to load one register with the base address and then use relative offsets in li or sw instructions. Example: li t0, KSEG1ADDR(AR71XX_RESET_BASE) li t1, AR933X_RESET_REG_RESET_MODULE(t0) .. sw t1, AR933X_RESET_REG_RESET_MODULE(t0) or li t0, KSEG1ADDR(AR71XX_PLL_BASE) li t1, PLL_CPU_CONF(t0) li t2, PLL_SEC_CONF(t0) .. sw t1, PLL_CPU_CONF(t0) This is more readable. It is also more efficient because you can drop a lot of instructions which repeatingly load absolute register addresses. Most of the code in this file could be simplified and optimized with this method. > + > +#define SET_BIT(val, bit) ((val) | (1 << (bit))) > +#define SET_PLL_PD(val) SET_BIT(val, 30) > +#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) > +#define PLL_BYPASS(val) SET_BIT(val, 2) > + > +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ > + (((0x3F & divint) << 10) | \ > + ((0x1F & refdiv) << 16) | \ > + ((0x1 & range) << 21) | \ > + ((0x7 & outdiv) << 23) ) > + > +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ > + (((0x3 & (cpudiv - 1)) << 5) | \ > + ((0x3 & (ddrdiv - 1)) << 10) | \ > + ((0x3 & (ahbdiv - 1)) << 15) ) > + > +/* > + * PLL_CPU_CONFIG_VAL > + * > + * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) > + * After PLL configuration we need to clear this bit > + * > + * Values written into CPU PLL Configuration (CPU_PLL_CONFIG) > + * > + * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL) > + * => 32 (0x20) VCOOUT = XTAL * DIV_INT > + * bits 16..20 (5bit) REFDIV (Reference clock divider) > + * => 1 (0x1) [Must start at values 1] > + * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL) > + * => 0 (0x0) [Doesn't impact clock values] > + * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output) > + * => 1 (0x1) [0 is illegal!] > + * PLLOUT = VCOOUT * (1/2^OUTDIV) > + */ > +/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ > +#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) > +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ > +#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1) > + > +/* > + * PLL_CLK_CONTROL_VAL > + * > + * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) > + * After PLL configuration we need to clear this bit > + * > + * Values written into CPU Clock Control Register CLOCK_CONTROL > + * > + * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test. > + * Software must enable the CPU PLL for normal and > + * then set this bit to 0) > + * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) > + * CPU_CLK = PLLOUT / CPU_POST_DIV > + * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) > + * DDR_CLK = PLLOUT / DDR_POST_DIV > + * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) > + * AHB_CLK = PLLOUT / AHB_POST_DIV > + * > + */ > +#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2) > + > + .text > + .set noreorder > + .set mips32 again only set noreorder > + > + .globl lowlevel_init > +lowlevel_init: again use LEAF() and END() > + /* These three WLAN_RESET will avoid original issue */ > + li t3, 0x03 > +1: > + li t0, KSEG1ADDR(RST_RESET) > + lw t1, 0x0(t0) > + ori t1, t1, 0x0800 > + sw t1, 0x0(t0) > + nop > + lw t1, 0x0(t0) > + li t2, 0xfffff7ff > + and t1, t1, t2 > + sw t1, 0x0(t0) > + nop > + addi t3, t3, -1 > + bnez t3, 1b > + nop > + > + li t2, 0x20 > +2: > + beqz t2, 1b > + nop > + addi t2, t2, -1 > + li t0, KSEG1ADDR(BOOT_STRAP) > + lw t5, 0x0(t0) > + andi t1, t5, 0x10 > + bnez t1, 2b > + nop > + > + li t1, 0x02110E > + sw t1, 0x0(t0) > + nop > + > + /* RTC Force Wake */ > + li t0, KSEG1ADDR(RTC_FORCE_WAKE) > + li t1, 0x03 > + sw t1, 0x0(t0) > + nop > + nop > + > + /* RTC Reset */ > + li t0, KSEG1ADDR(RTC_RESET) > + li t1, 0x00 > + sw t1, 0x0(t0) > + nop > + nop > + > + li t0, KSEG1ADDR(RTC_RESET) > + li t1, 0x01 > + sw t1, 0x0(t0) > + nop > + nop > + > + /* Wait for RTC in on state */ > + li t0, KSEG1ADDR(RTC_STATUS) > +1: > + lw t1, 0x0(t0) > + andi t1, t1, 0x02 > + beqz t1, 1b > + nop > + > + /* Program ki/kd */ > + li t0, KSEG1ADDR(DDR_DPLL2) > + andi t1, t5, 0x01 # t5 BOOT_STRAP > + bnez t1, 1f > + nop > + li t1, 0x19e82f01 > + b 2f > + nop > +1: > + li t1, 0x18e82f01 > +2: > + sw t1, 0x0(t0) > + > + /* Program phase shift */ > + li t0, KSEG1ADDR(DDR_DPLL3) > + lw t1, 0x0(t0) > + li t2, 0xc07fffff > + and t1, t1, t2 > + li t2, 0x800000 # meas_at_txon > + or t1, t1, t2 > + sw t1, 0x0(t0) > + nop > + > + /* Max AHB Master wait time out ... */ > + li t0, KSEG1ADDR(DDR_TO_MAX) > + li t1, 0xfffff > + sw t1, 0x0(t0) > + nop > + > + /* in some cases, the SoC doesn't start with higher clock on AHB */ > + li t0, KSEG1ADDR(PLL_CLK_CTRL) > + li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL)) > + sw t1, 0x0(t0) > + nop > + > + /* Set SETTLE_TIME in CPU PLL */ > + li t0, KSEG1ADDR(PLL_SEC_CONF) > + andi t1, t5, 0x01 # t5 BOOT_STRAP > + bnez t1, 1f > + nop > + li t1, 0x0352 > + b 2f > + nop > +1: > + li t1, 0x0550 > +2: > + sw t1, 0x0(t0) > + nop > + > + /* Set nint, frac, refdiv, outdiv, range according to xtal */ > +0: > + li t0, KSEG1ADDR(PLL_CPU_CONF) > + andi t1, t5, 0x01 # t5 BOOT_STRAP > + bnez t1, 1f > + nop > + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M) > + b 2f > + nop > +1: > + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M) > +2: > + sw t1, 0x0(t0) > + nop > +1: > + lw t1, 0x0(t0) > + li t2, 0x80000000 > + and t1, t1, t2 > + bnez t1, 1b > + nop > + > + /* Put frac bit19:10 configuration */ > + li t0, KSEG1ADDR(PLL_DITH_FRAC) > + li t1, 0x1003E8 > + sw t1, 0x0(t0) > + nop > + > + /* Clear PLL power down bit in CPU PLL configuration */ > + li t0, KSEG1ADDR(PLL_CPU_CONF) > + andi t1, t5, 0x01 # t5 BOOT_STRAP > + bnez t1, 1f > + nop > + li t1, PLL_CPU_CONFIG_VAL_25M > + b 2f > + nop > +1: > + li t1, PLL_CPU_CONFIG_VAL_40M > +2: > + sw t1, 0x0(t0) > + nop > + > + /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */ > +1: > + lw t1, 0x0(t0) > + li t2, 0x80000000 > + and t1, t1, t2 > + bnez t1, 1b > + nop > + > + /* Confirm DDR PLL lock */ > + li t3, 100 > + li t4, 0 > + > +2: > + addi t4, t4, 1 > + bgt t4, t3, 0b > + nop > + > + li t3, 5 > +3: > + /* Clear do_meas */ > + li t6, KSEG1ADDR(DDR_DPLL3) > + lw t7, 0x0(t6) > + li t8, 0xBFFFFFFF > + and t7, t7, t8 > + sw t7, 0x0(t6) > + nop > + > + li t9, 10 > +1: > + subu t9, t9, 1 > + bnez t9, 1b > + nop > + > + /* Set do_meas */ > + li t8, 0x40000000 > + or t7, t7, t8 > + sw t7, 0x0(t6) > + nop > + > + /* Check meas_done */ > +1: > + li t6, KSEG1ADDR(DDR_DPLL4) > + lw t7, 0x0(t6) > + andi t7, t7, 0x8 > + beqz t7, 1b > + nop > + > + li t6, KSEG1ADDR(DDR_DPLL3) > + lw t7, 0x0(t6) > + li t8, 0x007FFFF8 > + and t7, t7, t8 > + srl t7, t7, 3 > + li t8, 0x4000 > + bgt t7, t8, 2b > + nop > + addi t3, t3, -1 > + bnez t3, 3b > + nop > + > + /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ > + li t0, KSEG1ADDR(PLL_CLK_CTRL) > + li t1, PLL_CLK_CONTROL_VAL > + sw t1, 0x0(t0) > + nop > + > + li t0, KSEG1ADDR(DDR_CONFIG) > + li t1, 0x7fbc8cd0 > + sw t1, 0x0(t0) > + > + li t0, KSEG1ADDR(DDR_CONFIG2) > + li t1, 0x9dd0e6a8 > + sw t1, 0x0(t0) > + > + andi t1, t5, 0x2000 # t5 BOOT_STRAP > + beqz t1, 3f > + nop > + > + /* Enable DDR2 */ > + li t0, KSEG1ADDR(DDR_DDR2_CONF) > + li t1, 0xA59 > + sw t1, 0x0(t0) > + > + /* Precharge All */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x08 > + sw t1, 0x0(t0) > + > + /* Disable High Temperature Self-Refresh Rate */ > + li t0, KSEG1ADDR(DDR_EMR2) > + li t1, 0x00 > + sw t1, 0x0(t0) > + > + /* Extended Mode Register 2 Set (EMR2S) */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x10 > + sw t1, 0x0(t0) > + > + li t0, KSEG1ADDR(DDR_EMR3) > + li t1, 0x00 > + sw t1, 0x0(t0) > + > + /* Extended Mode Register 3 Set (EMR3S) */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x20 > + sw t1, 0x0(t0) > + > + /* Enable DLL */ > + li t0, KSEG1ADDR(DDR_EMR) > + li t1, 0x00 > + sw t1, 0x0(t0) > + > + /* Extended Mode Register Set (EMRS) */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x02 > + sw t1, 0x0(t0) > + > + /* Reset DLL */ > + li t0, KSEG1ADDR(DDR_MODE) > + li t1, 0x100 > + sw t1, 0x0(t0) > + > + /* Mode Register Set (MRS) */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x01 > + sw t1, 0x0(t0) > + > + /* Precharge All */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x08 > + sw t1, 0x0(t0) > + > + /* Auto Refresh */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x04 > + sw t1, 0x0(t0) > + > + /* Auto Refresh */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x04 > + sw t1, 0x0(t0) > + > + /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */ > + li t0, KSEG1ADDR(DDR_MODE) > + li t1, 0xa33 > + sw t1, 0x0(t0) > + > + /* Mode Register Set (MRS) */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x01 > + sw t1, 0x0(t0) > + > + /* E7,E8,E9 equal to 1(Enable OCD defaults), Enable DLL, > + Reduced Drive Strength */ > + li t0, KSEG1ADDR(DDR_EMR) > + li t1, 0x382 > + sw t1, 0x0(t0) > + > + /* Extended Mode Register Set (EMRS) */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x02 > + sw t1, 0x0(t0) > + > + /* E7,E8,E9 equal to 0(OCD exit), Enable DLL, > + Reduced Drive Strength */ > + li t0, KSEG1ADDR(DDR_EMR) > + li t1, 0x402 > + sw t1, 0x0(t0) > + > + /* Extended Mode Register Set (EMRS) */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x02 > + sw t1, 0x0(t0) > + > + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ > + li t0, KSEG1ADDR(DDR_REFRESH) > + andi t1, t5, 0x01 # t5 BOOT_STRAP > + bnez t1, 1f > + nop > + li t1, 0x4186 > + b 2f > + nop > +1: > + li t1, 0x4270 > +2: > + sw t1, 0x0(t2) > + > + /* DQS 0 Tap Control (needs tuning) */ > + li t0, KSEG1ADDR(DDR_TAP_CTRL0) > + li t1, 0x08 > + sw t1, 0x0(t0) > + > + /* DQS 1 Tap Control (needs tuning) */ > + li t0, KSEG1ADDR(DDR_TAP_CTRL1) > + li t1, 0x09 > + sw t1, 0x0(t0) > + > + /* For 16-bit DDR */ > + li t0, KSEG1ADDR(DDR_RD_CYCLE) > + li t1, 0xff > + sw t1, 0x0(t0) > + > + nop > + b 4f > + nop > + > + /* DDR1 config */ > +3: > + /* Precharge All */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x08 > + sw t1, 0x0(t0) > + > + /* Write Mode Word */ > + li t0, KSEG1ADDR(DDR_MODE) > + li t1, 0x133 > + sw t1, 0x0(t0) > + > + /* Forces an MRS update cycle in DDR */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x01 > + sw t1, 0x0(t0) > + > + /* Enable DLL, High drive strength from DDR */ > + li t0, KSEG1ADDR(DDR_EMR) > + li t1, 0x02 > + sw t1, 0x0(t0) > + > + /* Write Extended Mode Word of DDR */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x02 > + sw t1, 0x0(t0) > + > + /* Precharge All */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x08 > + sw t1, 0x0(t0) > + > + /* DLL out of reset, CAS Latency 3 */ > + li t0, KSEG1ADDR(DDR_MODE) > + li t1, 0x33 > + sw t1, 0x0(t0) > + > + /* Write mode word */ > + li t0, KSEG1ADDR(DDR_CONTROL) > + li t1, 0x01 > + sw t1, 0x0(t0) > + > + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ > + li t0, KSEG1ADDR(DDR_REFRESH) > + andi t1, t5, 0x01 # t5 BOOT_STRAP > + bnez t1, 1f > + nop > + li t1, 0x4270 > + b 2f > + nop > +1: > + li t1, 0x4186 > +2: > + sw t1, 0x0(t0) > + > + /* DQS 0 Tap Control (needs tuning) */ > + li t0, KSEG1ADDR(DDR_TAP_CTRL0) > + li t1, 0x08 > + sw t1, 0x0(t0) > + > + /* DQS 1 Tap Control (needs tuning) */ > + li t0, KSEG1ADDR(DDR_TAP_CTRL1) > + li t1, 0x09 > + sw t1, 0x0(t0) > + > + /* For 16-bit DDR */ > + li t0, KSEG1ADDR(DDR_RD_CYCLE) > + li t1, 0xff > + sw t1, 0x0(t0) > + > +4: > + nop > + jr ra > + nop > diff --git a/arch/mips/mach-ath79/config.mk b/arch/mips/mach-ath79/config.mk > new file mode 100644 > index 0000000..cc76d3b > --- /dev/null > +++ b/arch/mips/mach-ath79/config.mk > @@ -0,0 +1,8 @@ > +# > +# (C) Copyright 2011 > +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +PLATFORM_CPPFLAGS += -mtune=24kc config.mk files are deprecated. Please add following line to arch/mips/config.mk: cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc > diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c > new file mode 100644 > index 0000000..295e11e > --- /dev/null > +++ b/arch/mips/mach-ath79/cpu.c > @@ -0,0 +1,274 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/addrspace.h> > +#include <asm/types.h> > +#include <asm/arch/ath79.h> > +#include <asm/arch/ar71xx_regs.h> > + > +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) > +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) > +#define RST_READ(a) REG_READ(AR71XX_RESET_BASE, a) > +#define RST_WRITE(a, v) REG_WRITE(AR71XX_RESET_BASE, a, v) please put such code in a SoC specific header file like io.h. Also use static inline function instread of macros. In genereal all register accesses should be implemented like this: void __iomem *base = (void __iomem *)KSEG1ADDR(BASE_ADDRESS) u32 data = readl(base + REG_OFFSET) If you only need RST_READ in several locations, you could add a helper function something like this: static inline u32 ath79_rst_readl(u32 offset) { const void __iomem *base = (void __iomem *)KSEG1ADDR(AR71XX_RESET_BASE); return readl(base + offset); } > + > +DECLARE_GLOBAL_DATA_PTR; > + > +enum ath79_soc_type get_soc_type(void) > +{ > + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; > + u32 id, major, minor; > + > + id = RST_READ(AR71XX_RESET_REG_REV_ID); > + major = id & REV_ID_MAJOR_MASK; > + > + switch (major) { > + case REV_ID_MAJOR_AR71XX: > + minor = id & AR71XX_REV_ID_MINOR_MASK; > + switch (minor) { > + case AR71XX_REV_ID_MINOR_AR7130: > + soc = ATH79_SOC_AR7130; > + break; > + > + case AR71XX_REV_ID_MINOR_AR7141: > + soc = ATH79_SOC_AR7141; > + break; > + > + case AR71XX_REV_ID_MINOR_AR7161: > + soc = ATH79_SOC_AR7161; > + break; > + } > + break; > + > + case REV_ID_MAJOR_AR7240: > + soc = ATH79_SOC_AR7240; > + break; > + > + case REV_ID_MAJOR_AR7241: > + soc = ATH79_SOC_AR7241; > + break; > + > + case REV_ID_MAJOR_AR7242: > + soc = ATH79_SOC_AR7242; > + break; > + > + case REV_ID_MAJOR_AR913X: > + minor = id & AR913X_REV_ID_MINOR_MASK; > + switch (minor) { > + case AR913X_REV_ID_MINOR_AR9130: > + soc = ATH79_SOC_AR9130; > + break; > + > + case AR913X_REV_ID_MINOR_AR9132: > + soc = ATH79_SOC_AR9132; > + break; > + } > + break; > + > + case REV_ID_MAJOR_AR9330: > + soc = ATH79_SOC_AR9330; > + break; > + > + case REV_ID_MAJOR_AR9331: > + soc = ATH79_SOC_AR9331; > + break; > + > + case REV_ID_MAJOR_AR9341: > + soc = ATH79_SOC_AR9341; > + break; > + > + case REV_ID_MAJOR_AR9342: > + soc = ATH79_SOC_AR9342; > + break; > + > + case REV_ID_MAJOR_AR9344: > + soc = ATH79_SOC_AR9344; > + break; > + > + case REV_ID_MAJOR_QCA9533_V2: > + /* drop through */ > + > + case REV_ID_MAJOR_QCA9533: > + soc = ATH79_SOC_QCA9533; > + break; > + > + case REV_ID_MAJOR_QCA9556: > + soc = ATH79_SOC_QCA9556; > + break; > + > + case REV_ID_MAJOR_QCA9558: > + soc = ATH79_SOC_QCA9558; > + break; > + > + case REV_ID_MAJOR_TP9343: > + soc = ATH79_SOC_TP9343; > + break; > + > + case REV_ID_MAJOR_QCA9561: > + soc = ATH79_SOC_QCA9561; > + break; > + default: > + break; > + } > + > + return soc; > +} > + > +int print_cpuinfo(void) > +{ > + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; > + char *chip = "????"; > + u32 id, major, minor; > + u32 rev = 0; > + u32 ver = 1; > + > + id = RST_READ(AR71XX_RESET_REG_REV_ID); > + major = id & REV_ID_MAJOR_MASK; > + > + switch (major) { > + case REV_ID_MAJOR_AR71XX: > + minor = id & AR71XX_REV_ID_MINOR_MASK; > + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; > + rev &= AR71XX_REV_ID_REVISION_MASK; > + switch (minor) { > + case AR71XX_REV_ID_MINOR_AR7130: > + soc = ATH79_SOC_AR7130; > + chip = "7130"; > + break; > + > + case AR71XX_REV_ID_MINOR_AR7141: > + soc = ATH79_SOC_AR7141; > + chip = "7141"; > + break; > + > + case AR71XX_REV_ID_MINOR_AR7161: > + soc = ATH79_SOC_AR7161; > + chip = "7161"; > + break; > + } > + break; > + > + case REV_ID_MAJOR_AR7240: > + soc = ATH79_SOC_AR7240; > + chip = "7240"; > + rev = id & AR724X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_AR7241: > + soc = ATH79_SOC_AR7241; > + chip = "7241"; > + rev = id & AR724X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_AR7242: > + soc = ATH79_SOC_AR7242; > + chip = "7242"; > + rev = id & AR724X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_AR913X: > + minor = id & AR913X_REV_ID_MINOR_MASK; > + rev = id >> AR913X_REV_ID_REVISION_SHIFT; > + rev &= AR913X_REV_ID_REVISION_MASK; > + switch (minor) { > + case AR913X_REV_ID_MINOR_AR9130: > + soc = ATH79_SOC_AR9130; > + chip = "9130"; > + break; > + > + case AR913X_REV_ID_MINOR_AR9132: > + soc = ATH79_SOC_AR9132; > + chip = "9132"; > + break; > + } > + break; > + > + case REV_ID_MAJOR_AR9330: > + soc = ATH79_SOC_AR9330; > + chip = "9330"; > + rev = id & AR933X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_AR9331: > + soc = ATH79_SOC_AR9331; > + chip = "9331"; > + rev = id & AR933X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_AR9341: > + soc = ATH79_SOC_AR9341; > + chip = "9341"; > + rev = id & AR934X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_AR9342: > + soc = ATH79_SOC_AR9342; > + chip = "9342"; > + rev = id & AR934X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_AR9344: > + soc = ATH79_SOC_AR9344; > + chip = "9344"; > + rev = id & AR934X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_QCA9533_V2: > + ver = 2; > + /* drop through */ > + > + case REV_ID_MAJOR_QCA9533: > + soc = ATH79_SOC_QCA9533; > + chip = "9533"; > + rev = id & QCA953X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_QCA9556: > + soc = ATH79_SOC_QCA9556; > + chip = "9556"; > + rev = id & QCA955X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_QCA9558: > + soc = ATH79_SOC_QCA9558; > + chip = "9558"; > + rev = id & QCA955X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_TP9343: > + soc = ATH79_SOC_TP9343; > + chip = "9343"; > + rev = id & QCA956X_REV_ID_REVISION_MASK; > + break; > + > + case REV_ID_MAJOR_QCA9561: > + soc = ATH79_SOC_QCA9561; > + chip = "9561"; > + rev = id & QCA956X_REV_ID_REVISION_MASK; > + break; > + } > + > + puts("SoC: "); > + switch (soc) { > + case ATH79_SOC_QCA9533: > + case ATH79_SOC_QCA9556: > + case ATH79_SOC_QCA9558: > + case ATH79_SOC_QCA9561: > + printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip, ver, rev); > + break; > + case ATH79_SOC_TP9343: > + printf("Qualcomm Atheros TP%s rev %u\n", chip, rev); > + break; > + case ATH79_SOC_UNKNOWN: > + printf("ATH79: unknown SoC, id:0x%08x", id); > + default: > + printf("Atheros AR%s rev %u\n", chip, rev); > + } > + > + return 0; > +} > diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c > new file mode 100644 > index 0000000..a9bc945 > --- /dev/null > +++ b/arch/mips/mach-ath79/dram.c > @@ -0,0 +1,27 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/addrspace.h> > + > +extern void ddr_tap_init(void); try to put this in a SoC specific header file > +phys_size_t initdram(int board_type) > +{ > + uint8_t *addr, *p; > + int i; > + > + ddr_tap_init(); > + addr = (uint8_t *)KSEG1; > + *addr = 0x77; > + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { > + p += 0x1000000; > + *p = i; > + if (*addr != 0x77) > + break; > + } > + return (phys_size_t)(p - addr); > +} > diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c > new file mode 100644 > index 0000000..0ace05d > --- /dev/null > +++ b/arch/mips/mach-ath79/reset.c > @@ -0,0 +1,55 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/addrspace.h> > +#include <asm/types.h> > +#include <asm/arch/ath79.h> > +#include <asm/arch/ar71xx_regs.h> > + > +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) > +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) > +#define RST_READ(a) REG_READ(AR71XX_RESET_BASE, a) > +#define RST_WRITE(a, v) REG_WRITE(AR71XX_RESET_BASE, a, v) > + > +DECLARE_GLOBAL_DATA_PTR; > + > +void _machine_restart(void) > +{ > + enum ath79_soc_type soc; > + u32 val, reg = 0; > + > + soc = get_soc_type(); > + if (soc_is_ar71xx(soc)) > + reg = AR71XX_RESET_REG_RESET_MODULE; > + else if (soc_is_ar724x(soc)) > + reg = AR724X_RESET_REG_RESET_MODULE; > + else if (soc_is_ar913x(soc)) > + reg = AR913X_RESET_REG_RESET_MODULE; > + else if (soc_is_ar933x(soc)) > + reg = AR933X_RESET_REG_RESET_MODULE; > + else if (soc_is_ar934x(soc)) > + reg = AR934X_RESET_REG_RESET_MODULE; > + else if (soc_is_qca953x(soc)) > + reg = QCA953X_RESET_REG_RESET_MODULE; > + else if (soc_is_qca955x(soc)) > + reg = QCA955X_RESET_REG_RESET_MODULE; > + else if (soc_is_qca956x(soc)) > + reg = QCA956X_RESET_REG_RESET_MODULE; > + else > + puts("Reset register not defined for this SOC\n"); > + > + if (reg) { > + val = RST_READ(reg); > + val |= AR71XX_RESET_FULL_CHIP; > + RST_WRITE(reg, val); > + } > + > + while (1) > + /* NOP */; > +} > -- - Daniel ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 2/4] mips: ath79: add spi driver [not found] <1450770285-14566-1-git-send-email-wills.wang@live.com> 2015-12-22 7:44 ` [U-Boot] [PATCH v2 1/4] mips: add base support for atheros ath79 based SOCs Wills Wang @ 2015-12-22 7:44 ` Wills Wang 2015-12-22 8:03 ` Jagan Teki 2015-12-22 7:44 ` [U-Boot] [PATCH v2 3/4] mips: ath79: add serial driver for ar933x SOC Wills Wang 2015-12-22 7:44 ` [U-Boot] [PATCH v2 4/4] mips: ath79: add AP121 reference board Wills Wang 3 siblings, 1 reply; 8+ messages in thread From: Wills Wang @ 2015-12-22 7:44 UTC (permalink / raw) To: u-boot Signed-off-by: Wills Wang <wills.wang@live.com> --- drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 142 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 drivers/spi/ath79_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3eca745..7fb2926 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c new file mode 100644 index 0000000..e9a9dd2 --- /dev/null +++ b/drivers/spi/ath79_spi.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ar71xx_regs.h> + +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) +#define REG_WRITE(b, o, v) writel((v), KSEG1ADDR(b + o)) +#define SPI_READ(a) REG_READ(AR71XX_SPI_BASE, a) +#define SPI_WRITE(a, v) REG_WRITE(AR71XX_SPI_BASE, a, v) + +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */ +#define SPI_CLK_DIV(x) ((x >> 1) - 1) + +struct ar71xx_spi_slave { + struct spi_slave slave; + unsigned int mode; +}; + +static inline struct ar71xx_spi_slave *to_ar71xx_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ar71xx_spi_slave, slave); +} + +void spi_init(void) +{ + /* Init SPI Hardware, disable remap, set clock */ + SPI_WRITE(AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); + SPI_WRITE(AR71XX_SPI_REG_CTRL, AR71XX_SPI_CTRL_RD | SPI_CLK_DIV(8)); + SPI_WRITE(AR71XX_SPI_REG_FS, 0); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct ar71xx_spi_slave *ss; + + if (bus || (cs > 2)) + return NULL; + + ss = malloc(sizeof(struct ar71xx_spi_slave)); + if (!ss) + return NULL; + memset(ss, 0, sizeof(struct ar71xx_spi_slave)); + + ss->slave.bus = bus; + ss->slave.cs = cs; + ss->slave.memory_map = (void *)KSEG0ADDR(AR71XX_SPI_BASE); + ss->mode = mode; + + return &ss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct ar71xx_spi_slave *ss = to_ar71xx_spi(slave); + + free(ss); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + uint8_t *rx = din; + const uint8_t *tx = dout; + uint8_t curbyte, curbitlen, restbits; + uint32_t bytes = bitlen / 8; + uint32_t out; + uint32_t in; + + if (flags & SPI_XFER_BEGIN) { + SPI_WRITE(AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); + SPI_WRITE(AR71XX_SPI_REG_IOC, AR71XX_SPI_IOC_CS_ALL); + } + + restbits = (bitlen % 8); + if (restbits) + bytes++; + + /* enable chip select */ + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs)); + while (bytes--) { + curbyte = 0; + if (tx) + curbyte = *tx++; + + if (restbits) { + curbitlen = restbits; + curbyte <<= 8 - restbits; + } else { + curbitlen = 8; + } + + /* clock starts@inactive polarity */ + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) { + if (curbyte & 0x80) + out |= AR71XX_SPI_IOC_DO; + else + out &= ~(AR71XX_SPI_IOC_DO); + + /* setup MSB (to slave) on trailing edge */ + SPI_WRITE(AR71XX_SPI_REG_IOC, out); + SPI_WRITE(AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); + + curbyte <<= 1; + } + + in = SPI_READ(AR71XX_SPI_REG_RDS); + if (rx) { + if (restbits) + *rx++ = (in << (8 - restbits)); + else + *rx++ = in; + } + } + + if (flags & SPI_XFER_END) { + SPI_WRITE(AR71XX_SPI_REG_IOC, AR71XX_SPI_IOC_CS(slave->cs)); + SPI_WRITE(AR71XX_SPI_REG_IOC, AR71XX_SPI_IOC_CS_ALL); + SPI_WRITE(AR71XX_SPI_REG_FS, 0); + } + + return 0; +} -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 2/4] mips: ath79: add spi driver 2015-12-22 7:44 ` [U-Boot] [PATCH v2 2/4] mips: ath79: add spi driver Wills Wang @ 2015-12-22 8:03 ` Jagan Teki 0 siblings, 0 replies; 8+ messages in thread From: Jagan Teki @ 2015-12-22 8:03 UTC (permalink / raw) To: u-boot On 22 December 2015 at 13:14, Wills Wang <wills.wang@live.com> wrote: > Signed-off-by: Wills Wang <wills.wang@live.com> > --- > > drivers/spi/Makefile | 1 + > drivers/spi/ath79_spi.c | 142 ++++++++++++++++++++++++++++++++++++++++++++++++ Please write it on driver-model, we're accepting new drivers will be in driver-model format. > 2 files changed, 143 insertions(+) > create mode 100644 drivers/spi/ath79_spi.c > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 3eca745..7fb2926 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -17,6 +17,7 @@ endif > > obj-$(CONFIG_ALTERA_SPI) += altera_spi.o > obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o > +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o > obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o > obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o > obj-$(CONFIG_BFIN_SPI) += bfin_spi.o > diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c > new file mode 100644 > index 0000000..e9a9dd2 > --- /dev/null > +++ b/drivers/spi/ath79_spi.c > @@ -0,0 +1,142 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <malloc.h> > +#include <spi.h> > +#include <asm/io.h> > +#include <asm/addrspace.h> > +#include <asm/types.h> > +#include <asm/arch/ar71xx_regs.h> > + > +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) > +#define REG_WRITE(b, o, v) writel((v), KSEG1ADDR(b + o)) > +#define SPI_READ(a) REG_READ(AR71XX_SPI_BASE, a) > +#define SPI_WRITE(a, v) REG_WRITE(AR71XX_SPI_BASE, a, v) > + > +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */ > +#define SPI_CLK_DIV(x) ((x >> 1) - 1) > + > +struct ar71xx_spi_slave { > + struct spi_slave slave; > + unsigned int mode; > +}; > + > +static inline struct ar71xx_spi_slave *to_ar71xx_spi(struct spi_slave *slave) > +{ > + return container_of(slave, struct ar71xx_spi_slave, slave); > +} > + > +void spi_init(void) > +{ > + /* Init SPI Hardware, disable remap, set clock */ > + SPI_WRITE(AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); > + SPI_WRITE(AR71XX_SPI_REG_CTRL, AR71XX_SPI_CTRL_RD | SPI_CLK_DIV(8)); > + SPI_WRITE(AR71XX_SPI_REG_FS, 0); > +} > + > +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, > + unsigned int max_hz, unsigned int mode) > +{ > + struct ar71xx_spi_slave *ss; > + > + if (bus || (cs > 2)) > + return NULL; > + > + ss = malloc(sizeof(struct ar71xx_spi_slave)); > + if (!ss) > + return NULL; > + memset(ss, 0, sizeof(struct ar71xx_spi_slave)); > + > + ss->slave.bus = bus; > + ss->slave.cs = cs; > + ss->slave.memory_map = (void *)KSEG0ADDR(AR71XX_SPI_BASE); > + ss->mode = mode; > + > + return &ss->slave; > +} > + > +void spi_free_slave(struct spi_slave *slave) > +{ > + struct ar71xx_spi_slave *ss = to_ar71xx_spi(slave); > + > + free(ss); > +} > + > +int spi_claim_bus(struct spi_slave *slave) > +{ > + return 0; > +} > + > +void spi_release_bus(struct spi_slave *slave) > +{ > +} > + > +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, > + void *din, unsigned long flags) > +{ > + uint8_t *rx = din; > + const uint8_t *tx = dout; > + uint8_t curbyte, curbitlen, restbits; > + uint32_t bytes = bitlen / 8; > + uint32_t out; > + uint32_t in; > + > + if (flags & SPI_XFER_BEGIN) { > + SPI_WRITE(AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); > + SPI_WRITE(AR71XX_SPI_REG_IOC, AR71XX_SPI_IOC_CS_ALL); > + } > + > + restbits = (bitlen % 8); > + if (restbits) > + bytes++; > + > + /* enable chip select */ > + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs)); > + while (bytes--) { > + curbyte = 0; > + if (tx) > + curbyte = *tx++; > + > + if (restbits) { > + curbitlen = restbits; > + curbyte <<= 8 - restbits; > + } else { > + curbitlen = 8; > + } > + > + /* clock starts at inactive polarity */ > + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) { > + if (curbyte & 0x80) > + out |= AR71XX_SPI_IOC_DO; > + else > + out &= ~(AR71XX_SPI_IOC_DO); > + > + /* setup MSB (to slave) on trailing edge */ > + SPI_WRITE(AR71XX_SPI_REG_IOC, out); > + SPI_WRITE(AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); > + > + curbyte <<= 1; > + } > + > + in = SPI_READ(AR71XX_SPI_REG_RDS); > + if (rx) { > + if (restbits) > + *rx++ = (in << (8 - restbits)); > + else > + *rx++ = in; > + } > + } > + > + if (flags & SPI_XFER_END) { > + SPI_WRITE(AR71XX_SPI_REG_IOC, AR71XX_SPI_IOC_CS(slave->cs)); > + SPI_WRITE(AR71XX_SPI_REG_IOC, AR71XX_SPI_IOC_CS_ALL); > + SPI_WRITE(AR71XX_SPI_REG_FS, 0); > + } > + > + return 0; > +} > -- > 1.9.1 > > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot -- Jagan. ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 3/4] mips: ath79: add serial driver for ar933x SOC [not found] <1450770285-14566-1-git-send-email-wills.wang@live.com> 2015-12-22 7:44 ` [U-Boot] [PATCH v2 1/4] mips: add base support for atheros ath79 based SOCs Wills Wang 2015-12-22 7:44 ` [U-Boot] [PATCH v2 2/4] mips: ath79: add spi driver Wills Wang @ 2015-12-22 7:44 ` Wills Wang 2015-12-22 13:03 ` Thomas Chou 2015-12-22 14:54 ` Marek Vasut 2015-12-22 7:44 ` [U-Boot] [PATCH v2 4/4] mips: ath79: add AP121 reference board Wills Wang 3 siblings, 2 replies; 8+ messages in thread From: Wills Wang @ 2015-12-22 7:44 UTC (permalink / raw) To: u-boot Signed-off-by: Wills Wang <wills.wang@live.com> --- drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 337 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 338 insertions(+) create mode 100644 drivers/serial/serial_ar933x.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..9a7ad89 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.o diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c new file mode 100644 index 0000000..6ea500a --- /dev/null +++ b/drivers/serial/serial_ar933x.c @@ -0,0 +1,337 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <config.h> +#include <serial.h> +#include <asm/arch/ar71xx_regs.h> +#include <asm/arch/ar933x_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) +#define UART_READ(a) REG_READ(AR933X_UART_BASE, a) +#define UART_WRITE(a, v) REG_WRITE(AR933X_UART_BASE, a, v) + +static void ar933x_serial_get_scale_step(u32 *uart_scale, u32 *uart_step) +{ + u32 val; + + val = REG_READ(AR71XX_RESET_BASE, AR933X_RESET_REG_BOOTSTRAP); + if (val & AR933X_BOOTSTRAP_REF_CLK_40) { + switch (gd->baudrate) { + case 600: + *uart_scale = 255; + *uart_step = 503; + break; + case 1200: + *uart_scale = 249; + *uart_step = 983; + break; + case 2400: + *uart_scale = 167; + *uart_step = 1321; + break; + case 4800: + *uart_scale = 87; + *uart_step = 1384; + break; + case 9600: + *uart_scale = 45; + *uart_step = 1447; + break; + case 14400: + *uart_scale = 53; + *uart_step = 2548; + break; + case 19200: + *uart_scale = 22; + *uart_step = 1447; + break; + case 28800: + *uart_scale = 26; + *uart_step = 2548; + break; + case 38400: + *uart_scale = 28; + *uart_step = 3649; + break; + case 56000: + *uart_scale = 7; + *uart_step = 1468; + break; + case 57600: + *uart_scale = 34; + *uart_step = 6606; + break; + case 115200: + *uart_scale = 28; + *uart_step = 10947; + break; + case 128000: + *uart_scale = 6; + *uart_step = 2936; + break; + case 153600: + *uart_scale = 18; + *uart_step = 9563; + break; + case 230400: + *uart_scale = 16; + *uart_step = 12834; + break; + case 250000: + *uart_scale = 4; + *uart_step = 4096; + break; + case 256000: + *uart_scale = 6; + *uart_step = 5872; + break; + case 460800: + *uart_scale = 7; + *uart_step = 12079; + break; + case 576000: + *uart_scale = 4; + *uart_step = 9437; + break; + case 921600: + *uart_scale = 3; + *uart_step = 12079; + break; + case 1000000: + *uart_scale = 2; + *uart_step = 9830; + break; + case 1152000: + *uart_scale = 2; + *uart_step = 11324; + break; + case 1500000: + *uart_scale = 0; + *uart_step = 4915; + break; + case 2000000: + *uart_scale = 0; + *uart_step = 6553; + break; + default: + *uart_scale = (40000000 / (16 * gd->baudrate)) - 1; + *uart_step = 8192; + } + } else { + switch (gd->baudrate) { + case 600: + *uart_scale = 255; + *uart_step = 805; + break; + case 1200: + *uart_scale = 209; + *uart_step = 1321; + break; + case 2400: + *uart_scale = 104; + *uart_step = 1321; + break; + case 4800: + *uart_scale = 54; + *uart_step = 1384; + break; + case 9600: + *uart_scale = 78; + *uart_step = 3976; + break; + case 14400: + *uart_scale = 98; + *uart_step = 7474; + break; + case 19200: + *uart_scale = 55; + *uart_step = 5637; + break; + case 28800: + *uart_scale = 77; + *uart_step = 11777; + break; + case 38400: + *uart_scale = 36; + *uart_step = 7449; + break; + case 56000: + *uart_scale = 4; + *uart_step = 1468; + break; + case 57600: + *uart_scale = 35; + *uart_step = 10871; + break; + case 115200: + *uart_scale = 20; + *uart_step = 12683; + break; + case 128000: + *uart_scale = 11; + *uart_step = 8053; + break; + case 153600: + *uart_scale = 9; + *uart_step = 8053; + break; + case 230400: + *uart_scale = 9; + *uart_step = 12079; + break; + case 250000: + *uart_scale = 6; + *uart_step = 9175; + break; + case 256000: + *uart_scale = 5; + *uart_step = 8053; + break; + case 460800: + *uart_scale = 4; + *uart_step = 12079; + break; + case 576000: + *uart_scale = 3; + *uart_step = 12079; + break; + case 921600: + *uart_scale = 1; + *uart_step = 9663; + break; + case 1000000: + *uart_scale = 1; + *uart_step = 10485; + break; + case 1152000: + *uart_scale = 1; + *uart_step = 12079; + break; + case 1500000: + *uart_scale = 0; + *uart_step = 7864; + break; + case 2000000: + *uart_scale = 0; + *uart_step = 10485; + break; + default: + *uart_scale = (25000000 / (16 * gd->baudrate)) - 1; + *uart_step = 8192; + } + } +} + +static void ar933x_serial_setbrg(void) +{ + /* TODO: better clock calculation, baudrate, etc. */ + u32 val, scale, step; + + ar933x_serial_get_scale_step(&scale, &step); + val = ((scale & AR933X_UART_CLOCK_SCALE_M) + << AR933X_UART_CLOCK_SCALE_S); + val |= ((step & AR933X_UART_CLOCK_STEP_M) + << AR933X_UART_CLOCK_STEP_S); + UART_WRITE(AR933X_UART_CLOCK_REG, val); +} + +int ar933x_serial_init(void) +{ + u32 val; + + /* + * Set GPIO10 (UART_SO) as output and enable UART, + * BIT(15) in GPIO_FUNCTION_1 register must be written with 1 + */ + val = REG_READ(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE); + val |= BIT(10); + REG_WRITE(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val); + + val = REG_READ(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC); + val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15)); + REG_WRITE(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val); + + /* + * UART controller configuration: + * - no DMA + * - no interrupt + * - DCE mode + * - no flow control + * - set RX ready oride + * - set TX ready oride + */ + val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE + | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S); + UART_WRITE(AR933X_UART_CS_REG, val); + ar933x_serial_setbrg(); + + return 0; +} + +void ar933x_serial_putc(const char c) +{ + u32 data; + + if (c == '\n') + ar933x_serial_putc('\r'); + + do { + data = UART_READ(AR933X_UART_DATA_REG); + } while (!(data & AR933X_UART_DATA_TX_CSR)); + + data = (u32)c | AR933X_UART_DATA_TX_CSR; + UART_WRITE(AR933X_UART_DATA_REG, data); +} + +static int ar933x_serial_getc(void) +{ + u32 data; + + do { + data = UART_READ(AR933X_UART_DATA_REG); + } while (!(data & AR933X_UART_DATA_RX_CSR)); + + data = UART_READ(AR933X_UART_DATA_REG); + UART_WRITE(AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR); + return (int)(data & AR933X_UART_DATA_TX_RX_MASK); +} + +static int ar933x_serial_tstc(void) +{ + u32 data; + + data = UART_READ(AR933X_UART_DATA_REG); + return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0; +} + +static struct serial_device ar933x_serial_drv = { + .name = "ar933x_serial", + .start = ar933x_serial_init, + .stop = NULL, + .setbrg = ar933x_serial_setbrg, + .putc = ar933x_serial_putc, + .puts = default_serial_puts, + .getc = ar933x_serial_getc, + .tstc = ar933x_serial_tstc, +}; + +void ar933x_serial_initialize(void) +{ + serial_register(&ar933x_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &ar933x_serial_drv; +} -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 3/4] mips: ath79: add serial driver for ar933x SOC 2015-12-22 7:44 ` [U-Boot] [PATCH v2 3/4] mips: ath79: add serial driver for ar933x SOC Wills Wang @ 2015-12-22 13:03 ` Thomas Chou 2015-12-22 14:54 ` Marek Vasut 1 sibling, 0 replies; 8+ messages in thread From: Thomas Chou @ 2015-12-22 13:03 UTC (permalink / raw) To: u-boot Hi Wills, On 2015?12?22? 15:44, Wills Wang wrote: > Signed-off-by: Wills Wang <wills.wang@live.com> > --- > > drivers/serial/Makefile | 1 + > drivers/serial/serial_ar933x.c | 337 +++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 338 insertions(+) > create mode 100644 drivers/serial/serial_ar933x.c > Please convert the serial driver to driver model. Please check u-boot/doc/driver-model/serial-howto.txt. Best regards, Thomas ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 3/4] mips: ath79: add serial driver for ar933x SOC 2015-12-22 7:44 ` [U-Boot] [PATCH v2 3/4] mips: ath79: add serial driver for ar933x SOC Wills Wang 2015-12-22 13:03 ` Thomas Chou @ 2015-12-22 14:54 ` Marek Vasut 1 sibling, 0 replies; 8+ messages in thread From: Marek Vasut @ 2015-12-22 14:54 UTC (permalink / raw) To: u-boot On Tuesday, December 22, 2015 at 08:44:44 AM, Wills Wang wrote: > Signed-off-by: Wills Wang <wills.wang@live.com> > --- > > drivers/serial/Makefile | 1 + > drivers/serial/serial_ar933x.c | 337 > +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 338 > insertions(+) > create mode 100644 drivers/serial/serial_ar933x.c > > diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile > index dd87147..9a7ad89 100644 > --- a/drivers/serial/Makefile > +++ b/drivers/serial/Makefile > @@ -17,6 +17,7 @@ endif > > obj-$(CONFIG_ALTERA_UART) += altera_uart.o > obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o > +obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o > obj-$(CONFIG_ARM_DCC) += arm_dcc.o > obj-$(CONFIG_ATMEL_USART) += atmel_usart.o > obj-$(CONFIG_EFI_APP) += serial_efi.o > diff --git a/drivers/serial/serial_ar933x.c > b/drivers/serial/serial_ar933x.c new file mode 100644 > index 0000000..6ea500a > --- /dev/null > +++ b/drivers/serial/serial_ar933x.c > @@ -0,0 +1,337 @@ > +/* > + * (C) Copyright 2015 > + * Wills Wang, <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/addrspace.h> > +#include <asm/types.h> > +#include <config.h> > +#include <serial.h> > +#include <asm/arch/ar71xx_regs.h> > +#include <asm/arch/ar933x_uart.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) > +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) > +#define UART_READ(a) REG_READ(AR933X_UART_BASE, a) > +#define UART_WRITE(a, v) REG_WRITE(AR933X_UART_BASE, a, v) Please remove these macros (see below) > +static void ar933x_serial_get_scale_step(u32 *uart_scale, u32 *uart_step) > +{ > + u32 val; > + > + val = REG_READ(AR71XX_RESET_BASE, AR933X_RESET_REG_BOOTSTRAP); > + if (val & AR933X_BOOTSTRAP_REF_CLK_40) { > + switch (gd->baudrate) { > + case 600: > + *uart_scale = 255; > + *uart_step = 503; > + break; > + case 1200: > + *uart_scale = 249; > + *uart_step = 983; I suppose this cannot be calculated, right ? What about making this into a table, something like: struct { u16 baudrate; u16 scale; u16 step; } uart_something[] { { 600, 255, 503 }, { 1200, .... }, .... }; and then look things up: for (i = 0; i < ARRAY_SIZE(uart_something); i++) if (gd->baudrate == uart_something[i].baudrate) break; if (i == ARRAY_SIZE(uart_something)) do default handling here [...] > + default: > + *uart_scale = (40000000 / (16 * gd->baudrate)) - 1; > + *uart_step = 8192; > + } > + } else { > + switch (gd->baudrate) { > + case 600: > + *uart_scale = 255; > + *uart_step = 805; > + break; You can wrap this part into the table as well then, quite easily. [...] > +static void ar933x_serial_setbrg(void) > +{ > + /* TODO: better clock calculation, baudrate, etc. */ > + u32 val, scale, step; > + > + ar933x_serial_get_scale_step(&scale, &step); > + val = ((scale & AR933X_UART_CLOCK_SCALE_M) > + << AR933X_UART_CLOCK_SCALE_S); > + val |= ((step & AR933X_UART_CLOCK_STEP_M) > + << AR933X_UART_CLOCK_STEP_S); Drop the extraneous parenthesis around the statement please. > + UART_WRITE(AR933X_UART_CLOCK_REG, val); This should be just writel(). > +} > + > +int ar933x_serial_init(void) > +{ > + u32 val; > + > + /* > + * Set GPIO10 (UART_SO) as output and enable UART, > + * BIT(15) in GPIO_FUNCTION_1 register must be written with 1 > + */ > + val = REG_READ(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE); > + val |= BIT(10); > + REG_WRITE(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val); Use setbits_le32() > + val = REG_READ(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC); > + val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15)); > + REG_WRITE(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val); Same here. > + /* > + * UART controller configuration: > + * - no DMA > + * - no interrupt > + * - DCE mode > + * - no flow control > + * - set RX ready oride > + * - set TX ready oride > + */ > + val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE > + | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S); > + UART_WRITE(AR933X_UART_CS_REG, val); > + ar933x_serial_setbrg(); > + > + return 0; > +} > + > +void ar933x_serial_putc(const char c) > +{ > + u32 data; > + > + if (c == '\n') > + ar933x_serial_putc('\r'); > + > + do { > + data = UART_READ(AR933X_UART_DATA_REG); > + } while (!(data & AR933X_UART_DATA_TX_CSR)); > + > + data = (u32)c | AR933X_UART_DATA_TX_CSR; $c is already u32, no need for the cast. > + UART_WRITE(AR933X_UART_DATA_REG, data); > +} > + > +static int ar933x_serial_getc(void) > +{ > + u32 data; > + > + do { > + data = UART_READ(AR933X_UART_DATA_REG); > + } while (!(data & AR933X_UART_DATA_RX_CSR)); > + > + data = UART_READ(AR933X_UART_DATA_REG); > + UART_WRITE(AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR); > + return (int)(data & AR933X_UART_DATA_TX_RX_MASK); Please drop all the casts, they are useless. > +} > + > +static int ar933x_serial_tstc(void) > +{ > + u32 data; > + > + data = UART_READ(AR933X_UART_DATA_REG); > + return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0; > +} > + > +static struct serial_device ar933x_serial_drv = { > + .name = "ar933x_serial", > + .start = ar933x_serial_init, > + .stop = NULL, > + .setbrg = ar933x_serial_setbrg, > + .putc = ar933x_serial_putc, > + .puts = default_serial_puts, > + .getc = ar933x_serial_getc, > + .tstc = ar933x_serial_tstc, > +}; > + > +void ar933x_serial_initialize(void) > +{ > + serial_register(&ar933x_serial_drv); > +} > + > +__weak struct serial_device *default_serial_console(void) > +{ > + return &ar933x_serial_drv; > +} ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 4/4] mips: ath79: add AP121 reference board [not found] <1450770285-14566-1-git-send-email-wills.wang@live.com> ` (2 preceding siblings ...) 2015-12-22 7:44 ` [U-Boot] [PATCH v2 3/4] mips: ath79: add serial driver for ar933x SOC Wills Wang @ 2015-12-22 7:44 ` Wills Wang 3 siblings, 0 replies; 8+ messages in thread From: Wills Wang @ 2015-12-22 7:44 UTC (permalink / raw) To: u-boot Signed-off-by: Wills Wang <wills.wang@live.com> --- arch/mips/Kconfig | 8 ++++ board/ath79/ap121/Kconfig | 15 +++++++ board/ath79/ap121/MAINTAINERS | 6 +++ board/ath79/ap121/Makefile | 8 ++++ board/ath79/ap121/README | 18 ++++++++ board/ath79/ap121/ap121.c | 18 ++++++++ board/ath79/ap121/config.mk | 16 +++++++ configs/ap121_defconfig | 18 ++++++++ include/configs/ap121.h | 98 +++++++++++++++++++++++++++++++++++++++++++ 9 files changed, 205 insertions(+) create mode 100644 board/ath79/ap121/Kconfig create mode 100644 board/ath79/ap121/MAINTAINERS create mode 100644 board/ath79/ap121/Makefile create mode 100644 board/ath79/ap121/README create mode 100644 board/ath79/ap121/ap121.c create mode 100644 board/ath79/ap121/config.mk create mode 100644 configs/ap121_defconfig create mode 100644 include/configs/ap121.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7f7e258..09b8709 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -51,6 +51,13 @@ config TARGET_PB1X00 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD +config TARGET_AP121 + bool "Support ap121" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + endchoice @@ -59,6 +66,7 @@ source "board/imgtec/malta/Kconfig" source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" +source "board/ath79/ap121/Kconfig" if MIPS diff --git a/board/ath79/ap121/Kconfig b/board/ath79/ap121/Kconfig new file mode 100644 index 0000000..88d9eff --- /dev/null +++ b/board/ath79/ap121/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AP121 + +config SYS_BOARD + default "ap121" + +config SYS_VENDOR + default "ath79" + +config SYS_SOC + default "ath79" + +config SYS_CONFIG_NAME + default "ap121" + +endif diff --git a/board/ath79/ap121/MAINTAINERS b/board/ath79/ap121/MAINTAINERS new file mode 100644 index 0000000..319b521 --- /dev/null +++ b/board/ath79/ap121/MAINTAINERS @@ -0,0 +1,6 @@ +AP121 BOARD +M: Wills Wang <wills.wang@live.com> +S: Maintained +F: board/ath79/ap121/ +F: include/configs/ap121.h +F: configs/ap121_defconfig diff --git a/board/ath79/ap121/Makefile b/board/ath79/ap121/Makefile new file mode 100644 index 0000000..9132118 --- /dev/null +++ b/board/ath79/ap121/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap121.o diff --git a/board/ath79/ap121/README b/board/ath79/ap121/README new file mode 100644 index 0000000..104850f --- /dev/null +++ b/board/ath79/ap121/README @@ -0,0 +1,18 @@ +ATHEROS AP121 +================== + +Supported hardware: AP121 referance board. + +Files of the AP121 port +-------------------------- + +arch/mips/mach-ath79/ar933x/ - The CPU support code for the Atheros ar933x +arch/mips/include/asm/arch-ath79 - Header files for the Atheros ath79 +board/ath79/ap121/ - AP121 board specific files +include/configs/ap121.h - AP121 configuration file + +Configure +------------------- + +To configure for the current board + make ap121_defconfig diff --git a/board/ath79/ap121/ap121.c b/board/ath79/ap121/ap121.c new file mode 100644 index 0000000..3a3d782 --- /dev/null +++ b/board/ath79/ap121/ap121.c @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/io.h> + +int checkboard(void) +{ + puts("Board: AP121\n"); + return 0; +} diff --git a/board/ath79/ap121/config.mk b/board/ath79/ap121/config.mk new file mode 100644 index 0000000..f7dd3b7 --- /dev/null +++ b/board/ath79/ap121/config.mk @@ -0,0 +1,16 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# +# AP121 referance board, MIPS32 core +# + +# ROM version +CONFIG_SYS_TEXT_BASE = 0x9f000000 + +# RAM version +#CONFIG_SYS_TEXT_BASE = 0x80010000 diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig new file mode 100644 index 0000000..04a8ecb --- /dev/null +++ b/configs/ap121_defconfig @@ -0,0 +1,18 @@ +CONFIG_MIPS=y +CONFIG_TARGET_AP121=y +CONFIG_SYS_PROMPT="ap121 # " +# CONFIG_NET is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_NET is not set +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/ap121.h b/include/configs/ap121.h new file mode 100644 index 0000000..c9715c2 --- /dev/null +++ b/include/configs/ap121.h @@ -0,0 +1,98 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/kconfig.h> +#include <linux/sizes.h> + +#define CONFIG_SOC_ATH79 +#define CONFIG_SOC_AR933X + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 200 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32 * SZ_1K +#define CONFIG_SYS_ICACHE_SIZE 64 * SZ_1K +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN ROUND(0x30000 + 128 * SZ_1K, 0x1000) + +#define CONFIG_SYS_BOOTPARAMS_LEN 128 * SZ_1K + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x20000 +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (240 * SZ_1K) +#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) +#define CONFIG_ENV_SIZE (16 * SZ_1K) + +#define CONFIG_AR933X_SERIAL +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 600, 1200, 2400, 4800, 9600, 14400, \ + 19200, 28800, 38400, 56000, 57600, 115200, \ + 128000, 153600, 230400, 250000, 256000, 460800, \ + 576000, 921600, 1000000, 1152000, 1500000, 2000000 } + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" +#define CONFIG_BOOTCOMMAND "sf probe;mtdparts default;bootm 0x9f300000" +#define CONFIG_LZMA + +/* Commands */ +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF + +/* SPI */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_ATH79_SPI +#endif +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_USE_4K_SECTORS +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SPI_FLASH_EON +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SPI_FLASH_ISSI +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_MTD +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=spi-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ + "256k(u-boot),64k(u-boot-env),2752k(rootfs),896k(uImage),64k(NVRAM),64k(ART)" +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 +#define CONFIG_CMD_MEMTEST + +#endif /* __CONFIG_H */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-12-22 14:54 UTC | newest]
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[not found] <1450770285-14566-1-git-send-email-wills.wang@live.com>
2015-12-22 7:44 ` [U-Boot] [PATCH v2 1/4] mips: add base support for atheros ath79 based SOCs Wills Wang
2015-12-22 14:34 ` Daniel Schwierzeck
2015-12-22 7:44 ` [U-Boot] [PATCH v2 2/4] mips: ath79: add spi driver Wills Wang
2015-12-22 8:03 ` Jagan Teki
2015-12-22 7:44 ` [U-Boot] [PATCH v2 3/4] mips: ath79: add serial driver for ar933x SOC Wills Wang
2015-12-22 13:03 ` Thomas Chou
2015-12-22 14:54 ` Marek Vasut
2015-12-22 7:44 ` [U-Boot] [PATCH v2 4/4] mips: ath79: add AP121 reference board Wills Wang
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