From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
"Nakajima, Jun" <jun.nakajima@intel.com>,
"keir@xen.org" <keir@xen.org>,
"jbeulich@suse.com" <jbeulich@suse.com>,
"andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>
Cc: "dietmar.hahn@ts.fujitsu.com" <dietmar.hahn@ts.fujitsu.com>,
"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
Subject: Re: [PATCH] x86/VPMU: Check more carefully which bits are allowed to be written to MSRs
Date: Wed, 23 Dec 2015 10:03:56 -0500 [thread overview]
Message-ID: <567AB7DC.80708@oracle.com> (raw)
In-Reply-To: <AADFC41AFE54684AB9EE6CBC0274A5D15F753FCB@SHSMSX101.ccr.corp.intel.com>
On 12/23/2015 12:21 AM, Tian, Kevin wrote:
>> From: Boris Ostrovsky [mailto:boris.ostrovsky@oracle.com]
>> Sent: Wednesday, December 23, 2015 12:25 AM
>>
>> Current Intel VPMU emulation needs to perform more checks when writing
>> PMU MSRs on guest's behalf:
>> * MSR_CORE_PERF_GLOBAL_CTRL is not checked at all
>> * MSR_CORE_PERF_FIXED_CTR_CTRL has more reserved bits in PMU version 2
>> * MSR_CORE_PERF_GLOBAL_OVF_CTRL's bit 61 is allowed on versions greater
>> * than 2.
>>
>> We can also use precomputed mask in core2_vpmu_do_interrupt().
>>
>> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
> Acked-by: Kevin Tian <kevin.tian@intel.com>
I think I missed one more register. Let me send another version.
-boris
prev parent reply other threads:[~2015-12-23 15:03 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-22 16:24 [PATCH] x86/VPMU: Check more carefully which bits are allowed to be written to MSRs Boris Ostrovsky
2015-12-23 5:21 ` Tian, Kevin
2015-12-23 15:03 ` Boris Ostrovsky [this message]
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