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From: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: <tony.luck@intel.com>, <tglx@linutronix.de>, <mingo@redhat.com>,
	<hpa@zytor.com>, <x86@kernel.org>, <linux-edac@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per bank
Date: Thu, 14 Jan 2016 16:48:22 -0600	[thread overview]
Message-ID: <569825B6.6020507@amd.com> (raw)
In-Reply-To: <20160114223739.GJ19941@pd.tnic>

On 1/14/2016 4:37 PM, Borislav Petkov wrote:
> On Thu, Jan 14, 2016 at 04:05:38PM -0600, Aravind Gopalakrishnan wrote:
>>   
>> -#define NR_BLOCKS         9
>> +#define NR_BLOCKS         5
> This doesn't look necessary to me. We do check MCi_MISC[BlkPtr] before
> accessing that MSR.
>

True. But that BlkPtr logic also will undergo changes as it's 
interpretation for future processors is different.

We are guaranteed to have all the MISC registers (all 5 of them) going 
forward.
But we shouldn't be accessing MSRs beyond the 5th extended MISC register 
for each bank as that is the architectural boundary.
Hence the change here.

Thanks,
-Aravind.

  reply	other threads:[~2016-01-14 22:48 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-14 22:05 [PATCH 0/5] Updates to AMD MCE driver per Scalable MCA spec Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 1/5] x86, mce: Fix order of AMD MCE init function call Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 2/5] x86/mcheck/AMD: Do not perform shared bank check for future processors Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per bank Aravind Gopalakrishnan
2016-01-14 22:37   ` Borislav Petkov
2016-01-14 22:48     ` Aravind Gopalakrishnan [this message]
2016-01-14 22:53       ` Borislav Petkov
2016-01-14 23:08         ` Aravind Gopalakrishnan
2016-01-15 11:14           ` Borislav Petkov
2016-01-15 15:35             ` Gopalakrishnan, Aravind
2016-01-15 16:29             ` Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 4/5] x86/mcheck/AMD: Fix LVT offset configuration for thresholding Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 5/5] x86/mcheck/AMD: Set MCAX Enable bit Aravind Gopalakrishnan
2016-01-14 22:46   ` Borislav Petkov
2016-01-14 22:53     ` Aravind Gopalakrishnan
2016-01-14 22:58       ` Borislav Petkov
2016-01-14 23:13         ` Aravind Gopalakrishnan

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