From: Nick Hoath <nicholas.hoath@intel.com>
To: Arun Siluvery <arun.siluvery@linux.intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Kuoppala, Mika" <mika.kuoppala@intel.com>
Subject: Re: [PATCH 2/8] drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelist
Date: Thu, 21 Jan 2016 11:49:01 +0000 [thread overview]
Message-ID: <56A0C5AD.2080107@intel.com> (raw)
In-Reply-To: <1452679593-3922-3-git-send-email-arun.siluvery@linux.intel.com>
On 13/01/2016 10:06, Arun Siluvery wrote:
> Required for WaEnablePreemptionGranularityControlByUMD:skl,bxt
>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6668bb0..1067ff0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5998,6 +5998,8 @@ enum skl_disp_power_wells {
> #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
> #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
>
> +#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
> +
> /* GEN7 chicken */
> #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
> # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 354da81..35e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -909,6 +909,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> struct drm_device *dev = ring->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> uint32_t tmp;
> + int ret;
>
> /* WaEnableLbsSlaRetryTimerDecrement:skl */
> I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
> @@ -979,6 +980,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> /* WaDisableSTUnitPowerOptimization:skl,bxt */
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>
> + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
> + ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);
> + if (ret)
> + return ret;
> +
> return 0;
> }
>
>
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next prev parent reply other threads:[~2016-01-21 11:49 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-13 10:06 [PATCH 0/8] Gen9 HW whitelist and Preemption WA patches Arun Siluvery
2016-01-13 10:06 ` [PATCH 1/8] drm/i915/gen9: Add framework to whitelist specific GPU registers Arun Siluvery
2016-01-13 10:34 ` Ville Syrjälä
2016-01-13 11:39 ` Mika Kuoppala
2016-01-13 10:06 ` [PATCH 2/8] drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelist Arun Siluvery
2016-01-21 11:49 ` Nick Hoath [this message]
2016-01-13 10:06 ` [PATCH 3/8] drm/i915/gen9: Add HDC_CHICKEN1 " Arun Siluvery
2016-01-21 11:54 ` Nick Hoath
2016-01-13 10:06 ` [PATCH 4/8] drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 " Arun Siluvery
2016-01-21 11:56 ` Nick Hoath
2016-01-13 10:06 ` [PATCH 5/8] drm/i915/bxt: Add GEN8_L3SQCREG4 " Arun Siluvery
2016-01-21 12:14 ` Nick Hoath
2016-01-13 10:06 ` [PATCH 6/8] drm/i915/skl: " Arun Siluvery
2016-01-21 12:14 ` Nick Hoath
2016-01-13 10:06 ` [PATCH 7/8] drm/i915/skl: Enable Per context Preemption granularity control Arun Siluvery
2016-01-21 14:37 ` Nick Hoath
2016-01-13 10:06 ` [PATCH 8/8] drm/i915/gen9: Add WaOCLCoherentLineFlush Arun Siluvery
2016-01-13 10:50 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-13 12:28 ` [PATCH v2 1/8] drm/i915/gen9: Add framework to whitelist specific GPU registers Arun Siluvery
2016-01-13 13:03 ` Chris Wilson
2016-01-13 13:41 ` Arun Siluvery
2016-01-13 13:52 ` Chris Wilson
2016-01-13 15:38 ` [PATCH v3 " Arun Siluvery
2016-01-13 19:01 ` Chris Wilson
2016-01-13 19:14 ` Arun Siluvery
2016-01-13 19:38 ` Chris Wilson
2016-01-14 15:27 ` [PATCH v4 " Arun Siluvery
2016-01-19 9:00 ` Daniel Vetter
2016-01-19 10:16 ` Arun Siluvery
2016-01-19 12:03 ` Daniel Vetter
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