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From: Nick Hoath <nicholas.hoath@intel.com>
To: Arun Siluvery <arun.siluvery@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "Kuoppala, Mika" <mika.kuoppala@intel.com>
Subject: Re: [PATCH 5/8] drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist
Date: Thu, 21 Jan 2016 12:14:18 +0000	[thread overview]
Message-ID: <56A0CB9A.7080104@intel.com> (raw)
In-Reply-To: <1452679593-3922-6-git-send-email-arun.siluvery@linux.intel.com>

On 13/01/2016 10:06, Arun Siluvery wrote:
> Required for WaDisableLSQCROPERFforOCL:bxt
>
> According to WA database these are only applicable for BXT:A0 but since
> A0 and A1 shares the same GT these are extended for A1 as well.
>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 7a46cf1..5eb4eea 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1135,10 +1135,15 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
>   	/* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
>   	/* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
>   	/* WaDisableObjectLevelPreemtionForInstanceId:bxt */
> +	/* WaDisableLSQCROPERFforOCL:bxt */
>   	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
>   		ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1);
>   		if (ret)
>   			return ret;
> +
> +		ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
> +		if (ret)
> +			return ret;
>   	}
>
>   	return 0;
>

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  reply	other threads:[~2016-01-21 12:14 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-13 10:06 [PATCH 0/8] Gen9 HW whitelist and Preemption WA patches Arun Siluvery
2016-01-13 10:06 ` [PATCH 1/8] drm/i915/gen9: Add framework to whitelist specific GPU registers Arun Siluvery
2016-01-13 10:34   ` Ville Syrjälä
2016-01-13 11:39   ` Mika Kuoppala
2016-01-13 10:06 ` [PATCH 2/8] drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelist Arun Siluvery
2016-01-21 11:49   ` Nick Hoath
2016-01-13 10:06 ` [PATCH 3/8] drm/i915/gen9: Add HDC_CHICKEN1 " Arun Siluvery
2016-01-21 11:54   ` Nick Hoath
2016-01-13 10:06 ` [PATCH 4/8] drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 " Arun Siluvery
2016-01-21 11:56   ` Nick Hoath
2016-01-13 10:06 ` [PATCH 5/8] drm/i915/bxt: Add GEN8_L3SQCREG4 " Arun Siluvery
2016-01-21 12:14   ` Nick Hoath [this message]
2016-01-13 10:06 ` [PATCH 6/8] drm/i915/skl: " Arun Siluvery
2016-01-21 12:14   ` Nick Hoath
2016-01-13 10:06 ` [PATCH 7/8] drm/i915/skl: Enable Per context Preemption granularity control Arun Siluvery
2016-01-21 14:37   ` Nick Hoath
2016-01-13 10:06 ` [PATCH 8/8] drm/i915/gen9: Add WaOCLCoherentLineFlush Arun Siluvery
2016-01-13 10:50 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-13 12:28 ` [PATCH v2 1/8] drm/i915/gen9: Add framework to whitelist specific GPU registers Arun Siluvery
2016-01-13 13:03   ` Chris Wilson
2016-01-13 13:41     ` Arun Siluvery
2016-01-13 13:52       ` Chris Wilson
2016-01-13 15:38 ` [PATCH v3 " Arun Siluvery
2016-01-13 19:01   ` Chris Wilson
2016-01-13 19:14     ` Arun Siluvery
2016-01-13 19:38       ` Chris Wilson
2016-01-14 15:27 ` [PATCH v4 " Arun Siluvery
2016-01-19  9:00   ` Daniel Vetter
2016-01-19 10:16     ` Arun Siluvery
2016-01-19 12:03       ` Daniel Vetter

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