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From: Marc Zyngier <marc.zyngier@arm.com>
To: Tomasz Nowicki <tn@semihalf.com>,
	tglx@linutronix.de, jason@lakedaemon.net, rjw@rjwysocki.net,
	lorenzo.pieralisi@arm.com, robert.richter@caviumnetworks.com,
	shijie.huang@arm.com, guohanjun@huawei.com,
	Suravee.Suthikulpanit@amd.com
Cc: mw@semihalf.com, graeme.gregory@linaro.org,
	Catalin.Marinas@arm.com, will.deacon@arm.com,
	linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
	hanjun.guo@linaro.org, linux-arm-kernel@lists.infradead.org,
	ddaney.cavm@gmail.com
Subject: Re: [PATCH V3 08/10] irqchip, gicv3, its: Probe ITS in the ACPI way.
Date: Wed, 10 Feb 2016 11:46:03 +0000	[thread overview]
Message-ID: <56BB22FB.5060609@arm.com> (raw)
In-Reply-To: <1453209083-3358-9-git-send-email-tn@semihalf.com>

On 19/01/16 13:11, Tomasz Nowicki wrote:
> Since we prepared ITS for being initialized different that via DT,
> it is now possible to parse MADT and pass mandatory info to
> firmware-agnostic ITS init call.
> 
> Note that we are using here IORT lib to keep track of allocated
> domain handler which will be used to build PCI MSI domain on top
> in the later patches.
> 
> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> ---
>  drivers/irqchip/irq-gic-v3-its.c | 57 +++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 56 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index fecb7a6..42f378a 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -15,10 +15,13 @@
>   * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>  
> +#include <linux/acpi.h>
>  #include <linux/bitmap.h>
>  #include <linux/cpu.h>
>  #include <linux/delay.h>
>  #include <linux/interrupt.h>
> +#include <linux/irqdomain.h>
> +#include <linux/iort.h>
>  #include <linux/log2.h>
>  #include <linux/mm.h>
>  #include <linux/msi.h>
> @@ -1272,6 +1275,11 @@ static int its_irq_gic_domain_alloc(struct irq_domain *domain,
>  		fwspec.param[0] = GIC_IRQ_TYPE_LPI;
>  		fwspec.param[1] = hwirq;
>  		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
> +	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
> +		fwspec.fwnode = domain->parent->fwnode;
> +		fwspec.param_count = 2;
> +		fwspec.param[0] = hwirq;
> +		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
>  	} else {
>  		return -EINVAL;
>  	}
> @@ -1594,6 +1602,52 @@ int its_cpu_init(void)
>  	return 0;
>  }
>  
> +#ifdef CONFIG_ACPI
> +
> +#define ACPI_GICV3_ITS_MEM_SIZE (2 * SZ_64K)
> +
> +static struct irq_domain *its_parent __initdata;
> +
> +static int __init
> +gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
> +			const unsigned long end)
> +{
> +	struct acpi_madt_generic_translator *its_entry;
> +	struct fwnode_handle *domain_handle;
> +	int err;
> +
> +	its_entry = (struct acpi_madt_generic_translator *)header;
> +	domain_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
> +	if (!domain_handle) {
> +		pr_err("Unable to allocate GICv2m domain token\n");

-ECOPYPASTE.

> +		return -ENOMEM;
> +	}
> +
> +	/* ITS works as msi controller in ACPI case */
> +	err = its_probe_one(its_entry->base_address, ACPI_GICV3_ITS_MEM_SIZE,
> +			    its_parent, true, domain_handle);
> +	if (err) {
> +		irq_domain_free_fwnode(domain_handle);
> +		return err;
> +	}
> +	iort_register_domain_token(its_entry->translation_id, domain_handle);

And what if this fails?

> +	return 0;
> +}
> +
> +void __init its_acpi_probe(struct irq_domain *parent_domain)
> +{
> +	int count;
> +
> +	its_parent = parent_domain;
> +	count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
> +				      gic_acpi_parse_madt_its, 0);
> +	if (count <= 0)
> +		pr_info("No valid GIC ITS entries exist\n");
> +}
> +#else
> +static inline void __init its_acpi_probe(struct irq_domain *parent_domain) { }
> +#endif
> +
>  static struct of_device_id its_device_id[] = {
>  	{	.compatible	= "arm,gic-v3-its",	},
>  	{},
> @@ -1610,7 +1664,8 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
>  		     np = of_find_matching_node(np, its_device_id)) {
>  			its_of_probe(np, parent_domain);
>  		}
> -	}
> +	} else
> +		its_acpi_probe(parent_domain);

Missing braces.

>  
>  	if (list_empty(&its_nodes)) {
>  		pr_warn("ITS: No ITS available, not enabling LPIs\n");
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V3 08/10] irqchip, gicv3, its: Probe ITS in the ACPI way.
Date: Wed, 10 Feb 2016 11:46:03 +0000	[thread overview]
Message-ID: <56BB22FB.5060609@arm.com> (raw)
In-Reply-To: <1453209083-3358-9-git-send-email-tn@semihalf.com>

On 19/01/16 13:11, Tomasz Nowicki wrote:
> Since we prepared ITS for being initialized different that via DT,
> it is now possible to parse MADT and pass mandatory info to
> firmware-agnostic ITS init call.
> 
> Note that we are using here IORT lib to keep track of allocated
> domain handler which will be used to build PCI MSI domain on top
> in the later patches.
> 
> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> ---
>  drivers/irqchip/irq-gic-v3-its.c | 57 +++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 56 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index fecb7a6..42f378a 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -15,10 +15,13 @@
>   * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>  
> +#include <linux/acpi.h>
>  #include <linux/bitmap.h>
>  #include <linux/cpu.h>
>  #include <linux/delay.h>
>  #include <linux/interrupt.h>
> +#include <linux/irqdomain.h>
> +#include <linux/iort.h>
>  #include <linux/log2.h>
>  #include <linux/mm.h>
>  #include <linux/msi.h>
> @@ -1272,6 +1275,11 @@ static int its_irq_gic_domain_alloc(struct irq_domain *domain,
>  		fwspec.param[0] = GIC_IRQ_TYPE_LPI;
>  		fwspec.param[1] = hwirq;
>  		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
> +	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
> +		fwspec.fwnode = domain->parent->fwnode;
> +		fwspec.param_count = 2;
> +		fwspec.param[0] = hwirq;
> +		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
>  	} else {
>  		return -EINVAL;
>  	}
> @@ -1594,6 +1602,52 @@ int its_cpu_init(void)
>  	return 0;
>  }
>  
> +#ifdef CONFIG_ACPI
> +
> +#define ACPI_GICV3_ITS_MEM_SIZE (2 * SZ_64K)
> +
> +static struct irq_domain *its_parent __initdata;
> +
> +static int __init
> +gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
> +			const unsigned long end)
> +{
> +	struct acpi_madt_generic_translator *its_entry;
> +	struct fwnode_handle *domain_handle;
> +	int err;
> +
> +	its_entry = (struct acpi_madt_generic_translator *)header;
> +	domain_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
> +	if (!domain_handle) {
> +		pr_err("Unable to allocate GICv2m domain token\n");

-ECOPYPASTE.

> +		return -ENOMEM;
> +	}
> +
> +	/* ITS works as msi controller in ACPI case */
> +	err = its_probe_one(its_entry->base_address, ACPI_GICV3_ITS_MEM_SIZE,
> +			    its_parent, true, domain_handle);
> +	if (err) {
> +		irq_domain_free_fwnode(domain_handle);
> +		return err;
> +	}
> +	iort_register_domain_token(its_entry->translation_id, domain_handle);

And what if this fails?

> +	return 0;
> +}
> +
> +void __init its_acpi_probe(struct irq_domain *parent_domain)
> +{
> +	int count;
> +
> +	its_parent = parent_domain;
> +	count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
> +				      gic_acpi_parse_madt_its, 0);
> +	if (count <= 0)
> +		pr_info("No valid GIC ITS entries exist\n");
> +}
> +#else
> +static inline void __init its_acpi_probe(struct irq_domain *parent_domain) { }
> +#endif
> +
>  static struct of_device_id its_device_id[] = {
>  	{	.compatible	= "arm,gic-v3-its",	},
>  	{},
> @@ -1610,7 +1664,8 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
>  		     np = of_find_matching_node(np, its_device_id)) {
>  			its_of_probe(np, parent_domain);
>  		}
> -	}
> +	} else
> +		its_acpi_probe(parent_domain);

Missing braces.

>  
>  	if (list_empty(&its_nodes)) {
>  		pr_warn("ITS: No ITS available, not enabling LPIs\n");
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  parent reply	other threads:[~2016-02-10 11:46 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-19 13:11 [PATCH V3 00/10] Introduce ACPI world to GICv3 & ITS irqchip Tomasz Nowicki
2016-01-19 13:11 ` Tomasz Nowicki
2016-01-19 13:11 ` [PATCH V3 01/10] irqchip / GICv3: Refactor gic_of_init() for GICv3 driver Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-02-10  9:50   ` Marc Zyngier
2016-02-10  9:50     ` Marc Zyngier
2016-01-19 13:11 ` [PATCH V3 02/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-02-10  9:55   ` Marc Zyngier
2016-02-10  9:55     ` Marc Zyngier
2016-01-19 13:11 ` [PATCH V3 03/10] irqchip,GICv3,ACPI: Add redistributor support via GICC structures Tomasz Nowicki
2016-01-19 13:11   ` [PATCH V3 03/10] irqchip, GICv3, ACPI: " Tomasz Nowicki
2016-02-10 10:16   ` [PATCH V3 03/10] irqchip,GICv3,ACPI: " Marc Zyngier
2016-02-10 10:16     ` Marc Zyngier
2016-01-19 13:11 ` [PATCH V3 04/10] irqchip / GICv3: remove gic root node in ITS Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-02-10 10:25   ` Marc Zyngier
2016-02-10 10:25     ` Marc Zyngier
2016-01-19 13:11 ` [PATCH V3 05/10] irqchip, gicv3, its: Mark its_init() and its children as __init Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-02-10 10:30   ` Marc Zyngier
2016-02-10 10:30     ` Marc Zyngier
2016-01-19 13:11 ` [PATCH V3 06/10] irqchip, GICv3, ITS: Refator ITS dt init code to prepare for ACPI Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-02-10 10:47   ` Marc Zyngier
2016-02-10 10:47     ` Marc Zyngier
2016-02-12 10:10     ` Tomasz Nowicki
2016-02-12 10:10       ` Tomasz Nowicki
2016-02-14  8:06     ` Hanjun Guo
2016-02-14  8:06       ` Hanjun Guo
2016-01-19 13:11 ` [PATCH V3 07/10] ARM64, ACPI, PCI: I/O Remapping Table (IORT) initial support Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-01-19 13:11 ` [PATCH V3 08/10] irqchip, gicv3, its: Probe ITS in the ACPI way Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-01-19 18:04   ` kbuild test robot
2016-01-19 18:04     ` kbuild test robot
2016-01-19 18:04     ` kbuild test robot
2016-02-10 11:46   ` Marc Zyngier [this message]
2016-02-10 11:46     ` Marc Zyngier
2016-02-12 10:14     ` Tomasz Nowicki
2016-02-12 10:14       ` Tomasz Nowicki
2016-01-19 13:11 ` [PATCH V3 09/10] acpi, gicv3, msi: Factor out code that might be reused for ACPI equivalent Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-01-19 13:11 ` [PATCH V3 10/10] acpi, gicv3, its: Use MADT ITS subtable to do PCI/MSI domain initialization Tomasz Nowicki
2016-01-19 13:11   ` Tomasz Nowicki
2016-01-19 18:26   ` kbuild test robot
2016-01-19 18:26     ` kbuild test robot
2016-01-19 18:26     ` kbuild test robot
2016-02-10 12:02   ` Marc Zyngier
2016-02-10 12:02     ` Marc Zyngier
2016-02-12 12:26     ` Tomasz Nowicki
2016-02-12 12:26       ` Tomasz Nowicki
2016-02-12 13:22       ` Marc Zyngier
2016-02-12 13:22         ` Marc Zyngier
2016-01-22 21:56 ` [PATCH V3 00/10] Introduce ACPI world to GICv3 & ITS irqchip Christopher Covington
2016-01-22 21:56   ` Christopher Covington
2016-01-22 23:06 ` Robert Richter
2016-01-22 23:06   ` Robert Richter
2016-01-22 23:06   ` Robert Richter
2016-02-10  8:55 ` Tomasz Nowicki
2016-02-10  8:55   ` Tomasz Nowicki
2016-02-10 10:19   ` Marc Zyngier
2016-02-10 10:19     ` Marc Zyngier
2016-02-10 10:19     ` Marc Zyngier
2016-02-11 11:47 ` Marc Zyngier
2016-02-11 11:47   ` Marc Zyngier
2016-02-11 14:02   ` Tomasz Nowicki
2016-02-11 14:02     ` Tomasz Nowicki

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