* Re: [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
@ 2015-12-09 20:53 ` Ville Syrjälä
2016-02-10 0:28 ` [PATCH V3] " clinton.a.taylor
` (14 subsequent siblings)
15 siblings, 0 replies; 39+ messages in thread
From: Ville Syrjälä @ 2015-12-09 20:53 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Tue, Dec 08, 2015 at 04:15:05PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> to set cdclk based on the max required pixel clock based on VCO
> selected.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 83 +++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp.c | 9 +++-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 5 files changed, 81 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f1a8a53..3ff5abd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1777,7 +1777,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int hpll_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 5d20c64..b787d02 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3019,7 +3019,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2e8d1a8..852dd08 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5671,7 +5671,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5829,17 +5829,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> -
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640) {
> + dev_priv->skl_vco_freq = 8100;
> + }
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> }
>
> /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 308570 );
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5855,7 +5855,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -5879,11 +5879,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9805,6 +9801,64 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + int max_pixclk = ilk_max_pixel_rate(state);
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
> +
> + if (dev_priv->skl_vco_freq == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + }
> + else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + to_intel_atomic_state(state)->cdclk = cdclk;
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
> +
> + skl_set_cdclk(dev_priv, req_cdclk);
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -14945,6 +14999,11 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
>
> switch (INTEL_INFO(dev)->gen) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f335c92..e87adcb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1220,9 +1220,10 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
> }
>
> static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> +skl_edp_set_pll_config(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config)
> {
> u32 ctrl1;
> + u32 vco = 8100;
>
> memset(&pipe_config->dpll_hw_state, 0,
> sizeof(pipe_config->dpll_hw_state));
> @@ -1255,13 +1256,17 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0);
> + vco = 8640;
> break;
>
> }
> +
> + dev_priv->skl_vco_freq = vco;
I think we would need to include this also in the pipe_config, compute
that in intel_dp_compute_config() based on the required link frequency,
and then use that in the calc_cdclk function. That way we'll compute the
right cdclk, and force a modeset across all pipes if it needs to change.
One extra complication is that in theory we'll need to account for all
the pipe's computed vco frequency. For non-eDP I think we'll want the
compute_config to set the pipe_config earget vco to 0, and we'll take
that to mean "don't care". Then the cdclk computation can first walk
all the crtc states (like ilk_max_pixel_rate()) to find the actual
requested vco (and if that's 0, then we can keep using the current
vco), aborting if there's a conflict between two states. We can then
stuff the result into the top level intel_atomic_state for later use
like we do with the cdclk.
intel_modeset_checks() will then have to check if dev_priv->skl_vco_freq
differs from the one we computed so that we'll also force a modeset in
case cdclk remains the same but the vco must be changed (needed since
540MHz can be done with either vco).
Then once we actually set the cdclk we also update
dev_priv->skl_vco_freq with whatever we calculated. Actually we should
handke it same way we handle cdclk, and actually read it out from DPLL0.
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
>
> @@ -1642,7 +1647,7 @@ found:
> }
>
> if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
> - skl_edp_set_pll_config(pipe_config);
> + skl_edp_set_pll_config(dev_priv, pipe_config);
> else if (IS_BROXTON(dev))
> /* handled in ddi */;
> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8963a8a..554d587 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1182,6 +1182,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
2015-12-09 20:53 ` Ville Syrjälä
@ 2016-02-10 0:28 ` clinton.a.taylor
2016-02-10 3:29 ` Thulasimani, Sivakumar
` (2 more replies)
2016-02-10 9:43 ` ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev2) Patchwork
` (13 subsequent siblings)
15 siblings, 3 replies; 39+ messages in thread
From: clinton.a.taylor @ 2016-02-10 0:28 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.
The vco should be tracked at the atomic level and all CRTCs updated if
the required vco is changed. At this time the eDP pll is configured
inside the encoder which has no visibility into the atomic state. When
eDP v1.4 panel that require the 8640 vco are available this may need
to be investigated.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 83 +++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dp.c | 9 +++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
5 files changed, 81 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..372a68f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
-
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640) {
+ dev_priv->skl_vco_freq = 8100;
+ }
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
}
/* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 308570 );
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
- * As of now initialize with max cdclk till
- * we get dynamic cdclk support
- * */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9845,6 +9841,64 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+ if (dev_priv->skl_vco_freq == 8640) {
+ /* vco 8640 */
+ if (max_pixclk > 540000)
+ cdclk = 617140;
+ else if (max_pixclk > 432000)
+ cdclk = 540000;
+ else if (max_pixclk > 308570)
+ cdclk = 432000;
+ else
+ cdclk = 308570;
+ }
+ else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ cdclk = 675000;
+ else if (max_pixclk > 450000)
+ cdclk = 540000;
+ else if (max_pixclk > 337500)
+ cdclk = 450000;
+ else
+ cdclk = 337500;
+ }
+
+ /*
+ * FIXME move the cdclk caclulation to
+ * compute_config() so we can fail gracegully.
+ */
+ if (cdclk > dev_priv->max_cdclk_freq) {
+ DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+ cdclk = dev_priv->max_cdclk_freq;
+ }
+
+ to_intel_atomic_state(state)->cdclk = cdclk;
+
+ return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+ struct drm_device *dev = old_state->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
+
+ skl_set_cdclk(dev_priv, req_cdclk);
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -15002,6 +15056,11 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.modeset_commit_cdclk =
+ skl_modeset_commit_cdclk;
+ dev_priv->display.modeset_calc_cdclk =
+ skl_modeset_calc_cdclk;
}
switch (INTEL_INFO(dev)->gen) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04..0ed25a8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1242,9 +1242,10 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
}
static void
-skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
+skl_edp_set_pll_config(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config)
{
u32 ctrl1;
+ u32 vco = 8100;
memset(&pipe_config->dpll_hw_state, 0,
sizeof(pipe_config->dpll_hw_state));
@@ -1277,13 +1278,17 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
SKL_DPLL0);
+ vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
SKL_DPLL0);
+ vco = 8640;
break;
}
+
+ dev_priv->skl_vco_freq = vco;
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}
@@ -1664,7 +1669,7 @@ found:
}
if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
- skl_edp_set_pll_config(pipe_config);
+ skl_edp_set_pll_config(dev_priv, pipe_config);
else if (IS_BROXTON(dev))
/* handled in ddi */;
else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 878172a..1acfdf9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1191,6 +1191,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-10 0:28 ` [PATCH V3] " clinton.a.taylor
@ 2016-02-10 3:29 ` Thulasimani, Sivakumar
2016-02-10 22:58 ` Clint Taylor
2016-02-10 14:27 ` Ville Syrjälä
2016-02-11 10:48 ` Ville Syrjälä
2 siblings, 1 reply; 39+ messages in thread
From: Thulasimani, Sivakumar @ 2016-02-10 3:29 UTC (permalink / raw)
To: clinton.a.taylor, Intel-gfx
couple of questions since i am looking at SKL code for the first time
> seems we are not reading max cd clock from VBIOS like BDW
even though SKL has limit register to say max cd clock i dont think
it is working, so VBIOS saves the value during boot just like in BDW
and we are supposed to use it. please check VBT spec for the details
> why should we store vco in a separate variable when it is already
available as part of "pipe_config->dpll_hw_state.ctrl1"
> still trying to understand the flow but is "ctrl1"/"VCO" in this patch
written to DPLL_CTRL1 before we change the CD Clock ? if not then
it might be a bug and must be fixed as part of changes
here.
regards,
Sivakumar
On 2/10/2016 5:58 AM, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> to set cdclk based on the max required pixel clock based on VCO
> selected.
>
> The vco should be tracked at the atomic level and all CRTCs updated if
> the required vco is changed. At this time the eDP pll is configured
> inside the encoder which has no visibility into the atomic state. When
> eDP v1.4 panel that require the 8640 vco are available this may need
> to be investigated.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 83 +++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp.c | 9 +++-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 5 files changed, 81 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8216665..f65dd1a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int hpll_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6d5b09f..285adab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9e2273b..372a68f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> -
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640) {
> + dev_priv->skl_vco_freq = 8100;
> + }
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> }
>
> /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 308570 );
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9845,6 +9841,64 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + int max_pixclk = ilk_max_pixel_rate(state);
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
> +
> + if (dev_priv->skl_vco_freq == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + }
> + else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + to_intel_atomic_state(state)->cdclk = cdclk;
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
> +
> + skl_set_cdclk(dev_priv, req_cdclk);
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -15002,6 +15056,11 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
>
> switch (INTEL_INFO(dev)->gen) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a073f04..0ed25a8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1242,9 +1242,10 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
> }
>
> static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> +skl_edp_set_pll_config(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config)
> {
> u32 ctrl1;
> + u32 vco = 8100;
>
> memset(&pipe_config->dpll_hw_state, 0,
> sizeof(pipe_config->dpll_hw_state));
> @@ -1277,13 +1278,17 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0);
> + vco = 8640;
> break;
>
> }
> +
> + dev_priv->skl_vco_freq = vco;
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
>
> @@ -1664,7 +1669,7 @@ found:
> }
>
> if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
> - skl_edp_set_pll_config(pipe_config);
> + skl_edp_set_pll_config(dev_priv, pipe_config);
> else if (IS_BROXTON(dev))
> /* handled in ddi */;
> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 878172a..1acfdf9 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1191,6 +1191,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
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^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-10 3:29 ` Thulasimani, Sivakumar
@ 2016-02-10 22:58 ` Clint Taylor
0 siblings, 0 replies; 39+ messages in thread
From: Clint Taylor @ 2016-02-10 22:58 UTC (permalink / raw)
To: Thulasimani, Sivakumar, Intel-gfx
On 02/09/2016 07:29 PM, Thulasimani, Sivakumar wrote:
> couple of questions since i am looking at SKL code for the first time
> > seems we are not reading max cd clock from VBIOS like BDW
> even though SKL has limit register to say max cd clock i dont think
> it is working, so VBIOS saves the value during boot just like in BDW
> and we are supposed to use it. please check VBT spec for the details
Sounds like you might have found a bug. Submit a patch.
> > why should we store vco in a separate variable when it is already
> available as part of "pipe_config->dpll_hw_state.ctrl1"
We are going to need to know current VCO and target VCO. Current VCO
will have the existing VCO in use and target VCO will be compared to
existing to see in we need a modeset across all CRTCs. ctrl1 will only
contain the new VCO setting. V4 of the patch is in process.
> > still trying to understand the flow but is "ctrl1"/"VCO" in this patch
> written to DPLL_CTRL1 before we change the CD Clock ? if not then
> it might be a bug and must be fixed as part of changes
> here.
>
> regards,
> Sivakumar
>
> On 2/10/2016 5:58 AM, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
>> to set cdclk based on the max required pixel clock based on VCO
>> selected.
>>
>> The vco should be tracked at the atomic level and all CRTCs updated if
>> the required vco is changed. At this time the eDP pll is configured
>> inside the encoder which has no visibility into the atomic state. When
>> eDP v1.4 panel that require the 8640 vco are available this may need
>> to be investigated.
>>
>> V1: initial version
>> V2: add vco tracking in intel_dp_compute_config(), rename
>> skl_boot_cdclk.
>> V3: rebase, V2 feedback not possible as encoders are not aware of
>> atomic.
>>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
>>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>> drivers/gpu/drm/i915/intel_display.c | 83
>> +++++++++++++++++++++++++++++-----
>> drivers/gpu/drm/i915/intel_dp.c | 9 +++-
>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>> 5 files changed, 81 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 8216665..f65dd1a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
>> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>> unsigned int fsb_freq, mem_freq, is_ddr3;
>> - unsigned int skl_boot_cdclk;
>> + unsigned int skl_vco_freq;
>> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
>> unsigned int max_dotclk_freq;
>> unsigned int hpll_freq;
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>> b/drivers/gpu/drm/i915/intel_ddi.c
>> index 6d5b09f..285adab 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
>> int cdclk_freq;
>> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>> - dev_priv->skl_boot_cdclk = cdclk_freq;
>> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
>> if (skl_sanitize_cdclk(dev_priv))
>> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 9e2273b..372a68f 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned
>> int freq)
>> return (freq - 1000) / 500;
>> }
>> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
>> +unsigned int skl_cdclk_get_vco(unsigned int freq)
>> {
>> unsigned int i;
>> @@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private
>> *dev_priv)
>> void skl_init_cdclk(struct drm_i915_private *dev_priv)
>> {
>> - unsigned int required_vco;
>> -
>> /* DPLL0 not enabled (happens on early BIOS versions) */
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
>> /* enable DPLL0 */
>> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
>> - skl_dpll0_enable(dev_priv, required_vco);
>> + if (dev_priv->skl_vco_freq != 8640) {
>> + dev_priv->skl_vco_freq = 8100;
>> + }
>> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
>> }
>> /* set CDCLK to the frequency the BIOS chose */
>> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
>> + skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500
>> : 308570 );
>> /* enable DBUF power */
>> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
>> @@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private
>> *dev_priv)
>> {
>> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
>> uint32_t cdctl = I915_READ(CDCLK_CTL);
>> - int freq = dev_priv->skl_boot_cdclk;
>> + int freq = dev_priv->cdclk_freq;
>> /*
>> * check if the pre-os intialized the display
>> @@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private
>> *dev_priv)
>> /* All well; nothing to sanitize */
>> return false;
>> sanitize:
>> - /*
>> - * As of now initialize with max cdclk till
>> - * we get dynamic cdclk support
>> - * */
>> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
>> +
>> skl_init_cdclk(dev_priv);
>> /* we did have to sanitize */
>> @@ -9845,6 +9841,64 @@ static void
>> broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> broadwell_set_cdclk(dev, req_cdclk);
>> }
>> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(state->dev);
>> + int max_pixclk = ilk_max_pixel_rate(state);
>> + int cdclk;
>> +
>> + /*
>> + * FIXME should also account for plane ratio
>> + * once 64bpp pixel formats are supported.
>> + */
>> +
>> + if (dev_priv->skl_vco_freq == 8640) {
>> + /* vco 8640 */
>> + if (max_pixclk > 540000)
>> + cdclk = 617140;
>> + else if (max_pixclk > 432000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 308570)
>> + cdclk = 432000;
>> + else
>> + cdclk = 308570;
>> + }
>> + else {
>> + /* VCO 8100 */
>> + if (max_pixclk > 540000)
>> + cdclk = 675000;
>> + else if (max_pixclk > 450000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 337500)
>> + cdclk = 450000;
>> + else
>> + cdclk = 337500;
>> + }
>> +
>> + /*
>> + * FIXME move the cdclk caclulation to
>> + * compute_config() so we can fail gracegully.
>> + */
>> + if (cdclk > dev_priv->max_cdclk_freq) {
>> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>> + cdclk, dev_priv->max_cdclk_freq);
>> + cdclk = dev_priv->max_cdclk_freq;
>> + }
>> +
>> + to_intel_atomic_state(state)->cdclk = cdclk;
>> +
>> + return 0;
>> +}
>> +
>> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> +{
>> + struct drm_device *dev = old_state->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
>> +
>> + skl_set_cdclk(dev_priv, req_cdclk);
>> +}
>> +
>> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>> struct intel_crtc_state *crtc_state)
>> {
>> @@ -15002,6 +15056,11 @@ static void intel_init_display(struct
>> drm_device *dev)
>> broxton_modeset_commit_cdclk;
>> dev_priv->display.modeset_calc_cdclk =
>> broxton_modeset_calc_cdclk;
>> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
>> + dev_priv->display.modeset_commit_cdclk =
>> + skl_modeset_commit_cdclk;
>> + dev_priv->display.modeset_calc_cdclk =
>> + skl_modeset_calc_cdclk;
>> }
>> switch (INTEL_INFO(dev)->gen) {
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index a073f04..0ed25a8 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1242,9 +1242,10 @@ intel_dp_connector_unregister(struct
>> intel_connector *intel_connector)
>> }
>> static void
>> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>> +skl_edp_set_pll_config(struct drm_i915_private *dev_priv, struct
>> intel_crtc_state *pipe_config)
>> {
>> u32 ctrl1;
>> + u32 vco = 8100;
>> memset(&pipe_config->dpll_hw_state, 0,
>> sizeof(pipe_config->dpll_hw_state));
>> @@ -1277,13 +1278,17 @@ skl_edp_set_pll_config(struct intel_crtc_state
>> *pipe_config)
>> case 108000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
>> SKL_DPLL0);
>> + vco = 8640;
>> break;
>> case 216000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
>> SKL_DPLL0);
>> + vco = 8640;
>> break;
>> }
>> +
>> + dev_priv->skl_vco_freq = vco;
>> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
>> }
>> @@ -1664,7 +1669,7 @@ found:
>> }
>> if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
>> - skl_edp_set_pll_config(pipe_config);
>> + skl_edp_set_pll_config(dev_priv, pipe_config);
>> else if (IS_BROXTON(dev))
>> /* handled in ddi */;
>> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 878172a..1acfdf9 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1191,6 +1191,7 @@ void bxt_disable_dc9(struct drm_i915_private
>> *dev_priv);
>> void skl_init_cdclk(struct drm_i915_private *dev_priv);
>> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
>> +unsigned int skl_cdclk_get_vco(unsigned int freq);
>> void skl_enable_dc6(struct drm_i915_private *dev_priv);
>> void skl_disable_dc6(struct drm_i915_private *dev_priv);
>> void intel_dp_get_m_n(struct intel_crtc *crtc,
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-10 0:28 ` [PATCH V3] " clinton.a.taylor
2016-02-10 3:29 ` Thulasimani, Sivakumar
@ 2016-02-10 14:27 ` Ville Syrjälä
2016-02-11 1:37 ` Marc Herbert
2016-02-11 10:48 ` Ville Syrjälä
2 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjälä @ 2016-02-10 14:27 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Tue, Feb 09, 2016 at 04:28:27PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> to set cdclk based on the max required pixel clock based on VCO
> selected.
>
> The vco should be tracked at the atomic level and all CRTCs updated if
> the required vco is changed. At this time the eDP pll is configured
> inside the encoder which has no visibility into the atomic state.
Yes it does. The passed in pipe_config is the crtc's state. And
if you want to store the thing in the top level atomic state you
just dig up that up from the crtc state:
to_intel_atomic_state(pipe_config->base.state)
or something along those lines).
> When
> eDP v1.4 panel that require the 8640 vco are available this may need
> to be investigated.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 83 +++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp.c | 9 +++-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 5 files changed, 81 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8216665..f65dd1a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int hpll_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6d5b09f..285adab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9e2273b..372a68f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> -
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640) {
> + dev_priv->skl_vco_freq = 8100;
> + }
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> }
>
> /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 308570 );
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9845,6 +9841,64 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + int max_pixclk = ilk_max_pixel_rate(state);
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
> +
> + if (dev_priv->skl_vco_freq == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + }
> + else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + to_intel_atomic_state(state)->cdclk = cdclk;
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
> +
> + skl_set_cdclk(dev_priv, req_cdclk);
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -15002,6 +15056,11 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
>
> switch (INTEL_INFO(dev)->gen) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a073f04..0ed25a8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1242,9 +1242,10 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
> }
>
> static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> +skl_edp_set_pll_config(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config)
> {
> u32 ctrl1;
> + u32 vco = 8100;
>
> memset(&pipe_config->dpll_hw_state, 0,
> sizeof(pipe_config->dpll_hw_state));
> @@ -1277,13 +1278,17 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0);
> + vco = 8640;
> break;
>
> }
> +
> + dev_priv->skl_vco_freq = vco;
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
>
> @@ -1664,7 +1669,7 @@ found:
> }
>
> if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
> - skl_edp_set_pll_config(pipe_config);
> + skl_edp_set_pll_config(dev_priv, pipe_config);
> else if (IS_BROXTON(dev))
> /* handled in ddi */;
> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 878172a..1acfdf9 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1191,6 +1191,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-10 14:27 ` Ville Syrjälä
@ 2016-02-11 1:37 ` Marc Herbert
2016-02-11 8:29 ` Daniel Vetter
0 siblings, 1 reply; 39+ messages in thread
From: Marc Herbert @ 2016-02-11 1:37 UTC (permalink / raw)
To: Intel-gfx
On 10/02/16 06:27, Ville Syrjälä wrote:
> On Tue, Feb 09, 2016 at 04:28:27PM -0800, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
>> to set cdclk based on the max required pixel clock based on VCO
>> selected.
>>
>> The vco should be tracked at the atomic level and all CRTCs updated if
>> the required vco is changed. At this time the eDP pll is configured
>> inside the encoder which has no visibility into the atomic state.
>
> Yes it does. The passed in pipe_config is the crtc's state. And
> if you want to store the thing in the top level atomic state you
> just dig up that up from the crtc state:
> to_intel_atomic_state(pipe_config->base.state)
> or something along those lines).
Hi, I'm writing this message with Clint. We understand the following:
- This V3 patch as it is now is fixing many use cases for hardware that has been
on the shelves for months.
- It does not fix all use cases with future eDP 1.4 panels.
Example: boot with external monitor and eDP 1.4 lid closed; then lid is
opened and causes a VCO change. However such cases are not supported yet anyway!
If this happens today, the CD clock will move to some uncontrolled value
and the pipelines will NOT be reprogrammed. So this patch does *not regress* any
use case - not even future use cases.
- Present and future use cases can be addressed in two consecutive patches: first
this V3 patch now; then atomic modeset VCO tracking later. This won't increase
development complexity in any way. In other words, the second patch will almost not
change the code of the first patch.
- From a validation perspective this first patch can be validated today with today's
hardware. The second patch cannot be validated yet because eDP 1.4 hardware
is not readily available yet.
- Getting atomic modeset VCO tracking right will take additional development time.
And... did I mention validation already?
- This first patch is fixing many use cases for hardware that has been
on the shelves for months, including failures to reach max resolution.
So - you saw me coming from a distance - can we agree on splitting this work
in two separate patches so we can merge this first V3 patch now? Products have
been needing this for months, thanks!
Cheers,
Marc
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-11 1:37 ` Marc Herbert
@ 2016-02-11 8:29 ` Daniel Vetter
0 siblings, 0 replies; 39+ messages in thread
From: Daniel Vetter @ 2016-02-11 8:29 UTC (permalink / raw)
To: Marc Herbert; +Cc: Intel-gfx
On Wed, Feb 10, 2016 at 05:37:20PM -0800, Marc Herbert wrote:
> On 10/02/16 06:27, Ville Syrjälä wrote:
> > On Tue, Feb 09, 2016 at 04:28:27PM -0800, clinton.a.taylor@intel.com wrote:
> >> From: Clint Taylor <clinton.a.taylor@intel.com>
> >>
> >> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> >> to set cdclk based on the max required pixel clock based on VCO
> >> selected.
> >>
> >> The vco should be tracked at the atomic level and all CRTCs updated if
> >> the required vco is changed. At this time the eDP pll is configured
> >> inside the encoder which has no visibility into the atomic state.
> >
> > Yes it does. The passed in pipe_config is the crtc's state. And
> > if you want to store the thing in the top level atomic state you
> > just dig up that up from the crtc state:
> > to_intel_atomic_state(pipe_config->base.state)
> > or something along those lines).
>
> Hi, I'm writing this message with Clint. We understand the following:
>
> - This V3 patch as it is now is fixing many use cases for hardware that has been
> on the shelves for months.
>
> - It does not fix all use cases with future eDP 1.4 panels.
> Example: boot with external monitor and eDP 1.4 lid closed; then lid is
> opened and causes a VCO change. However such cases are not supported yet anyway!
> If this happens today, the CD clock will move to some uncontrolled value
> and the pipelines will NOT be reprogrammed. So this patch does *not regress* any
> use case - not even future use cases.
>
> - Present and future use cases can be addressed in two consecutive patches: first
> this V3 patch now; then atomic modeset VCO tracking later. This won't increase
> development complexity in any way. In other words, the second patch will almost not
> change the code of the first patch.
>
> - From a validation perspective this first patch can be validated today with today's
> hardware. The second patch cannot be validated yet because eDP 1.4 hardware
> is not readily available yet.
>
> - Getting atomic modeset VCO tracking right will take additional development time.
> And... did I mention validation already?
>
> - This first patch is fixing many use cases for hardware that has been
> on the shelves for months, including failures to reach max resolution.
>
> So - you saw me coming from a distance - can we agree on splitting this work
> in two separate patches so we can merge this first V3 patch now? Products have
> been needing this for months, thanks!
Atomic is the new world, we need this thing to be atomic. Please work
together with Mika Kahola (who's done all the dynamic cdclk infrastucture
together with Ville).
Wrt validation: That's what we have testcases and CI for, plus in-kernel
consistency checks of atomic state.
Thanks, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-10 0:28 ` [PATCH V3] " clinton.a.taylor
2016-02-10 3:29 ` Thulasimani, Sivakumar
2016-02-10 14:27 ` Ville Syrjälä
@ 2016-02-11 10:48 ` Ville Syrjälä
2 siblings, 0 replies; 39+ messages in thread
From: Ville Syrjälä @ 2016-02-11 10:48 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Tue, Feb 09, 2016 at 04:28:27PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> to set cdclk based on the max required pixel clock based on VCO
> selected.
>
> The vco should be tracked at the atomic level and all CRTCs updated if
> the required vco is changed. At this time the eDP pll is configured
> inside the encoder which has no visibility into the atomic state. When
> eDP v1.4 panel that require the 8640 vco are available this may need
> to be investigated.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
BTW I think we might want a patch for stable that just removes the
max_cdclk setup for SKL/KBL (ie. just set max_cdclk=current cdclk).
We'd put that in first, then put in the final version of this patch,
and finally revert the first patch.
Without that, backporting any of the DP/HDMI max_dotclock check patches
to stable won't actually help SKL. Should we decide to backport those
that is.
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev2)
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
2015-12-09 20:53 ` Ville Syrjälä
2016-02-10 0:28 ` [PATCH V3] " clinton.a.taylor
@ 2016-02-10 9:43 ` Patchwork
2016-02-11 23:22 ` [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (12 subsequent siblings)
15 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2016-02-10 9:43 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Summary ==
Series 1609v2 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
http://patchwork.freedesktop.org/api/1.0/series/1609/revisions/2/mbox/
Test core_prop_blob:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test drv_getparams_basic:
Subgroup basic-subslice-total:
skip -> PASS (bdw-nuci7)
Test drv_hangman:
Subgroup error-state-basic:
skip -> PASS (bdw-nuci7)
Test gem_basic:
Subgroup create-close:
skip -> PASS (bdw-nuci7)
Subgroup create-fd-close:
skip -> PASS (bdw-nuci7)
Test gem_ctx_basic:
skip -> PASS (bdw-nuci7)
Test gem_ctx_create:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test gem_ctx_exec:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test gem_ctx_param_basic:
Subgroup basic-default:
skip -> PASS (bdw-nuci7)
Subgroup invalid-ctx-get:
skip -> PASS (bdw-nuci7)
Subgroup invalid-param-get:
skip -> PASS (bdw-nuci7)
Subgroup invalid-size-get:
skip -> PASS (bdw-nuci7)
Subgroup invalid-size-set:
skip -> PASS (bdw-nuci7)
Subgroup non-root-set-no-zeromap:
skip -> PASS (bdw-nuci7)
Subgroup root-set-no-zeromap-disabled:
skip -> PASS (bdw-nuci7)
Test gem_exec_basic:
Subgroup basic-bsd1:
skip -> PASS (bdw-nuci7)
Subgroup basic-bsd2:
skip -> PASS (bdw-nuci7)
Subgroup basic-default:
skip -> PASS (bdw-nuci7)
Subgroup basic-render:
skip -> PASS (bdw-nuci7)
Test gem_flink_basic:
Subgroup bad-flink:
skip -> PASS (bdw-nuci7)
Subgroup bad-open:
skip -> PASS (bdw-nuci7)
Subgroup basic:
skip -> PASS (bdw-nuci7)
Subgroup double-flink:
skip -> PASS (bdw-nuci7)
Test gem_linear_blits:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test gem_mmap:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test gem_mmap_gtt:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Subgroup basic-copy:
skip -> PASS (bdw-nuci7)
Subgroup basic-read:
skip -> PASS (bdw-nuci7)
Subgroup basic-read-no-prefault:
skip -> PASS (bdw-nuci7)
Subgroup basic-read-write:
skip -> PASS (bdw-nuci7)
Subgroup basic-read-write-distinct:
skip -> PASS (bdw-nuci7)
Subgroup basic-short:
skip -> PASS (bdw-nuci7)
Subgroup basic-small-bo-tiledx:
skip -> PASS (bdw-nuci7)
Subgroup basic-small-bo-tiledy:
skip -> PASS (bdw-nuci7)
Subgroup basic-small-copy:
skip -> PASS (bdw-nuci7)
Subgroup basic-write:
skip -> PASS (bdw-nuci7)
Subgroup basic-write-cpu-read-gtt:
skip -> PASS (bdw-nuci7)
Subgroup basic-write-gtt:
skip -> PASS (bdw-nuci7)
Subgroup basic-write-gtt-no-prefault:
skip -> PASS (bdw-nuci7)
Subgroup basic-write-no-prefault:
skip -> PASS (bdw-nuci7)
Subgroup basic-write-read:
skip -> PASS (bdw-nuci7)
Subgroup basic-write-read-distinct:
pass -> SKIP (bdw-nuci7)
Test gem_pread:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test gem_pwrite:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test gem_render_linear_blits:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test gem_render_tiled_blits:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test gem_ringfill:
Subgroup basic-default:
skip -> PASS (bdw-nuci7)
Subgroup basic-default-bomb:
skip -> PASS (bdw-nuci7)
Subgroup basic-default-hang:
skip -> PASS (bdw-nuci7)
Subgroup basic-default-interruptible:
skip -> PASS (bdw-nuci7)
Test gem_storedw_loop:
Subgroup basic-blt:
skip -> PASS (bdw-nuci7)
Subgroup basic-bsd:
skip -> PASS (bdw-nuci7)
Subgroup basic-bsd1:
skip -> PASS (bdw-nuci7)
Subgroup basic-default:
pass -> SKIP (bdw-nuci7)
Subgroup basic-vebox:
skip -> PASS (bdw-nuci7)
Test gem_sync:
Subgroup basic-blt:
skip -> PASS (bdw-nuci7)
Subgroup basic-bsd:
skip -> PASS (bdw-nuci7)
Subgroup basic-bsd1:
skip -> PASS (bdw-nuci7)
Subgroup basic-bsd2:
skip -> PASS (bdw-nuci7)
Subgroup basic-default:
skip -> PASS (bdw-nuci7)
Subgroup basic-render:
skip -> PASS (bdw-nuci7) UNSTABLE
Test gem_tiled_blits:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test gem_tiled_fence_blits:
Subgroup basic:
skip -> PASS (bdw-nuci7)
Test kms_addfb_basic:
Subgroup addfb25-bad-modifier:
skip -> PASS (bdw-nuci7)
Subgroup addfb25-framebuffer-vs-set-tiling:
skip -> PASS (bdw-nuci7)
Subgroup addfb25-modifier-no-flag:
skip -> PASS (bdw-nuci7)
Subgroup addfb25-x-tiled:
skip -> PASS (bdw-nuci7)
Subgroup addfb25-x-tiled-mismatch:
skip -> PASS (bdw-nuci7)
Subgroup addfb25-y-tiled:
skip -> PASS (bdw-nuci7)
Subgroup addfb25-yf-tiled:
skip -> PASS (bdw-nuci7)
Subgroup bad-pitch-0:
skip -> PASS (bdw-nuci7)
Subgroup bad-pitch-1024:
skip -> PASS (bdw-nuci7)
Subgroup bad-pitch-128:
skip -> PASS (bdw-nuci7)
Subgroup bad-pitch-256:
skip -> PASS (bdw-nuci7)
Subgroup bad-pitch-32:
skip -> PASS (bdw-nuci7)
Subgroup bad-pitch-63:
skip -> PASS (bdw-nuci7)
Subgroup bad-pitch-65536:
skip -> PASS (bdw-nuci7)
Subgroup bad-pitch-999:
skip -> PASS (bdw-nuci7)
Subgroup basic:
skip -> PASS (bdw-nuci7)
Subgroup basic-x-tiled:
skip -> PASS (bdw-nuci7)
Subgroup basic-y-tiled:
skip -> PASS (bdw-nuci7)
Subgroup bo-too-small:
skip -> PASS (bdw-nuci7)
Subgroup bo-too-small-due-to-tiling:
skip -> PASS (bdw-nuci7)
Subgroup clobberred-modifier:
skip -> PASS (bdw-nuci7)
Subgroup no-handle:
skip -> PASS (bdw-nuci7)
Subgroup size-max:
skip -> PASS (bdw-nuci7)
Subgroup small-bo:
skip -> PASS (bdw-nuci7)
Subgroup too-wide:
skip -> PASS (bdw-nuci7)
Subgroup unused-handle:
skip -> PASS (bdw-nuci7)
Subgroup unused-modifier:
skip -> PASS (bdw-nuci7)
Subgroup unused-offsets:
skip -> PASS (bdw-nuci7)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
skip -> PASS (bdw-nuci7)
Subgroup basic-flip-vs-wf_vblank:
skip -> PASS (bdw-nuci7)
Subgroup basic-plain-flip:
skip -> PASS (bdw-nuci7)
Test kms_pipe_crc_basic:
Subgroup bad-nb-words-1:
skip -> PASS (bdw-nuci7)
Subgroup bad-nb-words-3:
skip -> PASS (bdw-nuci7)
Subgroup bad-pipe:
skip -> PASS (bdw-nuci7)
Subgroup hang-read-crc-pipe-a:
skip -> PASS (bdw-nuci7)
Subgroup hang-read-crc-pipe-b:
skip -> PASS (bdw-nuci7)
Subgroup hang-read-crc-pipe-c:
skip -> PASS (bdw-nuci7)
Subgroup nonblocking-crc-pipe-a:
skip -> PASS (bdw-nuci7)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
skip -> PASS (bdw-nuci7)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
skip -> PASS (bdw-nuci7)
Subgroup nonblocking-crc-pipe-c:
skip -> PASS (bdw-nuci7)
Subgroup nonblocking-crc-pipe-c-frame-sequence:
skip -> PASS (bdw-nuci7)
Subgroup read-crc-pipe-a-frame-sequence:
skip -> PASS (bdw-nuci7)
Subgroup read-crc-pipe-b:
skip -> PASS (bdw-nuci7)
Subgroup read-crc-pipe-c:
skip -> PASS (bdw-nuci7)
Subgroup read-crc-pipe-c-frame-sequence:
skip -> PASS (bdw-nuci7)
Test kms_setmode:
Subgroup basic-clone-single-crtc:
skip -> PASS (bdw-nuci7)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass -> FAIL (hsw-gt2)
skip -> PASS (bdw-nuci7)
Subgroup basic-rte:
skip -> PASS (bdw-nuci7)
Test pm_rps:
Subgroup basic-api:
skip -> PASS (bdw-nuci7)
Test prime_self_import:
Subgroup basic-llseek-size:
skip -> PASS (bdw-nuci7)
Subgroup basic-with_fd_dup:
skip -> PASS (bdw-nuci7)
Subgroup basic-with_one_bo:
skip -> PASS (bdw-nuci7)
Subgroup basic-with_one_bo_two_files:
skip -> PASS (bdw-nuci7)
bdw-nuci7 total:161 pass:140 dwarn:0 dfail:1 fail:0 skip:20
byt-nuc total:164 pass:140 dwarn:1 dfail:0 fail:0 skip:23
hsw-brixbox total:164 pass:151 dwarn:0 dfail:0 fail:0 skip:13
hsw-gt2 total:164 pass:153 dwarn:0 dfail:0 fail:1 skip:10
ivb-t430s total:164 pass:150 dwarn:0 dfail:0 fail:0 skip:14
snb-dellxps total:164 pass:142 dwarn:0 dfail:0 fail:0 skip:22
snb-x220t total:164 pass:142 dwarn:0 dfail:0 fail:1 skip:21
Results at /archive/results/CI_IGT_test/Patchwork_1387/
2dc2aec853ab9d381000663507bdc874028fce0b drm-intel-nightly: 2016y-02m-10d-08h-56m-16s UTC integration manifest
9e69abb351a7c2e5a32ed76ceea619bb5d4181c0 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (2 preceding siblings ...)
2016-02-10 9:43 ` ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev2) Patchwork
@ 2016-02-11 23:22 ` clinton.a.taylor
2016-02-12 1:11 ` Marc Herbert
2016-02-12 11:18 ` Ville Syrjälä
2016-02-13 2:06 ` [PATCH V5] " clinton.a.taylor
` (11 subsequent siblings)
15 siblings, 2 replies; 39+ messages in thread
From: clinton.a.taylor @ 2016-02-11 23:22 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.
The vco should be tracked at the atomic level and all CRTCs updated if
the required vco is changed. At this time the eDP pll is configured
inside the encoder which has no visibility into the atomic state. When
eDP v1.4 panel that require the 8640 vco are available this may need
to be investigated.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 97 +++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dp.c | 10 ++--
drivers/gpu/drm/i915/intel_drv.h | 4 ++
5 files changed, 97 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..ef4ac34 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
-
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640) {
+ dev_priv->skl_vco_freq = 8100;
+ }
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
}
/* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 308570 );
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
- * As of now initialize with max cdclk till
- * we get dynamic cdclk support
- * */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9845,6 +9841,68 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+ if (to_intel_atomic_state(state)->vco_target == 8640) {
+ /* vco 8640 */
+ if (max_pixclk > 540000)
+ cdclk = 617140;
+ else if (max_pixclk > 432000)
+ cdclk = 540000;
+ else if (max_pixclk > 308570)
+ cdclk = 432000;
+ else
+ cdclk = 308570;
+ }
+ else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ cdclk = 675000;
+ else if (max_pixclk > 450000)
+ cdclk = 540000;
+ else if (max_pixclk > 337500)
+ cdclk = 450000;
+ else
+ cdclk = 337500;
+ }
+
+ /*
+ * FIXME move the cdclk caclulation to
+ * compute_config() so we can fail gracegully.
+ */
+ if (cdclk > dev_priv->max_cdclk_freq) {
+ DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+ cdclk = dev_priv->max_cdclk_freq;
+ }
+
+ to_intel_atomic_state(state)->cdclk = cdclk;
+
+ return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+ struct drm_device *dev = old_state->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
+
+ skl_set_cdclk(dev_priv, req_cdclk);
+
+ if (to_intel_atomic_state(old_state)->vco_target) {
+ dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->vco_target;
+ }
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -13219,11 +13277,13 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
static int intel_modeset_checks(struct drm_atomic_state *state)
{
+ struct drm_device *dev = state->dev;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_i915_private *dev_priv = state->dev->dev_private;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
int ret = 0, i;
+ unsigned int target_vco;
if (!check_digital_port_conflicts(state)) {
DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
@@ -13249,8 +13309,14 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
*/
if (dev_priv->display.modeset_calc_cdclk) {
ret = dev_priv->display.modeset_calc_cdclk(state);
+ target_vco = to_intel_atomic_state(state)->vco_target;
- if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ if (IS_SKYLAKE(dev) || (IS_KABYLAKE(dev))) {
+ if (((target_vco) && (dev_priv->skl_vco_freq != target_vco)) ||
+ (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)) {
+ ret = intel_modeset_all_pipes(state);
+ }
+ } else if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
ret = intel_modeset_all_pipes(state);
if (ret < 0)
@@ -15002,6 +15068,11 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.modeset_commit_cdclk =
+ skl_modeset_commit_cdclk;
+ dev_priv->display.modeset_calc_cdclk =
+ skl_modeset_calc_cdclk;
}
switch (INTEL_INFO(dev)->gen) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04..fbc37fe 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1242,9 +1242,10 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
}
static void
-skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
+skl_edp_set_pll_config(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config)
{
u32 ctrl1;
+ u32 vco = 8100;
memset(&pipe_config->dpll_hw_state, 0,
sizeof(pipe_config->dpll_hw_state));
@@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
SKL_DPLL0);
+ vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
SKL_DPLL0);
+ vco = 8640;
break;
-
}
+
+ to_intel_atomic_state(pipe_config->base.state)->vco_target = vco;
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}
@@ -1664,7 +1668,7 @@ found:
}
if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
- skl_edp_set_pll_config(pipe_config);
+ skl_edp_set_pll_config(dev_priv, pipe_config);
else if (IS_BROXTON(dev))
/* handled in ddi */;
else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 878172a..005e036 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -260,6 +260,9 @@ struct intel_atomic_state {
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
struct intel_wm_config wm_config;
+
+ /* SKL/KBL Only */
+ unsigned int vco_target;
};
struct intel_plane_state {
@@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
--
1.7.9.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-11 23:22 ` [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
@ 2016-02-12 1:11 ` Marc Herbert
2016-02-12 11:25 ` Ville Syrjälä
2016-02-12 11:18 ` Ville Syrjälä
1 sibling, 1 reply; 39+ messages in thread
From: Marc Herbert @ 2016-02-12 1:11 UTC (permalink / raw)
To: clinton.a.taylor, Intel-gfx
[I'm cheating and doing this code review with the author watching over my shoulder]
On 11/02/16 15:22, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> to set cdclk based on the max required pixel clock based on VCO
> selected.
Nit: the main point shouldn't come second.
> The vco should be tracked at the atomic level and all CRTCs updated if
> the required vco is changed. At this time the eDP pll is configured
> inside the encoder which has no visibility into the atomic state.
should be -> is
> When eDP v1.4 panel that require the 8640 vco are available this may need
> to be investigated.
Just say that 8640 can't be tested yet.
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> V4: track target vco is atomic state. modeset all CRTCs if vco changes
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 97 +++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp.c | 10 ++--
> drivers/gpu/drm/i915/intel_drv.h | 4 ++
> 5 files changed, 97 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8216665..f65dd1a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int hpll_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6d5b09f..285adab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
- skl_cdclk_get_vco() and skl_cdclk_frequencies[] should probably be renamed to:
+ skl_get_bios_cdclk_vco() and skl_bios_cdclk_frequencies[]
to avoid confusion with the (different) mapping used in the new skl_modeset_calc_cdclk()
function below.
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9e2273b..ef4ac34 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> -
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640) {
> + dev_priv->skl_vco_freq = 8100;
> + }
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> }
>
> /* set CDCLK to the frequency the BIOS chose */
This comment needs to be updated. Maybe something like:
"initialize to the lowest/most economical freq for now; will modeset very soon anyway".
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 308570 );
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9845,6 +9841,68 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + int max_pixclk = ilk_max_pixel_rate(state);
const ?
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
> +
> + if (to_intel_atomic_state(state)->vco_target == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + }
> + else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
This copied typos will help future grep and search/replace.
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + to_intel_atomic_state(state)->cdclk = cdclk;
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
> +
> + skl_set_cdclk(dev_priv, req_cdclk);
> +
> + if (to_intel_atomic_state(old_state)->vco_target) {
> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->vco_target;
> + }
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -13219,11 +13277,13 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
>
> static int intel_modeset_checks(struct drm_atomic_state *state)
> {
> + struct drm_device *dev = state->dev;
> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> struct drm_i915_private *dev_priv = state->dev->dev_private;
> struct drm_crtc *crtc;
> struct drm_crtc_state *crtc_state;
> int ret = 0, i;
> + unsigned int target_vco;
>
> if (!check_digital_port_conflicts(state)) {
> DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
> @@ -13249,8 +13309,14 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> */
> if (dev_priv->display.modeset_calc_cdclk) {
> ret = dev_priv->display.modeset_calc_cdclk(state);
If you change this to:
if ( ( ret = dev_priv->display.modeset_calc_cdclk(state) ) < 0 )
return ret;
... then you can simplify the boolean expressions below
> + target_vco = to_intel_atomic_state(state)->vco_target;
> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> + if (IS_SKYLAKE(dev) || (IS_KABYLAKE(dev))) {
Extra parens
> + if (((target_vco) && (dev_priv->skl_vco_freq != target_vco)) ||
> + (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)) {
> + ret = intel_modeset_all_pipes(state);
> + }
> + } else if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> ret = intel_modeset_all_pipes(state);
Suggestion (assuming ret change above):
const bool cdclk_change = intel_state->dev_cdclk != dev_priv->cdclk_freq;
const bool vco_change = ( IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ) &&
(target_vco) && (dev_priv->skl_vco_freq != target_vco)) ;
if ( cdclk_change || vco_change )
ret = intel_modeset_all_pipes(state);
> if (ret < 0)
> @@ -15002,6 +15068,11 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
>
> switch (INTEL_INFO(dev)->gen) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a073f04..fbc37fe 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1242,9 +1242,10 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
> }
>
> static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> +skl_edp_set_pll_config(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config)
> {
> u32 ctrl1;
> + u32 vco = 8100;
>
> memset(&pipe_config->dpll_hw_state, 0,
> sizeof(pipe_config->dpll_hw_state));
> @@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0);
> + vco = 8640;
> break;
> -
> }
> +
> + to_intel_atomic_state(pipe_config->base.state)->vco_target = vco;
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
>
> @@ -1664,7 +1668,7 @@ found:
> }
>
> if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
> - skl_edp_set_pll_config(pipe_config);
> + skl_edp_set_pll_config(dev_priv, pipe_config);
Clint says: I will remove the dev_priv param.
> else if (IS_BROXTON(dev))
> /* handled in ddi */;
> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 878172a..005e036 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -260,6 +260,9 @@ struct intel_atomic_state {
>
> struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
> struct intel_wm_config wm_config;
> +
> + /* SKL/KBL Only */
> + unsigned int vco_target;
> };
>
> struct intel_plane_state {
> @@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-12 1:11 ` Marc Herbert
@ 2016-02-12 11:25 ` Ville Syrjälä
0 siblings, 0 replies; 39+ messages in thread
From: Ville Syrjälä @ 2016-02-12 11:25 UTC (permalink / raw)
To: Marc Herbert; +Cc: Intel-gfx
On Thu, Feb 11, 2016 at 05:11:52PM -0800, Marc Herbert wrote:
> [I'm cheating and doing this code review with the author watching over my shoulder]
>
> On 11/02/16 15:22, clinton.a.taylor@intel.com wrote:
> > From: Clint Taylor <clinton.a.taylor@intel.com>
> >
> > Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> > to set cdclk based on the max required pixel clock based on VCO
> > selected.
>
> Nit: the main point shouldn't come second.
>
> > The vco should be tracked at the atomic level and all CRTCs updated if
> > the required vco is changed. At this time the eDP pll is configured
> > inside the encoder which has no visibility into the atomic state.
>
> should be -> is
>
>
> > When eDP v1.4 panel that require the 8640 vco are available this may need
> > to be investigated.
>
> Just say that 8640 can't be tested yet.
>
> > V1: initial version
> > V2: add vco tracking in intel_dp_compute_config(), rename
> > skl_boot_cdclk.
> > V3: rebase, V2 feedback not possible as encoders are not aware of
> > atomic.
> > V4: track target vco is atomic state. modeset all CRTCs if vco changes
> >
> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> > drivers/gpu/drm/i915/intel_display.c | 97 +++++++++++++++++++++++++++++-----
> > drivers/gpu/drm/i915/intel_dp.c | 10 ++--
> > drivers/gpu/drm/i915/intel_drv.h | 4 ++
> > 5 files changed, 97 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 8216665..f65dd1a 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1822,7 +1822,7 @@ struct drm_i915_private {
> > int num_fence_regs; /* 8 on pre-965, 16 otherwise */
> >
> > unsigned int fsb_freq, mem_freq, is_ddr3;
> > - unsigned int skl_boot_cdclk;
> > + unsigned int skl_vco_freq;
> > unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> > unsigned int max_dotclk_freq;
> > unsigned int hpll_freq;
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 6d5b09f..285adab 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> > int cdclk_freq;
> >
> > cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> > - dev_priv->skl_boot_cdclk = cdclk_freq;
> > + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
>
> - skl_cdclk_get_vco() and skl_cdclk_frequencies[] should probably be renamed to:
> + skl_get_bios_cdclk_vco() and skl_bios_cdclk_frequencies[]
>
> to avoid confusion with the (different) mapping used in the new skl_modeset_calc_cdclk()
> function below.
Let's not. This stuff doesn't really have anything to do with the BIOS.
We just want to read out the current hardware state, nothing more.
--
Ville Syrjälä
Intel OTC
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-11 23:22 ` [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
2016-02-12 1:11 ` Marc Herbert
@ 2016-02-12 11:18 ` Ville Syrjälä
2016-02-12 18:51 ` Clint Taylor
1 sibling, 1 reply; 39+ messages in thread
From: Ville Syrjälä @ 2016-02-12 11:18 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Thu, Feb 11, 2016 at 03:22:08PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> to set cdclk based on the max required pixel clock based on VCO
> selected.
>
> The vco should be tracked at the atomic level and all CRTCs updated if
> the required vco is changed. At this time the eDP pll is configured
> inside the encoder which has no visibility into the atomic state. When
> eDP v1.4 panel that require the 8640 vco are available this may need
> to be investigated.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> V4: track target vco is atomic state. modeset all CRTCs if vco changes
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 97 +++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp.c | 10 ++--
> drivers/gpu/drm/i915/intel_drv.h | 4 ++
> 5 files changed, 97 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8216665..f65dd1a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int hpll_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6d5b09f..285adab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
This should really read out the vco from the hardware. But I think we
can leave that for later. The problem really is the 540MHz case since it
can be using either vco frequency (IIRC).
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9e2273b..ef4ac34 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> -
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640) {
> + dev_priv->skl_vco_freq = 8100;
> + }
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> }
>
> /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 308570 );
We really shouldn't change the cdclk if there are active outputs. This
whole area definitely needs more work, for BXT too I already have
some BXT patches lined up in some branch that frob around these parts
a bit, so maybe I should extend that stuff to SKL as well.
In the meantime we don't want to cause a regression at least, so
maybe we can just do something like:
if (!LCPLL_ENABLE) {
...
cdclk = vco == 8100 ? ...;
} else {
cdclk = dev_priv->cdclk_freq;
}
set_cdclk(cdclk);
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9845,6 +9841,68 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + int max_pixclk = ilk_max_pixel_rate(state);
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
A bit of formatting issue with the comment. The stars should be lining up :)
> +
> + if (to_intel_atomic_state(state)->vco_target == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + }
> + else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + to_intel_atomic_state(state)->cdclk = cdclk;
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
> +
> + skl_set_cdclk(dev_priv, req_cdclk);
> +
> + if (to_intel_atomic_state(old_state)->vco_target) {
> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->vco_target;
> + }
skl_set_cdclk() really needs to be taught to do the 'disable+enable pll'
dance so that it can actually change the vco frequency. But I think we
can leave that for a followup so that we can move this forward. A FIXME
comment here would be good though so we don't forget.
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -13219,11 +13277,13 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
>
> static int intel_modeset_checks(struct drm_atomic_state *state)
> {
> + struct drm_device *dev = state->dev;
> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> struct drm_i915_private *dev_priv = state->dev->dev_private;
> struct drm_crtc *crtc;
> struct drm_crtc_state *crtc_state;
> int ret = 0, i;
> + unsigned int target_vco;
>
> if (!check_digital_port_conflicts(state)) {
> DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
> @@ -13249,8 +13309,14 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> */
> if (dev_priv->display.modeset_calc_cdclk) {
> ret = dev_priv->display.modeset_calc_cdclk(state);
> + target_vco = to_intel_atomic_state(state)->vco_target;
>
> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> + if (IS_SKYLAKE(dev) || (IS_KABYLAKE(dev))) {
> + if (((target_vco) && (dev_priv->skl_vco_freq != target_vco)) ||
Hmm. If target_vco is 0, then skl_modeset_calc_cdclk() has already
done something wrong. So I think if the target_vco wasn't set by the
encoder(s) you'll need to just set '->vco_target = dev_priv->vco' before
calling .modeset_calc_cdclk().
BTW the vco_target vs. target_vco is bothering me a bit. In fact I think
it's pretty clear that it's a target value simply due to the fact that
it's part of the atomic state. So we can probably just call it something
like cdclk_pll_vco (keeping the name somewhat generic in case we need
the same treatment for a future platform, and we all know the hardware
folks like to rename things for fun and profit).
> + (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)) {
> + ret = intel_modeset_all_pipes(state);
> + }
> + } else if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> ret = intel_modeset_all_pipes(state);
>
> if (ret < 0)
> @@ -15002,6 +15068,11 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
>
> switch (INTEL_INFO(dev)->gen) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a073f04..fbc37fe 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1242,9 +1242,10 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
> }
>
> static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> +skl_edp_set_pll_config(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config)
dev_priv could be dug out via the pipe_config too, but this way is fine
too IMO.
> {
> u32 ctrl1;
> + u32 vco = 8100;
>
> memset(&pipe_config->dpll_hw_state, 0,
> sizeof(pipe_config->dpll_hw_state));
> @@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0);
> + vco = 8640;
> break;
> -
> }
> +
> + to_intel_atomic_state(pipe_config->base.state)->vco_target = vco;
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
>
> @@ -1664,7 +1668,7 @@ found:
> }
>
> if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
> - skl_edp_set_pll_config(pipe_config);
> + skl_edp_set_pll_config(dev_priv, pipe_config);
> else if (IS_BROXTON(dev))
> /* handled in ddi */;
> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 878172a..005e036 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -260,6 +260,9 @@ struct intel_atomic_state {
>
> struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
> struct intel_wm_config wm_config;
> +
> + /* SKL/KBL Only */
> + unsigned int vco_target;
> };
>
> struct intel_plane_state {
> @@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-12 11:18 ` Ville Syrjälä
@ 2016-02-12 18:51 ` Clint Taylor
0 siblings, 0 replies; 39+ messages in thread
From: Clint Taylor @ 2016-02-12 18:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Intel-gfx
On 02/12/2016 03:18 AM, Ville Syrjälä wrote:
> On Thu, Feb 11, 2016 at 03:22:08PM -0800, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
>> to set cdclk based on the max required pixel clock based on VCO
>> selected.
>>
>> The vco should be tracked at the atomic level and all CRTCs updated if
>> the required vco is changed. At this time the eDP pll is configured
>> inside the encoder which has no visibility into the atomic state. When
>> eDP v1.4 panel that require the 8640 vco are available this may need
>> to be investigated.
>>
>> V1: initial version
>> V2: add vco tracking in intel_dp_compute_config(), rename
>> skl_boot_cdclk.
>> V3: rebase, V2 feedback not possible as encoders are not aware of
>> atomic.
>> V4: track target vco is atomic state. modeset all CRTCs if vco changes
>>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>> drivers/gpu/drm/i915/intel_display.c | 97 +++++++++++++++++++++++++++++-----
>> drivers/gpu/drm/i915/intel_dp.c | 10 ++--
>> drivers/gpu/drm/i915/intel_drv.h | 4 ++
>> 5 files changed, 97 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 8216665..f65dd1a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
>> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>>
>> unsigned int fsb_freq, mem_freq, is_ddr3;
>> - unsigned int skl_boot_cdclk;
>> + unsigned int skl_vco_freq;
>> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
>> unsigned int max_dotclk_freq;
>> unsigned int hpll_freq;
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 6d5b09f..285adab 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
>> int cdclk_freq;
>>
>> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>> - dev_priv->skl_boot_cdclk = cdclk_freq;
>> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
>
> This should really read out the vco from the hardware. But I think we
> can leave that for later. The problem really is the 540MHz case since it
> can be using either vco frequency (IIRC).
>
>> if (skl_sanitize_cdclk(dev_priv))
>> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 9e2273b..ef4ac34 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
>> return (freq - 1000) / 500;
>> }
>>
>> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
>> +unsigned int skl_cdclk_get_vco(unsigned int freq)
>> {
>> unsigned int i;
>>
>> @@ -5821,17 +5821,17 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>>
>> void skl_init_cdclk(struct drm_i915_private *dev_priv)
>> {
>> - unsigned int required_vco;
>> -
>> /* DPLL0 not enabled (happens on early BIOS versions) */
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
>> /* enable DPLL0 */
>> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
>> - skl_dpll0_enable(dev_priv, required_vco);
>> + if (dev_priv->skl_vco_freq != 8640) {
>> + dev_priv->skl_vco_freq = 8100;
>> + }
>> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
>> }
>>
>> /* set CDCLK to the frequency the BIOS chose */
>> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
>> + skl_set_cdclk(dev_priv, (dev_priv->skl_vco_freq == 8100) ? 337500 : 308570 );
>
> We really shouldn't change the cdclk if there are active outputs. This
> whole area definitely needs more work, for BXT too I already have
> some BXT patches lined up in some branch that frob around these parts
> a bit, so maybe I should extend that stuff to SKL as well.
>
> In the meantime we don't want to cause a regression at least, so
> maybe we can just do something like:
>
> if (!LCPLL_ENABLE) {
> ...
> cdclk = vco == 8100 ? ...;
> } else {
> cdclk = dev_priv->cdclk_freq;
> }
> set_cdclk(cdclk);
>
>
>>
>> /* enable DBUF power */
>> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
>> @@ -5847,7 +5847,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>> {
>> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
>> uint32_t cdctl = I915_READ(CDCLK_CTL);
>> - int freq = dev_priv->skl_boot_cdclk;
>> + int freq = dev_priv->cdclk_freq;
>>
>> /*
>> * check if the pre-os intialized the display
>> @@ -5871,11 +5871,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>> /* All well; nothing to sanitize */
>> return false;
>> sanitize:
>> - /*
>> - * As of now initialize with max cdclk till
>> - * we get dynamic cdclk support
>> - * */
>> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
>> +
>> skl_init_cdclk(dev_priv);
>>
>> /* we did have to sanitize */
>> @@ -9845,6 +9841,68 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> broadwell_set_cdclk(dev, req_cdclk);
>> }
>>
>> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(state->dev);
>> + int max_pixclk = ilk_max_pixel_rate(state);
>> + int cdclk;
>> +
>> + /*
>> + * FIXME should also account for plane ratio
>> + * once 64bpp pixel formats are supported.
>> + */
>
> A bit of formatting issue with the comment. The stars should be lining up :)
>
>> +
>> + if (to_intel_atomic_state(state)->vco_target == 8640) {
>> + /* vco 8640 */
>> + if (max_pixclk > 540000)
>> + cdclk = 617140;
>> + else if (max_pixclk > 432000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 308570)
>> + cdclk = 432000;
>> + else
>> + cdclk = 308570;
>> + }
>> + else {
>> + /* VCO 8100 */
>> + if (max_pixclk > 540000)
>> + cdclk = 675000;
>> + else if (max_pixclk > 450000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 337500)
>> + cdclk = 450000;
>> + else
>> + cdclk = 337500;
>> + }
>> +
>> + /*
>> + * FIXME move the cdclk caclulation to
>> + * compute_config() so we can fail gracegully.
>> + */
>> + if (cdclk > dev_priv->max_cdclk_freq) {
>> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>> + cdclk, dev_priv->max_cdclk_freq);
>> + cdclk = dev_priv->max_cdclk_freq;
>> + }
>> +
>> + to_intel_atomic_state(state)->cdclk = cdclk;
>> +
>> + return 0;
>> +}
>> +
>> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> +{
>> + struct drm_device *dev = old_state->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
>> +
>> + skl_set_cdclk(dev_priv, req_cdclk);
>> +
>> + if (to_intel_atomic_state(old_state)->vco_target) {
>> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->vco_target;
>> + }
>
> skl_set_cdclk() really needs to be taught to do the 'disable+enable pll'
> dance so that it can actually change the vco frequency. But I think we
> can leave that for a followup so that we can move this forward. A FIXME
> comment here would be good though so we don't forget.
Ok
>
>> +}
>> +
>> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>> struct intel_crtc_state *crtc_state)
>> {
>> @@ -13219,11 +13277,13 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
>>
>> static int intel_modeset_checks(struct drm_atomic_state *state)
>> {
>> + struct drm_device *dev = state->dev;
>> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>> struct drm_i915_private *dev_priv = state->dev->dev_private;
>> struct drm_crtc *crtc;
>> struct drm_crtc_state *crtc_state;
>> int ret = 0, i;
>> + unsigned int target_vco;
>>
>> if (!check_digital_port_conflicts(state)) {
>> DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
>> @@ -13249,8 +13309,14 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>> */
>> if (dev_priv->display.modeset_calc_cdclk) {
>> ret = dev_priv->display.modeset_calc_cdclk(state);
>> + target_vco = to_intel_atomic_state(state)->vco_target;
>>
>> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
>> + if (IS_SKYLAKE(dev) || (IS_KABYLAKE(dev))) {
>> + if (((target_vco) && (dev_priv->skl_vco_freq != target_vco)) ||
>
> Hmm. If target_vco is 0, then skl_modeset_calc_cdclk() has already
> done something wrong. So I think if the target_vco wasn't set by the
> encoder(s) you'll need to just set '->vco_target = dev_priv->vco' before
> calling .modeset_calc_cdclk().
modeset_calc_cdclk defaults to the 8100 VCO. This is fine for all eDP
link rates except the new V1.4 rates. If target_vco is 0 copying in
dev_priv = vco is the correct thing to do. Thanks!
>
> BTW the vco_target vs. target_vco is bothering me a bit. In fact I think
> it's pretty clear that it's a target value simply due to the fact that
> it's part of the atomic state. So we can probably just call it something
> like cdclk_pll_vco (keeping the name somewhat generic in case we need
> the same treatment for a future platform, and we all know the hardware
> folks like to rename things for fun and profit).
agreed.
>
>> + (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)) {
>> + ret = intel_modeset_all_pipes(state);
>> + }
>> + } else if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
>> ret = intel_modeset_all_pipes(state);
>>
>> if (ret < 0)
>> @@ -15002,6 +15068,11 @@ static void intel_init_display(struct drm_device *dev)
>> broxton_modeset_commit_cdclk;
>> dev_priv->display.modeset_calc_cdclk =
>> broxton_modeset_calc_cdclk;
>> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
>> + dev_priv->display.modeset_commit_cdclk =
>> + skl_modeset_commit_cdclk;
>> + dev_priv->display.modeset_calc_cdclk =
>> + skl_modeset_calc_cdclk;
>> }
>>
>> switch (INTEL_INFO(dev)->gen) {
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index a073f04..fbc37fe 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1242,9 +1242,10 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
>> }
>>
>> static void
>> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>> +skl_edp_set_pll_config(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config)
>
> dev_priv could be dug out via the pipe_config too, but this way is fine
> too IMO.
dev_priv is not used anymore and I can remove this parameter.
>
>> {
>> u32 ctrl1;
>> + u32 vco = 8100;
>>
>> memset(&pipe_config->dpll_hw_state, 0,
>> sizeof(pipe_config->dpll_hw_state));
>> @@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>> case 108000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
>> SKL_DPLL0);
>> + vco = 8640;
>> break;
>> case 216000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
>> SKL_DPLL0);
>> + vco = 8640;
>> break;
>> -
>> }
>> +
>> + to_intel_atomic_state(pipe_config->base.state)->vco_target = vco;
>> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
>> }
>>
>> @@ -1664,7 +1668,7 @@ found:
>> }
>>
>> if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
>> - skl_edp_set_pll_config(pipe_config);
>> + skl_edp_set_pll_config(dev_priv, pipe_config);
>> else if (IS_BROXTON(dev))
>> /* handled in ddi */;
>> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 878172a..005e036 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -260,6 +260,9 @@ struct intel_atomic_state {
>>
>> struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
>> struct intel_wm_config wm_config;
>> +
>> + /* SKL/KBL Only */
>> + unsigned int vco_target;
>> };
>>
>> struct intel_plane_state {
>> @@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>> void skl_init_cdclk(struct drm_i915_private *dev_priv);
>> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
>> +unsigned int skl_cdclk_get_vco(unsigned int freq);
>> void skl_enable_dc6(struct drm_i915_private *dev_priv);
>> void skl_disable_dc6(struct drm_i915_private *dev_priv);
>> void intel_dp_get_m_n(struct intel_crtc *crtc,
>> --
>> 1.7.9.5
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH V5] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (3 preceding siblings ...)
2016-02-11 23:22 ` [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
@ 2016-02-13 2:06 ` clinton.a.taylor
2016-02-15 13:16 ` Ville Syrjälä
2016-02-16 9:45 ` ✗ Fi.CI.BAT: warning for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev4) Patchwork
` (10 subsequent siblings)
15 siblings, 1 reply; 39+ messages in thread
From: clinton.a.taylor @ 2016-02-13 2:06 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 114 +++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dp.c | 6 +-
drivers/gpu/drm/i915/intel_drv.h | 4 ++
5 files changed, 111 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..c283abd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
+ unsigned int cdclk;
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640)
+ dev_priv->skl_vco_freq = 8100;
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+ cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+ } else {
+ cdclk = dev_priv->cdclk_freq;
}
- /* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ /* set CDCLK to the lowest frequency, Modeset follows */
+ skl_set_cdclk(dev_priv, cdclk);
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
- * As of now initialize with max cdclk till
- * we get dynamic cdclk support
- * */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9845,6 +9845,70 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ const int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+ if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
+ /* vco 8640 */
+ if (max_pixclk > 540000)
+ cdclk = 617140;
+ else if (max_pixclk > 432000)
+ cdclk = 540000;
+ else if (max_pixclk > 308570)
+ cdclk = 432000;
+ else
+ cdclk = 308570;
+ } else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ cdclk = 675000;
+ else if (max_pixclk > 450000)
+ cdclk = 540000;
+ else if (max_pixclk > 337500)
+ cdclk = 450000;
+ else
+ cdclk = 337500;
+ }
+
+ /*
+ * FIXME move the cdclk caclulation to
+ * compute_config() so we can fail gracegully.
+ */
+ if (cdclk > dev_priv->max_cdclk_freq) {
+ DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+ cdclk = dev_priv->max_cdclk_freq;
+ }
+
+ to_intel_atomic_state(state)->cdclk = cdclk;
+
+ return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+ struct drm_device *dev = old_state->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
+
+ /*
+ * FIXME disable/enable PLL should wrap set_cdclk()
+ */
+ skl_set_cdclk(dev_priv, req_cdclk);
+
+ if (to_intel_atomic_state(old_state)->cdclk_pll_vco) {
+ dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
+ }
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -13219,11 +13283,14 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
static int intel_modeset_checks(struct drm_atomic_state *state)
{
+ struct drm_device *dev = state->dev;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_i915_private *dev_priv = state->dev->dev_private;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
int ret = 0, i;
+ unsigned int target_vco = 0;
+ bool cdclk_change, vco_change;
if (!check_digital_port_conflicts(state)) {
DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
@@ -13248,9 +13315,22 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
* adjusted_mode bits in the crtc directly.
*/
if (dev_priv->display.modeset_calc_cdclk) {
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ target_vco = to_intel_atomic_state(state)->cdclk_pll_vco;
+ if (!target_vco)
+ to_intel_atomic_state(state)->cdclk_pll_vco =
+ dev_priv->skl_vco_freq;
+ }
+
ret = dev_priv->display.modeset_calc_cdclk(state);
+ if (ret < 0)
+ return ret;
+
+ cdclk_change = intel_state->dev_cdclk != dev_priv->cdclk_freq;
+ vco_change = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
+ (target_vco) && (dev_priv->skl_vco_freq != target_vco));
- if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ if (cdclk_change || vco_change)
ret = intel_modeset_all_pipes(state);
if (ret < 0)
@@ -15002,6 +15082,11 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.modeset_commit_cdclk =
+ skl_modeset_commit_cdclk;
+ dev_priv->display.modeset_calc_cdclk =
+ skl_modeset_calc_cdclk;
}
switch (INTEL_INFO(dev)->gen) {
@@ -15725,7 +15810,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (crtc_state->base.active) {
dev_priv->active_crtcs |= 1 << crtc->pipe;
- if (IS_BROADWELL(dev_priv)) {
+ if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
+ IS_KABYLAKE(dev_priv)) {
pixclk = ilk_pipe_pixel_rate(crtc_state);
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04..afa21b6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1245,6 +1245,7 @@ static void
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
{
u32 ctrl1;
+ u32 vco = 8100;
memset(&pipe_config->dpll_hw_state, 0,
sizeof(pipe_config->dpll_hw_state));
@@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
SKL_DPLL0);
+ vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
SKL_DPLL0);
+ vco = 8640;
break;
-
}
+
+ to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 878172a..47936d4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -260,6 +260,9 @@ struct intel_atomic_state {
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
struct intel_wm_config wm_config;
+
+ /* SKL/KBL Only */
+ unsigned int cdclk_pll_vco;
};
struct intel_plane_state {
@@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V5] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-13 2:06 ` [PATCH V5] " clinton.a.taylor
@ 2016-02-15 13:16 ` Ville Syrjälä
2016-02-16 2:44 ` Thulasimani, Sivakumar
0 siblings, 1 reply; 39+ messages in thread
From: Ville Syrjälä @ 2016-02-15 13:16 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Fri, Feb 12, 2016 at 06:06:10PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Set cdclk based on the max required pixel clock based on VCO
> selected. Track boot vco instead of boot cdclk.
>
> The vco is now tracked at the atomic level and all CRTCs updated if
> the required vco is changed. Not tested with eDP v1.4 panels that
> require 8640 vco due to availability.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> V4: track target vco is atomic state. modeset all CRTCs if vco changes
> V5: rename atomic variable, cleaner if/else logic, use existing vco if
> encoder does not return a new vco value. check_patch.pl cleanup
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 114 +++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp.c | 6 +-
> drivers/gpu/drm/i915/intel_drv.h | 4 ++
> 5 files changed, 111 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8216665..f65dd1a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int hpll_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6d5b09f..285adab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9e2273b..c283abd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> + unsigned int cdclk;
>
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640)
> + dev_priv->skl_vco_freq = 8100;
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
> + } else {
> + cdclk = dev_priv->cdclk_freq;
> }
>
> - /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + /* set CDCLK to the lowest frequency, Modeset follows */
> + skl_set_cdclk(dev_priv, cdclk);
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9845,6 +9845,70 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + const int max_pixclk = ilk_max_pixel_rate(state);
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
> +
> + if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + } else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + to_intel_atomic_state(state)->cdclk = cdclk;
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
> +
> + /*
> + * FIXME disable/enable PLL should wrap set_cdclk()
> + */
> + skl_set_cdclk(dev_priv, req_cdclk);
> +
> + if (to_intel_atomic_state(old_state)->cdclk_pll_vco) {
> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
The if statement seems pointless. We should never get here without a
valid vco in the state. Or if we do, there is a bug somewhere else.
> + }
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -13219,11 +13283,14 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
>
> static int intel_modeset_checks(struct drm_atomic_state *state)
> {
> + struct drm_device *dev = state->dev;
> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> struct drm_i915_private *dev_priv = state->dev->dev_private;
> struct drm_crtc *crtc;
> struct drm_crtc_state *crtc_state;
> int ret = 0, i;
> + unsigned int target_vco = 0;
> + bool cdclk_change, vco_change;
>
> if (!check_digital_port_conflicts(state)) {
> DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
> @@ -13248,9 +13315,22 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> * adjusted_mode bits in the crtc directly.
> */
> if (dev_priv->display.modeset_calc_cdclk) {
> + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + target_vco = to_intel_atomic_state(state)->cdclk_pll_vco;
> + if (!target_vco)
> + to_intel_atomic_state(state)->cdclk_pll_vco =
> + dev_priv->skl_vco_freq;
> + }
> +
> ret = dev_priv->display.modeset_calc_cdclk(state);
> + if (ret < 0)
> + return ret;
> +
> + cdclk_change = intel_state->dev_cdclk != dev_priv->cdclk_freq;
> + vco_change = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
> + (target_vco) && (dev_priv->skl_vco_freq != target_vco));
I don't think you need all those SKL||KBL checks. And target_vco seems
like a rather pointless variable. Oh and cdclk_change and vco_change
could have tighter scope. Eg. something as simple as this ought
to work I think:
if (dev_priv->display.modeset_calc_cdclk) {
bool cdclk_change, vco_change;
if (intel_state->cdclk_pll_vco == 0)
intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
ret = dev_priv->display.modeset_calc_cdclk(state);
if (ret)
return ret;
cdclk_change = intel_state->dev_cdclk != dev_priv->cdclk_freq;
vco_change = intel_state->skl_vco_freq != dev_priv->skl_vco_freq;
...
Otherwise it looks pretty good to me.
>
> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> + if (cdclk_change || vco_change)
> ret = intel_modeset_all_pipes(state);
>
> if (ret < 0)
> @@ -15002,6 +15082,11 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
>
> switch (INTEL_INFO(dev)->gen) {
> @@ -15725,7 +15810,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> if (crtc_state->base.active) {
> dev_priv->active_crtcs |= 1 << crtc->pipe;
>
> - if (IS_BROADWELL(dev_priv)) {
> + if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
> + IS_KABYLAKE(dev_priv)) {
> pixclk = ilk_pipe_pixel_rate(crtc_state);
>
> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a073f04..afa21b6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1245,6 +1245,7 @@ static void
> skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> {
> u32 ctrl1;
> + u32 vco = 8100;
>
> memset(&pipe_config->dpll_hw_state, 0,
> sizeof(pipe_config->dpll_hw_state));
> @@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0);
> + vco = 8640;
> break;
> -
> }
> +
> + to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 878172a..47936d4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -260,6 +260,9 @@ struct intel_atomic_state {
>
> struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
> struct intel_wm_config wm_config;
> +
> + /* SKL/KBL Only */
> + unsigned int cdclk_pll_vco;
> };
>
> struct intel_plane_state {
> @@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V5] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-15 13:16 ` Ville Syrjälä
@ 2016-02-16 2:44 ` Thulasimani, Sivakumar
0 siblings, 0 replies; 39+ messages in thread
From: Thulasimani, Sivakumar @ 2016-02-16 2:44 UTC (permalink / raw)
To: Ville Syrjälä, clinton.a.taylor; +Cc: Intel-gfx
On 2/15/2016 6:46 PM, Ville Syrjälä wrote:
> On Fri, Feb 12, 2016 at 06:06:10PM -0800, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> Set cdclk based on the max required pixel clock based on VCO
>> selected. Track boot vco instead of boot cdclk.
>>
>> The vco is now tracked at the atomic level and all CRTCs updated if
>> the required vco is changed. Not tested with eDP v1.4 panels that
>> require 8640 vco due to availability.
>>
>> V1: initial version
>> V2: add vco tracking in intel_dp_compute_config(), rename
>> skl_boot_cdclk.
>> V3: rebase, V2 feedback not possible as encoders are not aware of
>> atomic.
>> V4: track target vco is atomic state. modeset all CRTCs if vco changes
>> V5: rename atomic variable, cleaner if/else logic, use existing vco if
>> encoder does not return a new vco value. check_patch.pl cleanup
>>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>> drivers/gpu/drm/i915/intel_display.c | 114 +++++++++++++++++++++++++++++-----
>> drivers/gpu/drm/i915/intel_dp.c | 6 +-
>> drivers/gpu/drm/i915/intel_drv.h | 4 ++
>> 5 files changed, 111 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 8216665..f65dd1a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
>> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>>
>> unsigned int fsb_freq, mem_freq, is_ddr3;
>> - unsigned int skl_boot_cdclk;
>> + unsigned int skl_vco_freq;
>> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
>> unsigned int max_dotclk_freq;
>> unsigned int hpll_freq;
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 6d5b09f..285adab 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
>> int cdclk_freq;
>>
>> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>> - dev_priv->skl_boot_cdclk = cdclk_freq;
>> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
>> if (skl_sanitize_cdclk(dev_priv))
>> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 9e2273b..c283abd 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
>> return (freq - 1000) / 500;
>> }
>>
>> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
>> +unsigned int skl_cdclk_get_vco(unsigned int freq)
>> {
>> unsigned int i;
>>
>> @@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>>
>> void skl_init_cdclk(struct drm_i915_private *dev_priv)
>> {
>> - unsigned int required_vco;
>> + unsigned int cdclk;
>>
>> /* DPLL0 not enabled (happens on early BIOS versions) */
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
>> /* enable DPLL0 */
>> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
>> - skl_dpll0_enable(dev_priv, required_vco);
>> + if (dev_priv->skl_vco_freq != 8640)
>> + dev_priv->skl_vco_freq = 8100;
>> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
>> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
>> + } else {
>> + cdclk = dev_priv->cdclk_freq;
>> }
>>
>> - /* set CDCLK to the frequency the BIOS chose */
>> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
>> + /* set CDCLK to the lowest frequency, Modeset follows */
>> + skl_set_cdclk(dev_priv, cdclk);
>>
>> /* enable DBUF power */
>> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
>> @@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>> {
>> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
>> uint32_t cdctl = I915_READ(CDCLK_CTL);
>> - int freq = dev_priv->skl_boot_cdclk;
>> + int freq = dev_priv->cdclk_freq;
>>
>> /*
>> * check if the pre-os intialized the display
>> @@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>> /* All well; nothing to sanitize */
>> return false;
>> sanitize:
>> - /*
>> - * As of now initialize with max cdclk till
>> - * we get dynamic cdclk support
>> - * */
>> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
>> +
>> skl_init_cdclk(dev_priv);
>>
>> /* we did have to sanitize */
>> @@ -9845,6 +9845,70 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> broadwell_set_cdclk(dev, req_cdclk);
>> }
>>
>> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(state->dev);
>> + const int max_pixclk = ilk_max_pixel_rate(state);
>> + int cdclk;
>> +
>> + /*
>> + * FIXME should also account for plane ratio
>> + * once 64bpp pixel formats are supported.
>> + */
>> +
>> + if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
not necessarily a comment for this patch (since bugs are waiting on this
:) )
if we can take advantage of VCO programming for non edp scenarios
we can program lower CD Clocks and save more power. i.e assume you
have MIPI with pixel clock less than 300MHz and full HD HDMI. both
can be driven by 308MHz but since we have tied our cd clock
programming to VCO we might end up with 337.5MHz.
to rephrase it, CD clock is controlled by two variables vco &
cd clock programmed, we control only one today in the
cd clock calc and commit path which is not
optimal.
regards,
Sivakumar
>> + /* vco 8640 */
>> + if (max_pixclk > 540000)
>> + cdclk = 617140;
>> + else if (max_pixclk > 432000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 308570)
>> + cdclk = 432000;
>> + else
>> + cdclk = 308570;
>> + } else {
>> + /* VCO 8100 */
>> + if (max_pixclk > 540000)
>> + cdclk = 675000;
>> + else if (max_pixclk > 450000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 337500)
>> + cdclk = 450000;
>> + else
>> + cdclk = 337500;
>> + }
>> +
>> + /*
>> + * FIXME move the cdclk caclulation to
>> + * compute_config() so we can fail gracegully.
>> + */
>> + if (cdclk > dev_priv->max_cdclk_freq) {
>> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>> + cdclk, dev_priv->max_cdclk_freq);
>> + cdclk = dev_priv->max_cdclk_freq;
>> + }
>> +
>> + to_intel_atomic_state(state)->cdclk = cdclk;
>> +
>> + return 0;
>> +}
>> +
>> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> +{
>> + struct drm_device *dev = old_state->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
>> +
>> + /*
>> + * FIXME disable/enable PLL should wrap set_cdclk()
>> + */
>> + skl_set_cdclk(dev_priv, req_cdclk);
>> +
>> + if (to_intel_atomic_state(old_state)->cdclk_pll_vco) {
>> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> The if statement seems pointless. We should never get here without a
> valid vco in the state. Or if we do, there is a bug somewhere else.
>
>> + }
>> +}
>> +
>> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>> struct intel_crtc_state *crtc_state)
>> {
>> @@ -13219,11 +13283,14 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
>>
>> static int intel_modeset_checks(struct drm_atomic_state *state)
>> {
>> + struct drm_device *dev = state->dev;
>> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>> struct drm_i915_private *dev_priv = state->dev->dev_private;
>> struct drm_crtc *crtc;
>> struct drm_crtc_state *crtc_state;
>> int ret = 0, i;
>> + unsigned int target_vco = 0;
>> + bool cdclk_change, vco_change;
>>
>> if (!check_digital_port_conflicts(state)) {
>> DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
>> @@ -13248,9 +13315,22 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>> * adjusted_mode bits in the crtc directly.
>> */
>> if (dev_priv->display.modeset_calc_cdclk) {
>> + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
>> + target_vco = to_intel_atomic_state(state)->cdclk_pll_vco;
>> + if (!target_vco)
>> + to_intel_atomic_state(state)->cdclk_pll_vco =
>> + dev_priv->skl_vco_freq;
>> + }
>> +
>> ret = dev_priv->display.modeset_calc_cdclk(state);
>> + if (ret < 0)
>> + return ret;
>> +
>> + cdclk_change = intel_state->dev_cdclk != dev_priv->cdclk_freq;
>> + vco_change = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
>> + (target_vco) && (dev_priv->skl_vco_freq != target_vco));
> I don't think you need all those SKL||KBL checks. And target_vco seems
> like a rather pointless variable. Oh and cdclk_change and vco_change
> could have tighter scope. Eg. something as simple as this ought
> to work I think:
>
> if (dev_priv->display.modeset_calc_cdclk) {
> bool cdclk_change, vco_change;
>
> if (intel_state->cdclk_pll_vco == 0)
> intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
>
> ret = dev_priv->display.modeset_calc_cdclk(state);
> if (ret)
> return ret;
>
> cdclk_change = intel_state->dev_cdclk != dev_priv->cdclk_freq;
> vco_change = intel_state->skl_vco_freq != dev_priv->skl_vco_freq;
> ...
>
> Otherwise it looks pretty good to me.
>
>>
>> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
>> + if (cdclk_change || vco_change)
>> ret = intel_modeset_all_pipes(state);
>>
>> if (ret < 0)
>> @@ -15002,6 +15082,11 @@ static void intel_init_display(struct drm_device *dev)
>> broxton_modeset_commit_cdclk;
>> dev_priv->display.modeset_calc_cdclk =
>> broxton_modeset_calc_cdclk;
>> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
>> + dev_priv->display.modeset_commit_cdclk =
>> + skl_modeset_commit_cdclk;
>> + dev_priv->display.modeset_calc_cdclk =
>> + skl_modeset_calc_cdclk;
>> }
>>
>> switch (INTEL_INFO(dev)->gen) {
>> @@ -15725,7 +15810,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>> if (crtc_state->base.active) {
>> dev_priv->active_crtcs |= 1 << crtc->pipe;
>>
>> - if (IS_BROADWELL(dev_priv)) {
>> + if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
>> + IS_KABYLAKE(dev_priv)) {
>> pixclk = ilk_pipe_pixel_rate(crtc_state);
>>
>> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index a073f04..afa21b6 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1245,6 +1245,7 @@ static void
>> skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>> {
>> u32 ctrl1;
>> + u32 vco = 8100;
>>
>> memset(&pipe_config->dpll_hw_state, 0,
>> sizeof(pipe_config->dpll_hw_state));
>> @@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>> case 108000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
>> SKL_DPLL0);
>> + vco = 8640;
>> break;
>> case 216000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
>> SKL_DPLL0);
>> + vco = 8640;
>> break;
>> -
>> }
>> +
>> + to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
>> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 878172a..47936d4 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -260,6 +260,9 @@ struct intel_atomic_state {
>>
>> struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
>> struct intel_wm_config wm_config;
>> +
>> + /* SKL/KBL Only */
>> + unsigned int cdclk_pll_vco;
>> };
>>
>> struct intel_plane_state {
>> @@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>> void skl_init_cdclk(struct drm_i915_private *dev_priv);
>> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
>> +unsigned int skl_cdclk_get_vco(unsigned int freq);
>> void skl_enable_dc6(struct drm_i915_private *dev_priv);
>> void skl_disable_dc6(struct drm_i915_private *dev_priv);
>> void intel_dp_get_m_n(struct intel_crtc *crtc,
>> --
>> 1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev4)
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (4 preceding siblings ...)
2016-02-13 2:06 ` [PATCH V5] " clinton.a.taylor
@ 2016-02-16 9:45 ` Patchwork
2016-02-16 17:19 ` [PATCH V6] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (9 subsequent siblings)
15 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2016-02-16 9:45 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Summary ==
Series 1609v4 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
http://patchwork.freedesktop.org/api/1.0/series/1609/revisions/4/mbox/
Test gem_sync:
Subgroup basic-bsd:
dmesg-fail -> PASS (ilk-hp8440p)
Subgroup basic-vebox:
dmesg-fail -> PASS (hsw-brixbox)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (ivb-t430s)
Test pm_rpm:
Subgroup basic-pci-d3-state:
dmesg-warn -> PASS (bsw-nuc-2)
Subgroup basic-rte:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> DMESG-WARN (byt-nuc) UNSTABLE
bdw-nuci7 total:162 pass:152 dwarn:0 dfail:0 fail:0 skip:10
bdw-ultra total:165 pass:152 dwarn:0 dfail:0 fail:0 skip:13
bsw-nuc-2 total:165 pass:135 dwarn:1 dfail:0 fail:0 skip:29
byt-nuc total:165 pass:140 dwarn:1 dfail:0 fail:0 skip:24
hsw-brixbox total:165 pass:151 dwarn:0 dfail:0 fail:0 skip:14
hsw-gt2 total:165 pass:154 dwarn:0 dfail:0 fail:1 skip:10
ilk-hp8440p total:165 pass:116 dwarn:0 dfail:0 fail:1 skip:48
ivb-t430s total:165 pass:150 dwarn:0 dfail:0 fail:1 skip:14
skl-i5k-2 total:165 pass:150 dwarn:0 dfail:0 fail:0 skip:15
snb-dellxps total:165 pass:142 dwarn:0 dfail:0 fail:1 skip:22
snb-x220t total:165 pass:142 dwarn:0 dfail:0 fail:2 skip:21
Results at /archive/results/CI_IGT_test/Patchwork_1404/
a4474d338aa8156348cebe58a329a18c8560da1e drm-intel-nightly: 2016y-02m-15d-17h-27m-11s UTC integration manifest
44389d0b1a4c466436111dfc65738a9ca1e117de drm/i915/skl: SKL CDCLK change on modeset tracking VCO
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH V6] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (5 preceding siblings ...)
2016-02-16 9:45 ` ✗ Fi.CI.BAT: warning for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev4) Patchwork
@ 2016-02-16 17:19 ` clinton.a.taylor
2016-02-16 17:44 ` [PATCH V7] " clinton.a.taylor
` (8 subsequent siblings)
15 siblings, 0 replies; 39+ messages in thread
From: clinton.a.taylor @ 2016-02-16 17:19 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 102 +++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dp.c | 6 +-
drivers/gpu/drm/i915/intel_drv.h | 4 ++
5 files changed, 99 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..124cc4c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
+ unsigned int cdclk;
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640)
+ dev_priv->skl_vco_freq = 8100;
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+ cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+ } else {
+ cdclk = dev_priv->cdclk_freq;
}
- /* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ /* set CDCLK to the lowest frequency, Modeset follows */
+ skl_set_cdclk(dev_priv, cdclk);
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
- * As of now initialize with max cdclk till
- * we get dynamic cdclk support
- * */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9845,6 +9845,68 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ const int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+ if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
+ /* vco 8640 */
+ if (max_pixclk > 540000)
+ cdclk = 617140;
+ else if (max_pixclk > 432000)
+ cdclk = 540000;
+ else if (max_pixclk > 308570)
+ cdclk = 432000;
+ else
+ cdclk = 308570;
+ } else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ cdclk = 675000;
+ else if (max_pixclk > 450000)
+ cdclk = 540000;
+ else if (max_pixclk > 337500)
+ cdclk = 450000;
+ else
+ cdclk = 337500;
+ }
+
+ /*
+ * FIXME move the cdclk caclulation to
+ * compute_config() so we can fail gracegully.
+ */
+ if (cdclk > dev_priv->max_cdclk_freq) {
+ DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+ cdclk = dev_priv->max_cdclk_freq;
+ }
+
+ to_intel_atomic_state(state)->cdclk = cdclk;
+
+ return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+ struct drm_device *dev = old_state->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
+
+ /*
+ * FIXME disable/enable PLL should wrap set_cdclk()
+ */
+ skl_set_cdclk(dev_priv, req_cdclk);
+
+ dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -13248,9 +13310,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
* adjusted_mode bits in the crtc directly.
*/
if (dev_priv->display.modeset_calc_cdclk) {
+ if (!intel_state->cdclk_pll_vco)
+ intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
+
ret = dev_priv->display.modeset_calc_cdclk(state);
+ if (ret < 0)
+ return ret;
- if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ dev_priv->skl_vco_freq != intel_state->cdclk_pll_vco)
ret = intel_modeset_all_pipes(state);
if (ret < 0)
@@ -15002,6 +15070,11 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.modeset_commit_cdclk =
+ skl_modeset_commit_cdclk;
+ dev_priv->display.modeset_calc_cdclk =
+ skl_modeset_calc_cdclk;
}
switch (INTEL_INFO(dev)->gen) {
@@ -15725,7 +15798,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (crtc_state->base.active) {
dev_priv->active_crtcs |= 1 << crtc->pipe;
- if (IS_BROADWELL(dev_priv)) {
+ if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
+ IS_KABYLAKE(dev_priv)) {
pixclk = ilk_pipe_pixel_rate(crtc_state);
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04..afa21b6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1245,6 +1245,7 @@ static void
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
{
u32 ctrl1;
+ u32 vco = 8100;
memset(&pipe_config->dpll_hw_state, 0,
sizeof(pipe_config->dpll_hw_state));
@@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
SKL_DPLL0);
+ vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
SKL_DPLL0);
+ vco = 8640;
break;
-
}
+
+ to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 878172a..47936d4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -260,6 +260,9 @@ struct intel_atomic_state {
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
struct intel_wm_config wm_config;
+
+ /* SKL/KBL Only */
+ unsigned int cdclk_pll_vco;
};
struct intel_plane_state {
@@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH V7] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (6 preceding siblings ...)
2016-02-16 17:19 ` [PATCH V6] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
@ 2016-02-16 17:44 ` clinton.a.taylor
2016-02-17 16:56 ` Ville Syrjälä
2016-02-25 13:49 ` Ville Syrjälä
2016-02-16 17:48 ` ✓ Fi.CI.BAT: success for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev5) Patchwork
` (7 subsequent siblings)
15 siblings, 2 replies; 39+ messages in thread
From: clinton.a.taylor @ 2016-02-16 17:44 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 102 +++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dp.c | 6 +-
drivers/gpu/drm/i915/intel_drv.h | 4 ++
5 files changed, 99 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8216665..f65dd1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1822,7 +1822,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6d5b09f..285adab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9e2273b..e118ce0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
+ unsigned int cdclk;
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640)
+ dev_priv->skl_vco_freq = 8100;
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+ cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+ } else {
+ cdclk = dev_priv->cdclk_freq;
}
- /* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ /* set CDCLK to the lowest frequency, Modeset follows */
+ skl_set_cdclk(dev_priv, cdclk);
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
- * As of now initialize with max cdclk till
- * we get dynamic cdclk support
- * */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9845,6 +9845,68 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ const int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+ if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
+ /* vco 8640 */
+ if (max_pixclk > 540000)
+ cdclk = 617140;
+ else if (max_pixclk > 432000)
+ cdclk = 540000;
+ else if (max_pixclk > 308570)
+ cdclk = 432000;
+ else
+ cdclk = 308570;
+ } else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ cdclk = 675000;
+ else if (max_pixclk > 450000)
+ cdclk = 540000;
+ else if (max_pixclk > 337500)
+ cdclk = 450000;
+ else
+ cdclk = 337500;
+ }
+
+ /*
+ * FIXME move the cdclk caclulation to
+ * compute_config() so we can fail gracegully.
+ */
+ if (cdclk > dev_priv->max_cdclk_freq) {
+ DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+ cdclk = dev_priv->max_cdclk_freq;
+ }
+
+ to_intel_atomic_state(state)->cdclk = cdclk;
+
+ return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+ struct drm_device *dev = old_state->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
+
+ /*
+ * FIXME disable/enable PLL should wrap set_cdclk()
+ */
+ skl_set_cdclk(dev_priv, req_cdclk);
+
+ dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -13248,9 +13310,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
* adjusted_mode bits in the crtc directly.
*/
if (dev_priv->display.modeset_calc_cdclk) {
+ if (!intel_state->cdclk_pll_vco)
+ intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
+
ret = dev_priv->display.modeset_calc_cdclk(state);
+ if (ret < 0)
+ return ret;
- if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
ret = intel_modeset_all_pipes(state);
if (ret < 0)
@@ -15002,6 +15070,11 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.modeset_commit_cdclk =
+ skl_modeset_commit_cdclk;
+ dev_priv->display.modeset_calc_cdclk =
+ skl_modeset_calc_cdclk;
}
switch (INTEL_INFO(dev)->gen) {
@@ -15725,7 +15798,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (crtc_state->base.active) {
dev_priv->active_crtcs |= 1 << crtc->pipe;
- if (IS_BROADWELL(dev_priv)) {
+ if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
+ IS_KABYLAKE(dev_priv)) {
pixclk = ilk_pipe_pixel_rate(crtc_state);
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04..afa21b6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1245,6 +1245,7 @@ static void
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
{
u32 ctrl1;
+ u32 vco = 8100;
memset(&pipe_config->dpll_hw_state, 0,
sizeof(pipe_config->dpll_hw_state));
@@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
SKL_DPLL0);
+ vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
SKL_DPLL0);
+ vco = 8640;
break;
-
}
+
+ to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 878172a..47936d4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -260,6 +260,9 @@ struct intel_atomic_state {
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
struct intel_wm_config wm_config;
+
+ /* SKL/KBL Only */
+ unsigned int cdclk_pll_vco;
};
struct intel_plane_state {
@@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V7] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-16 17:44 ` [PATCH V7] " clinton.a.taylor
@ 2016-02-17 16:56 ` Ville Syrjälä
2016-02-25 13:49 ` Ville Syrjälä
1 sibling, 0 replies; 39+ messages in thread
From: Ville Syrjälä @ 2016-02-17 16:56 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Tue, Feb 16, 2016 at 09:44:55AM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Set cdclk based on the max required pixel clock based on VCO
> selected. Track boot vco instead of boot cdclk.
>
> The vco is now tracked at the atomic level and all CRTCs updated if
> the required vco is changed. Not tested with eDP v1.4 panels that
> require 8640 vco due to availability.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> V4: track target vco is atomic state. modeset all CRTCs if vco changes
> V5: rename atomic variable, cleaner if/else logic, use existing vco if
> encoder does not return a new vco value. check_patch.pl cleanup
> V6: simplify logic in intel_modeset_checks.
> V7: reorder an IF for readability and whitespace fix.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Looks pretty good to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 102 +++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp.c | 6 +-
> drivers/gpu/drm/i915/intel_drv.h | 4 ++
> 5 files changed, 99 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8216665..f65dd1a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int hpll_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6d5b09f..285adab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9e2273b..e118ce0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> + unsigned int cdclk;
>
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640)
> + dev_priv->skl_vco_freq = 8100;
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
> + } else {
> + cdclk = dev_priv->cdclk_freq;
> }
>
> - /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + /* set CDCLK to the lowest frequency, Modeset follows */
> + skl_set_cdclk(dev_priv, cdclk);
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9845,6 +9845,68 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + const int max_pixclk = ilk_max_pixel_rate(state);
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
> +
> + if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + } else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + to_intel_atomic_state(state)->cdclk = cdclk;
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
> +
> + /*
> + * FIXME disable/enable PLL should wrap set_cdclk()
> + */
> + skl_set_cdclk(dev_priv, req_cdclk);
> +
> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -13248,9 +13310,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> * adjusted_mode bits in the crtc directly.
> */
> if (dev_priv->display.modeset_calc_cdclk) {
> + if (!intel_state->cdclk_pll_vco)
> + intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> +
> ret = dev_priv->display.modeset_calc_cdclk(state);
> + if (ret < 0)
> + return ret;
>
> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> + if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
> ret = intel_modeset_all_pipes(state);
>
> if (ret < 0)
> @@ -15002,6 +15070,11 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
>
> switch (INTEL_INFO(dev)->gen) {
> @@ -15725,7 +15798,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> if (crtc_state->base.active) {
> dev_priv->active_crtcs |= 1 << crtc->pipe;
>
> - if (IS_BROADWELL(dev_priv)) {
> + if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
> + IS_KABYLAKE(dev_priv)) {
> pixclk = ilk_pipe_pixel_rate(crtc_state);
>
> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a073f04..afa21b6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1245,6 +1245,7 @@ static void
> skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> {
> u32 ctrl1;
> + u32 vco = 8100;
>
> memset(&pipe_config->dpll_hw_state, 0,
> sizeof(pipe_config->dpll_hw_state));
> @@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0);
> + vco = 8640;
> break;
> -
> }
> +
> + to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 878172a..47936d4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -260,6 +260,9 @@ struct intel_atomic_state {
>
> struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
> struct intel_wm_config wm_config;
> +
> + /* SKL/KBL Only */
> + unsigned int cdclk_pll_vco;
> };
>
> struct intel_plane_state {
> @@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V7] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-16 17:44 ` [PATCH V7] " clinton.a.taylor
2016-02-17 16:56 ` Ville Syrjälä
@ 2016-02-25 13:49 ` Ville Syrjälä
2016-02-25 23:52 ` Clint Taylor
1 sibling, 1 reply; 39+ messages in thread
From: Ville Syrjälä @ 2016-02-25 13:49 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Tue, Feb 16, 2016 at 09:44:55AM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Set cdclk based on the max required pixel clock based on VCO
> selected. Track boot vco instead of boot cdclk.
>
> The vco is now tracked at the atomic level and all CRTCs updated if
> the required vco is changed. Not tested with eDP v1.4 panels that
> require 8640 vco due to availability.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> V4: track target vco is atomic state. modeset all CRTCs if vco changes
> V5: rename atomic variable, cleaner if/else logic, use existing vco if
> encoder does not return a new vco value. check_patch.pl cleanup
> V6: simplify logic in intel_modeset_checks.
> V7: reorder an IF for readability and whitespace fix.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
I finally got around to actually trying this out myself, and I
noticed a few remaining problems:
- skl_modeset_calc_cdclk() should calculate dev_cdclk as well
dev_cdclk will be the same as cdclk, except when all pipes are
inactive, at which point dev_cdclk should be the minimum cdclk
- skl_modeset_commit_cdclk() should commit dev_cdclk, not cdclk
- modeset_update_crtc_power_domains() should check of the current
vco is different from the requested vco in addition to checking
the dev_cdclk vs. current cdclk, just like intel_modeset_checks()
does
So the current thing works, but it fails to drop the cdclk to minimum
when all pipes are inactive, and it also reprograms the cdclk every
time, I assume since it forgot to compute dev_cdclk and so that one
is probably left at 0 and so it never matches the current cdclk.
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 102 +++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp.c | 6 +-
> drivers/gpu/drm/i915/intel_drv.h | 4 ++
> 5 files changed, 99 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8216665..f65dd1a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int hpll_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6d5b09f..285adab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9e2273b..e118ce0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> + unsigned int cdclk;
>
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640)
> + dev_priv->skl_vco_freq = 8100;
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
> + } else {
> + cdclk = dev_priv->cdclk_freq;
> }
>
> - /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + /* set CDCLK to the lowest frequency, Modeset follows */
> + skl_set_cdclk(dev_priv, cdclk);
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9845,6 +9845,68 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + const int max_pixclk = ilk_max_pixel_rate(state);
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
> +
> + if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + } else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + to_intel_atomic_state(state)->cdclk = cdclk;
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
> +
> + /*
> + * FIXME disable/enable PLL should wrap set_cdclk()
> + */
> + skl_set_cdclk(dev_priv, req_cdclk);
> +
> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -13248,9 +13310,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> * adjusted_mode bits in the crtc directly.
> */
> if (dev_priv->display.modeset_calc_cdclk) {
> + if (!intel_state->cdclk_pll_vco)
> + intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> +
> ret = dev_priv->display.modeset_calc_cdclk(state);
> + if (ret < 0)
> + return ret;
>
> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> + if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
> ret = intel_modeset_all_pipes(state);
>
> if (ret < 0)
> @@ -15002,6 +15070,11 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
>
> switch (INTEL_INFO(dev)->gen) {
> @@ -15725,7 +15798,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> if (crtc_state->base.active) {
> dev_priv->active_crtcs |= 1 << crtc->pipe;
>
> - if (IS_BROADWELL(dev_priv)) {
> + if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
> + IS_KABYLAKE(dev_priv)) {
> pixclk = ilk_pipe_pixel_rate(crtc_state);
>
> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a073f04..afa21b6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1245,6 +1245,7 @@ static void
> skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> {
> u32 ctrl1;
> + u32 vco = 8100;
>
> memset(&pipe_config->dpll_hw_state, 0,
> sizeof(pipe_config->dpll_hw_state));
> @@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0);
> + vco = 8640;
> break;
> -
> }
> +
> + to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 878172a..47936d4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -260,6 +260,9 @@ struct intel_atomic_state {
>
> struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
> struct intel_wm_config wm_config;
> +
> + /* SKL/KBL Only */
> + unsigned int cdclk_pll_vco;
> };
>
> struct intel_plane_state {
> @@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V7] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-02-25 13:49 ` Ville Syrjälä
@ 2016-02-25 23:52 ` Clint Taylor
0 siblings, 0 replies; 39+ messages in thread
From: Clint Taylor @ 2016-02-25 23:52 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Intel-gfx
On 02/25/2016 05:49 AM, Ville Syrjälä wrote:
> On Tue, Feb 16, 2016 at 09:44:55AM -0800, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> Set cdclk based on the max required pixel clock based on VCO
>> selected. Track boot vco instead of boot cdclk.
>>
>> The vco is now tracked at the atomic level and all CRTCs updated if
>> the required vco is changed. Not tested with eDP v1.4 panels that
>> require 8640 vco due to availability.
>>
>> V1: initial version
>> V2: add vco tracking in intel_dp_compute_config(), rename
>> skl_boot_cdclk.
>> V3: rebase, V2 feedback not possible as encoders are not aware of
>> atomic.
>> V4: track target vco is atomic state. modeset all CRTCs if vco changes
>> V5: rename atomic variable, cleaner if/else logic, use existing vco if
>> encoder does not return a new vco value. check_patch.pl cleanup
>> V6: simplify logic in intel_modeset_checks.
>> V7: reorder an IF for readability and whitespace fix.
>>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
>
> I finally got around to actually trying this out myself, and I
> noticed a few remaining problems:
>
> - skl_modeset_calc_cdclk() should calculate dev_cdclk as well
> dev_cdclk will be the same as cdclk, except when all pipes are
> inactive, at which point dev_cdclk should be the minimum cdclk
That explains the relationship between dev_cdclk and cdclk.
> - skl_modeset_commit_cdclk() should commit dev_cdclk, not cdclk
correct, based on the above statement. New version on its way.
> - modeset_update_crtc_power_domains() should check of the current
> vco is different from the requested vco in addition to checking
> the dev_cdclk vs. current cdclk, just like intel_modeset_checks()
> does
modeset_update_crtc_power_domains() no longer exists. However it appears
the functionality has been moved to intel_atomic_commit(). I will add
the vco check into intel_atomic_commit()
>
> So the current thing works, but it fails to drop the cdclk to minimum
> when all pipes are inactive, and it also reprograms the cdclk every
> time, I assume since it forgot to compute dev_cdclk and so that one
> is probably left at 0 and so it never matches the current cdclk.
>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>> drivers/gpu/drm/i915/intel_display.c | 102 +++++++++++++++++++++++++++++-----
>> drivers/gpu/drm/i915/intel_dp.c | 6 +-
>> drivers/gpu/drm/i915/intel_drv.h | 4 ++
>> 5 files changed, 99 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 8216665..f65dd1a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1822,7 +1822,7 @@ struct drm_i915_private {
>> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>>
>> unsigned int fsb_freq, mem_freq, is_ddr3;
>> - unsigned int skl_boot_cdclk;
>> + unsigned int skl_vco_freq;
>> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
>> unsigned int max_dotclk_freq;
>> unsigned int hpll_freq;
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 6d5b09f..285adab 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2958,7 +2958,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
>> int cdclk_freq;
>>
>> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>> - dev_priv->skl_boot_cdclk = cdclk_freq;
>> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
>> if (skl_sanitize_cdclk(dev_priv))
>> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 9e2273b..e118ce0 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5663,7 +5663,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
>> return (freq - 1000) / 500;
>> }
>>
>> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
>> +unsigned int skl_cdclk_get_vco(unsigned int freq)
>> {
>> unsigned int i;
>>
>> @@ -5821,17 +5821,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>>
>> void skl_init_cdclk(struct drm_i915_private *dev_priv)
>> {
>> - unsigned int required_vco;
>> + unsigned int cdclk;
>>
>> /* DPLL0 not enabled (happens on early BIOS versions) */
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
>> /* enable DPLL0 */
>> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
>> - skl_dpll0_enable(dev_priv, required_vco);
>> + if (dev_priv->skl_vco_freq != 8640)
>> + dev_priv->skl_vco_freq = 8100;
>> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
>> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
>> + } else {
>> + cdclk = dev_priv->cdclk_freq;
>> }
>>
>> - /* set CDCLK to the frequency the BIOS chose */
>> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
>> + /* set CDCLK to the lowest frequency, Modeset follows */
>> + skl_set_cdclk(dev_priv, cdclk);
>>
>> /* enable DBUF power */
>> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
>> @@ -5847,7 +5851,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>> {
>> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
>> uint32_t cdctl = I915_READ(CDCLK_CTL);
>> - int freq = dev_priv->skl_boot_cdclk;
>> + int freq = dev_priv->cdclk_freq;
>>
>> /*
>> * check if the pre-os intialized the display
>> @@ -5871,11 +5875,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>> /* All well; nothing to sanitize */
>> return false;
>> sanitize:
>> - /*
>> - * As of now initialize with max cdclk till
>> - * we get dynamic cdclk support
>> - * */
>> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
>> +
>> skl_init_cdclk(dev_priv);
>>
>> /* we did have to sanitize */
>> @@ -9845,6 +9845,68 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> broadwell_set_cdclk(dev, req_cdclk);
>> }
>>
>> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(state->dev);
>> + const int max_pixclk = ilk_max_pixel_rate(state);
>> + int cdclk;
>> +
>> + /*
>> + * FIXME should also account for plane ratio
>> + * once 64bpp pixel formats are supported.
>> + */
>> +
>> + if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
>> + /* vco 8640 */
>> + if (max_pixclk > 540000)
>> + cdclk = 617140;
>> + else if (max_pixclk > 432000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 308570)
>> + cdclk = 432000;
>> + else
>> + cdclk = 308570;
>> + } else {
>> + /* VCO 8100 */
>> + if (max_pixclk > 540000)
>> + cdclk = 675000;
>> + else if (max_pixclk > 450000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 337500)
>> + cdclk = 450000;
>> + else
>> + cdclk = 337500;
>> + }
>> +
>> + /*
>> + * FIXME move the cdclk caclulation to
>> + * compute_config() so we can fail gracegully.
>> + */
>> + if (cdclk > dev_priv->max_cdclk_freq) {
>> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>> + cdclk, dev_priv->max_cdclk_freq);
>> + cdclk = dev_priv->max_cdclk_freq;
>> + }
>> +
>> + to_intel_atomic_state(state)->cdclk = cdclk;
>> +
>> + return 0;
>> +}
>> +
>> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> +{
>> + struct drm_device *dev = old_state->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
>> +
>> + /*
>> + * FIXME disable/enable PLL should wrap set_cdclk()
>> + */
>> + skl_set_cdclk(dev_priv, req_cdclk);
>> +
>> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
>> +}
>> +
>> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>> struct intel_crtc_state *crtc_state)
>> {
>> @@ -13248,9 +13310,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>> * adjusted_mode bits in the crtc directly.
>> */
>> if (dev_priv->display.modeset_calc_cdclk) {
>> + if (!intel_state->cdclk_pll_vco)
>> + intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
>> +
>> ret = dev_priv->display.modeset_calc_cdclk(state);
>> + if (ret < 0)
>> + return ret;
>>
>> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
>> + if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
>> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
>> ret = intel_modeset_all_pipes(state);
>>
>> if (ret < 0)
>> @@ -15002,6 +15070,11 @@ static void intel_init_display(struct drm_device *dev)
>> broxton_modeset_commit_cdclk;
>> dev_priv->display.modeset_calc_cdclk =
>> broxton_modeset_calc_cdclk;
>> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
>> + dev_priv->display.modeset_commit_cdclk =
>> + skl_modeset_commit_cdclk;
>> + dev_priv->display.modeset_calc_cdclk =
>> + skl_modeset_calc_cdclk;
>> }
>>
>> switch (INTEL_INFO(dev)->gen) {
>> @@ -15725,7 +15798,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>> if (crtc_state->base.active) {
>> dev_priv->active_crtcs |= 1 << crtc->pipe;
>>
>> - if (IS_BROADWELL(dev_priv)) {
>> + if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
>> + IS_KABYLAKE(dev_priv)) {
>> pixclk = ilk_pipe_pixel_rate(crtc_state);
>>
>> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index a073f04..afa21b6 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1245,6 +1245,7 @@ static void
>> skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>> {
>> u32 ctrl1;
>> + u32 vco = 8100;
>>
>> memset(&pipe_config->dpll_hw_state, 0,
>> sizeof(pipe_config->dpll_hw_state));
>> @@ -1277,13 +1278,16 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>> case 108000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
>> SKL_DPLL0);
>> + vco = 8640;
>> break;
>> case 216000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
>> SKL_DPLL0);
>> + vco = 8640;
>> break;
>> -
>> }
>> +
>> + to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
>> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 878172a..47936d4 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -260,6 +260,9 @@ struct intel_atomic_state {
>>
>> struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
>> struct intel_wm_config wm_config;
>> +
>> + /* SKL/KBL Only */
>> + unsigned int cdclk_pll_vco;
>> };
>>
>> struct intel_plane_state {
>> @@ -1191,6 +1194,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>> void skl_init_cdclk(struct drm_i915_private *dev_priv);
>> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
>> +unsigned int skl_cdclk_get_vco(unsigned int freq);
>> void skl_enable_dc6(struct drm_i915_private *dev_priv);
>> void skl_disable_dc6(struct drm_i915_private *dev_priv);
>> void intel_dp_get_m_n(struct intel_crtc *crtc,
>> --
>> 1.7.9.5
>
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^ permalink raw reply [flat|nested] 39+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev5)
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (7 preceding siblings ...)
2016-02-16 17:44 ` [PATCH V7] " clinton.a.taylor
@ 2016-02-16 17:48 ` Patchwork
2016-03-09 21:58 ` [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (6 subsequent siblings)
15 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2016-02-16 17:48 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Summary ==
Series 1609v5 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
http://patchwork.freedesktop.org/api/1.0/series/1609/revisions/5/mbox/
Test drv_module_reload_basic:
fail -> PASS (snb-dellxps)
Test kms_force_connector_basic:
Subgroup force-edid:
skip -> PASS (snb-x220t)
skip -> PASS (ivb-t430s)
Subgroup prune-stale-modes:
skip -> PASS (ivb-t430s)
Test pm_rpm:
Subgroup basic-rte:
pass -> DMESG-WARN (byt-nuc) UNSTABLE
bdw-ultra total:165 pass:152 dwarn:0 dfail:0 fail:0 skip:13
bsw-nuc-2 total:165 pass:134 dwarn:2 dfail:0 fail:0 skip:29
byt-nuc total:165 pass:138 dwarn:3 dfail:0 fail:0 skip:24
hsw-brixbox total:165 pass:148 dwarn:3 dfail:0 fail:0 skip:14
hsw-gt2 total:165 pass:151 dwarn:3 dfail:0 fail:1 skip:10
ivb-t430s total:165 pass:150 dwarn:0 dfail:0 fail:1 skip:14
snb-dellxps total:165 pass:140 dwarn:2 dfail:0 fail:1 skip:22
snb-x220t total:165 pass:142 dwarn:0 dfail:0 fail:2 skip:21
Results at /archive/results/CI_IGT_test/Patchwork_1416/
d6fbb21195050d1fcff27e5918114fb5ef66c137 drm-intel-nightly: 2016y-02m-16d-14h-37m-16s UTC integration manifest
182f54d45492eaed9cedf7ce496b20ffa81d5b62 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
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^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (8 preceding siblings ...)
2016-02-16 17:48 ` ✓ Fi.CI.BAT: success for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev5) Patchwork
@ 2016-03-09 21:58 ` clinton.a.taylor
2016-03-10 8:08 ` Maarten Lankhorst
2016-03-10 13:35 ` Ville Syrjälä
2016-03-10 7:00 ` ✗ Fi.CI.BAT: warning for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev7) Patchwork
` (5 subsequent siblings)
15 siblings, 2 replies; 39+ messages in thread
From: clinton.a.taylor @ 2016-03-09 21:58 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
V8: use dev_cdclk for tracking new cdclk during atomic
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 109 +++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dp.c | 5 ++
drivers/gpu/drm/i915/intel_drv.h | 5 ++
5 files changed, 105 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..83bb3fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1833,7 +1833,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..f628647 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3003,7 +3003,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62d36a7..10cdeb7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5811,7 +5811,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5969,17 +5969,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
+ unsigned int cdclk;
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640)
+ dev_priv->skl_vco_freq = 8100;
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+ cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+ } else {
+ cdclk = dev_priv->cdclk_freq;
}
- /* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ /* set CDCLK to the lowest frequency, Modeset follows */
+ skl_set_cdclk(dev_priv, cdclk);
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5995,7 +5999,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -6019,11 +6023,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
- * As of now initialize with max cdclk till
- * we get dynamic cdclk support
- * */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9963,6 +9963,71 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ const int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+ if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
+ /* vco 8640 */
+ if (max_pixclk > 540000)
+ cdclk = 617140;
+ else if (max_pixclk > 432000)
+ cdclk = 540000;
+ else if (max_pixclk > 308570)
+ cdclk = 432000;
+ else
+ cdclk = 308570;
+ } else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ cdclk = 675000;
+ else if (max_pixclk > 450000)
+ cdclk = 540000;
+ else if (max_pixclk > 337500)
+ cdclk = 450000;
+ else
+ cdclk = 337500;
+ }
+
+ /*
+ * FIXME move the cdclk caclulation to
+ * compute_config() so we can fail gracegully.
+ */
+ if (cdclk > dev_priv->max_cdclk_freq) {
+ DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+ cdclk = dev_priv->max_cdclk_freq;
+ }
+
+ intel_state->cdclk = intel_state->dev_cdclk = cdclk;
+ if (!intel_state->active_crtcs)
+ intel_state->dev_cdclk = 337500;
+
+ return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+ struct drm_device *dev = old_state->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
+
+ /*
+ * FIXME disable/enable PLL should wrap set_cdclk()
+ */
+ skl_set_cdclk(dev_priv, req_cdclk);
+
+ dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -13379,9 +13444,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
* adjusted_mode bits in the crtc directly.
*/
if (dev_priv->display.modeset_calc_cdclk) {
+ if (!intel_state->cdclk_pll_vco)
+ intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
+
ret = dev_priv->display.modeset_calc_cdclk(state);
+ if (ret < 0)
+ return ret;
- if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
ret = intel_modeset_all_pipes(state);
if (ret < 0)
@@ -13753,7 +13824,8 @@ static int intel_atomic_commit(struct drm_device *dev,
drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
if (dev_priv->display.modeset_commit_cdclk &&
- intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
dev_priv->display.modeset_commit_cdclk(state);
}
@@ -15231,8 +15303,12 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.modeset_commit_cdclk =
+ skl_modeset_commit_cdclk;
+ dev_priv->display.modeset_calc_cdclk =
+ skl_modeset_calc_cdclk;
}
-
switch (INTEL_INFO(dev)->gen) {
case 2:
dev_priv->display.queue_flip = intel_gen2_queue_flip;
@@ -15968,7 +16044,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (crtc_state->base.active) {
dev_priv->active_crtcs |= 1 << crtc->pipe;
- if (IS_BROADWELL(dev_priv)) {
+ if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
+ IS_KABYLAKE(dev_priv)) {
pixclk = ilk_pipe_pixel_rate(crtc_state);
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 351a8f3..4298f89 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1228,6 +1228,7 @@ static void
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
{
u32 ctrl1;
+ u32 vco = 8100;
memset(&pipe_config->dpll_hw_state, 0,
sizeof(pipe_config->dpll_hw_state));
@@ -1260,13 +1261,17 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
SKL_DPLL0);
+ vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
SKL_DPLL0);
+ vco = 8640;
break;
}
+
+ to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b2d66d..17721b2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -301,6 +301,10 @@ struct intel_atomic_state {
* don't bother calculating intermediate watermarks.
*/
bool skip_intermediate_wm;
+
+ /* SKL/KBL Only */
+ unsigned int cdclk_pll_vco;
+
};
struct intel_plane_state {
@@ -1247,6 +1251,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
--
1.7.9.5
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-03-09 21:58 ` [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
@ 2016-03-10 8:08 ` Maarten Lankhorst
2016-03-11 17:04 ` Clint Taylor
2016-03-10 13:35 ` Ville Syrjälä
1 sibling, 1 reply; 39+ messages in thread
From: Maarten Lankhorst @ 2016-03-10 8:08 UTC (permalink / raw)
To: clinton.a.taylor, Intel-gfx
Op 09-03-16 om 22:58 schreef clinton.a.taylor@intel.com:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
> to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
> is enabled when the cdclk is less then required. DP connected to DDI2
> and HPD on either port works correctly.
>
> Set cdclk based on the max required pixel clock based on VCO
> selected. Track boot vco instead of boot cdclk.
>
> The vco is now tracked at the atomic level and all CRTCs updated if
> the required vco is changed. Not tested with eDP v1.4 panels that
> require 8640 vco due to availability.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> V4: track target vco is atomic state. modeset all CRTCs if vco changes
> V5: rename atomic variable, cleaner if/else logic, use existing vco if
> encoder does not return a new vco value. check_patch.pl cleanup
> V6: simplify logic in intel_modeset_checks.
> V7: reorder an IF for readability and whitespace fix.
> V8: use dev_cdclk for tracking new cdclk during atomic
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>
Is the hang in the commit message introduced by this commit, or fixed by this commit?
~Maarten
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-03-10 8:08 ` Maarten Lankhorst
@ 2016-03-11 17:04 ` Clint Taylor
0 siblings, 0 replies; 39+ messages in thread
From: Clint Taylor @ 2016-03-11 17:04 UTC (permalink / raw)
To: Maarten Lankhorst, Intel-gfx
On 03/10/2016 12:08 AM, Maarten Lankhorst wrote:
> Op 09-03-16 om 22:58 schreef clinton.a.taylor@intel.com:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
>> to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
>> is enabled when the cdclk is less then required. DP connected to DDI2
>> and HPD on either port works correctly.
>>
>> Set cdclk based on the max required pixel clock based on VCO
>> selected. Track boot vco instead of boot cdclk.
>>
>> The vco is now tracked at the atomic level and all CRTCs updated if
>> the required vco is changed. Not tested with eDP v1.4 panels that
>> require 8640 vco due to availability.
>>
>> V1: initial version
>> V2: add vco tracking in intel_dp_compute_config(), rename
>> skl_boot_cdclk.
>> V3: rebase, V2 feedback not possible as encoders are not aware of
>> atomic.
>> V4: track target vco is atomic state. modeset all CRTCs if vco changes
>> V5: rename atomic variable, cleaner if/else logic, use existing vco if
>> encoder does not return a new vco value. check_patch.pl cleanup
>> V6: simplify logic in intel_modeset_checks.
>> V7: reorder an IF for readability and whitespace fix.
>> V8: use dev_cdclk for tracking new cdclk during atomic
>>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>>
> Is the hang in the commit message introduced by this commit, or fixed by this commit?
The hang is introduced by this commit. The hang isn't reproducible using
Arch Linux this appears to be an existing issue that is exposed for the
first time now that cdclk can change on SKL. This warning will only
affect ChromeOS users using drm-intel-nightly as the backport to
ChromeOS removes many of the atomic specific changes. It's also very
strange that the issue only affects the encoder attached to DDI1 and its
computation of dev_cdclk during a cold boot.
>
> ~Maarten
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-03-09 21:58 ` [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
2016-03-10 8:08 ` Maarten Lankhorst
@ 2016-03-10 13:35 ` Ville Syrjälä
1 sibling, 0 replies; 39+ messages in thread
From: Ville Syrjälä @ 2016-03-10 13:35 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Wed, Mar 09, 2016 at 01:58:39PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
> to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
> is enabled when the cdclk is less then required. DP connected to DDI2
> and HPD on either port works correctly.
>
> Set cdclk based on the max required pixel clock based on VCO
> selected. Track boot vco instead of boot cdclk.
>
> The vco is now tracked at the atomic level and all CRTCs updated if
> the required vco is changed. Not tested with eDP v1.4 panels that
> require 8640 vco due to availability.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> V4: track target vco is atomic state. modeset all CRTCs if vco changes
> V5: rename atomic variable, cleaner if/else logic, use existing vco if
> encoder does not return a new vco value. check_patch.pl cleanup
> V6: simplify logic in intel_modeset_checks.
> V7: reorder an IF for readability and whitespace fix.
> V8: use dev_cdclk for tracking new cdclk during atomic
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 109 +++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp.c | 5 ++
> drivers/gpu/drm/i915/intel_drv.h | 5 ++
> 5 files changed, 105 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f37ac12..83bb3fd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1833,7 +1833,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int rawclk_freq;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 62de9f4..f628647 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3003,7 +3003,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 62d36a7..10cdeb7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5811,7 +5811,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5969,17 +5969,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> + unsigned int cdclk;
>
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640)
> + dev_priv->skl_vco_freq = 8100;
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
> + } else {
> + cdclk = dev_priv->cdclk_freq;
> }
>
> - /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + /* set CDCLK to the lowest frequency, Modeset follows */
> + skl_set_cdclk(dev_priv, cdclk);
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5995,7 +5999,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -6019,11 +6023,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9963,6 +9963,71 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + const int max_pixclk = ilk_max_pixel_rate(state);
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
> +
> + if (to_intel_atomic_state(state)->cdclk_pll_vco == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + } else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + intel_state->cdclk = intel_state->dev_cdclk = cdclk;
> + if (!intel_state->active_crtcs)
> + intel_state->dev_cdclk = 337500;
That's not correct for the vco==8640 case.
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
This looks correct now.
> +
> + /*
> + * FIXME disable/enable PLL should wrap set_cdclk()
> + */
> + skl_set_cdclk(dev_priv, req_cdclk);
> +
> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -13379,9 +13444,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> * adjusted_mode bits in the crtc directly.
> */
> if (dev_priv->display.modeset_calc_cdclk) {
> + if (!intel_state->cdclk_pll_vco)
> + intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> +
> ret = dev_priv->display.modeset_calc_cdclk(state);
> + if (ret < 0)
> + return ret;
>
> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> + if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
> ret = intel_modeset_all_pipes(state);
>
> if (ret < 0)
> @@ -13753,7 +13824,8 @@ static int intel_atomic_commit(struct drm_device *dev,
> drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
>
> if (dev_priv->display.modeset_commit_cdclk &&
> - intel_state->dev_cdclk != dev_priv->cdclk_freq)
> + (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
> dev_priv->display.modeset_commit_cdclk(state);
as does this.
With the "no active pipes with vco==8640" case fixed this is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I still need to see if I could reproduce the hang somehow on my end. I
got another SKL now, but unfortunately it's a NUC so I can't actually
test the eDP part on it, and the my eDP SKL machine is too unstable to
do anything with multiple displays attached. I did excercise the eDP
vco stuff on it though, and with my extra patches on top even tested
the vco changing by progamming the wrong vco originally, and then
checked that it got corrected on the first modeset.
> }
>
> @@ -15231,8 +15303,12 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
> -
> switch (INTEL_INFO(dev)->gen) {
> case 2:
> dev_priv->display.queue_flip = intel_gen2_queue_flip;
> @@ -15968,7 +16044,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> if (crtc_state->base.active) {
> dev_priv->active_crtcs |= 1 << crtc->pipe;
>
> - if (IS_BROADWELL(dev_priv)) {
> + if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
> + IS_KABYLAKE(dev_priv)) {
> pixclk = ilk_pipe_pixel_rate(crtc_state);
>
> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 351a8f3..4298f89 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1228,6 +1228,7 @@ static void
> skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> {
> u32 ctrl1;
> + u32 vco = 8100;
>
> memset(&pipe_config->dpll_hw_state, 0,
> sizeof(pipe_config->dpll_hw_state));
> @@ -1260,13 +1261,17 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> SKL_DPLL0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
> SKL_DPLL0);
> + vco = 8640;
> break;
>
> }
> +
> + to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7b2d66d..17721b2 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -301,6 +301,10 @@ struct intel_atomic_state {
> * don't bother calculating intermediate watermarks.
> */
> bool skip_intermediate_wm;
> +
> + /* SKL/KBL Only */
> + unsigned int cdclk_pll_vco;
> +
> };
>
> struct intel_plane_state {
> @@ -1247,6 +1251,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev7)
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (9 preceding siblings ...)
2016-03-09 21:58 ` [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
@ 2016-03-10 7:00 ` Patchwork
2016-03-10 18:42 ` [PATCH V9] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (4 subsequent siblings)
15 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2016-03-10 7:00 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev7)
URL : https://patchwork.freedesktop.org/series/1609/
State : warning
== Summary ==
Series 1609v7 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
http://patchwork.freedesktop.org/api/1.0/series/1609/revisions/7/mbox/
Test drv_module_reload_basic:
dmesg-warn -> PASS (ilk-hp8440p)
Test gem_ringfill:
Subgroup basic-default-s3:
pass -> DMESG-WARN (bsw-nuc-2)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (hsw-brixbox)
pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS (bdw-ultra)
Subgroup basic-plain-flip:
dmesg-warn -> PASS (hsw-gt2)
pass -> DMESG-WARN (hsw-brixbox)
pass -> DMESG-WARN (bdw-ultra)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b-frame-sequence:
dmesg-warn -> PASS (hsw-brixbox)
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (bsw-nuc-2)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass -> DMESG-WARN (snb-dellxps)
Subgroup basic-rte:
pass -> DMESG-WARN (bsw-nuc-2)
bdw-nuci7 total:193 pass:181 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:193 pass:171 dwarn:1 dfail:0 fail:0 skip:21
bsw-nuc-2 total:193 pass:154 dwarn:2 dfail:0 fail:0 skip:37
byt-nuc total:193 pass:158 dwarn:0 dfail:0 fail:0 skip:35
hsw-brixbox total:193 pass:169 dwarn:2 dfail:0 fail:0 skip:22
hsw-gt2 total:193 pass:176 dwarn:0 dfail:0 fail:0 skip:17
ilk-hp8440p total:193 pass:129 dwarn:1 dfail:0 fail:0 skip:63
skl-i5k-2 total:193 pass:170 dwarn:0 dfail:0 fail:0 skip:23
skl-i7k-2 total:193 pass:170 dwarn:0 dfail:0 fail:0 skip:23
snb-dellxps total:193 pass:157 dwarn:2 dfail:0 fail:0 skip:34
Results at /archive/results/CI_IGT_test/Patchwork_1555/
ab403b26610034afe0e0c97d960782bad98b97d0 drm-intel-nightly: 2016y-03m-09d-09h-25m-31s UTC integration manifest
b2f7da9e8179722e64f851a2cd28cd0cc7b135e3 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH V9] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (10 preceding siblings ...)
2016-03-10 7:00 ` ✗ Fi.CI.BAT: warning for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev7) Patchwork
@ 2016-03-10 18:42 ` clinton.a.taylor
2016-03-10 21:43 ` [PATCH V10] " clinton.a.taylor
` (3 subsequent siblings)
15 siblings, 0 replies; 39+ messages in thread
From: clinton.a.taylor @ 2016-03-10 18:42 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
V8: use dev_cdclk for tracking new cdclk during atomic
V9: correctly handle vco 8640 when crtcs==0
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 113 +++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dp.c | 5 ++
drivers/gpu/drm/i915/intel_drv.h | 5 ++
5 files changed, 109 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..83bb3fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1833,7 +1833,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..f628647 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3003,7 +3003,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62d36a7..b8c7c5e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5811,7 +5811,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5969,17 +5969,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
+ unsigned int cdclk;
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640)
+ dev_priv->skl_vco_freq = 8100;
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+ cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+ } else {
+ cdclk = dev_priv->cdclk_freq;
}
- /* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ /* set CDCLK to the lowest frequency, Modeset follows */
+ skl_set_cdclk(dev_priv, cdclk);
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5995,7 +5999,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -6019,11 +6023,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
- * As of now initialize with max cdclk till
- * we get dynamic cdclk support
- * */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9963,6 +9963,75 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ const int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+ if (intel_state->cdclk_pll_vco == 8640) {
+ /* vco 8640 */
+ if (max_pixclk > 540000)
+ cdclk = 617140;
+ else if (max_pixclk > 432000)
+ cdclk = 540000;
+ else if (max_pixclk > 308570)
+ cdclk = 432000;
+ else
+ cdclk = 308570;
+ } else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ cdclk = 675000;
+ else if (max_pixclk > 450000)
+ cdclk = 540000;
+ else if (max_pixclk > 337500)
+ cdclk = 450000;
+ else
+ cdclk = 337500;
+ }
+
+ /*
+ * FIXME move the cdclk caclulation to
+ * compute_config() so we can fail gracegully.
+ */
+ if (cdclk > dev_priv->max_cdclk_freq) {
+ DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+ cdclk = dev_priv->max_cdclk_freq;
+ }
+
+ intel_state->cdclk = intel_state->dev_cdclk = cdclk;
+ if (!intel_state->active_crtcs) {
+ if (intel_state->cdclk_pll_vco == 8640)
+ intel_state->dev_cdclk = 308570;
+ else
+ intel_state->dev_cdclk = 337500;
+ }
+
+ return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+ struct drm_device *dev = old_state->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
+
+ /*
+ * FIXME disable/enable PLL should wrap set_cdclk()
+ */
+ skl_set_cdclk(dev_priv, req_cdclk);
+
+ dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -13379,9 +13448,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
* adjusted_mode bits in the crtc directly.
*/
if (dev_priv->display.modeset_calc_cdclk) {
+ if (!intel_state->cdclk_pll_vco)
+ intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
+
ret = dev_priv->display.modeset_calc_cdclk(state);
+ if (ret < 0)
+ return ret;
- if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
ret = intel_modeset_all_pipes(state);
if (ret < 0)
@@ -13753,7 +13828,8 @@ static int intel_atomic_commit(struct drm_device *dev,
drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
if (dev_priv->display.modeset_commit_cdclk &&
- intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
dev_priv->display.modeset_commit_cdclk(state);
}
@@ -15231,8 +15307,12 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.modeset_commit_cdclk =
+ skl_modeset_commit_cdclk;
+ dev_priv->display.modeset_calc_cdclk =
+ skl_modeset_calc_cdclk;
}
-
switch (INTEL_INFO(dev)->gen) {
case 2:
dev_priv->display.queue_flip = intel_gen2_queue_flip;
@@ -15968,7 +16048,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (crtc_state->base.active) {
dev_priv->active_crtcs |= 1 << crtc->pipe;
- if (IS_BROADWELL(dev_priv)) {
+ if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
+ IS_KABYLAKE(dev_priv)) {
pixclk = ilk_pipe_pixel_rate(crtc_state);
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 351a8f3..4298f89 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1228,6 +1228,7 @@ static void
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
{
u32 ctrl1;
+ u32 vco = 8100;
memset(&pipe_config->dpll_hw_state, 0,
sizeof(pipe_config->dpll_hw_state));
@@ -1260,13 +1261,17 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
SKL_DPLL0);
+ vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
SKL_DPLL0);
+ vco = 8640;
break;
}
+
+ to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b2d66d..17721b2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -301,6 +301,10 @@ struct intel_atomic_state {
* don't bother calculating intermediate watermarks.
*/
bool skip_intermediate_wm;
+
+ /* SKL/KBL Only */
+ unsigned int cdclk_pll_vco;
+
};
struct intel_plane_state {
@@ -1247,6 +1251,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH V10] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (11 preceding siblings ...)
2016-03-10 18:42 ` [PATCH V9] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
@ 2016-03-10 21:43 ` clinton.a.taylor
2016-03-11 7:09 ` ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev9) Patchwork
` (2 subsequent siblings)
15 siblings, 0 replies; 39+ messages in thread
From: clinton.a.taylor @ 2016-03-10 21:43 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
V8: use dev_cdclk for tracking new cdclk during atomic
V9: correctly handle vco 8640 when crtcs==0
V10: Clean up if else in crtcs==0
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 111 +++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dp.c | 5 ++
drivers/gpu/drm/i915/intel_drv.h | 5 ++
5 files changed, 107 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..83bb3fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1833,7 +1833,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..f628647 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3003,7 +3003,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62d36a7..6f2d429 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5811,7 +5811,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5969,17 +5969,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
+ unsigned int cdclk;
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640)
+ dev_priv->skl_vco_freq = 8100;
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+ cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+ } else {
+ cdclk = dev_priv->cdclk_freq;
}
- /* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ /* set CDCLK to the lowest frequency, Modeset follows */
+ skl_set_cdclk(dev_priv, cdclk);
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5995,7 +5999,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -6019,11 +6023,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
- * As of now initialize with max cdclk till
- * we get dynamic cdclk support
- * */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9963,6 +9963,73 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ const int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+ if (intel_state->cdclk_pll_vco == 8640) {
+ /* vco 8640 */
+ if (max_pixclk > 540000)
+ cdclk = 617140;
+ else if (max_pixclk > 432000)
+ cdclk = 540000;
+ else if (max_pixclk > 308570)
+ cdclk = 432000;
+ else
+ cdclk = 308570;
+ } else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ cdclk = 675000;
+ else if (max_pixclk > 450000)
+ cdclk = 540000;
+ else if (max_pixclk > 337500)
+ cdclk = 450000;
+ else
+ cdclk = 337500;
+ }
+
+ /*
+ * FIXME move the cdclk caclulation to
+ * compute_config() so we can fail gracegully.
+ */
+ if (cdclk > dev_priv->max_cdclk_freq) {
+ DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+ cdclk = dev_priv->max_cdclk_freq;
+ }
+
+ intel_state->cdclk = intel_state->dev_cdclk = cdclk;
+ if (!intel_state->active_crtcs)
+ intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
+ 308570 : 337500);
+
+
+ return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+ struct drm_device *dev = old_state->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
+
+ /*
+ * FIXME disable/enable PLL should wrap set_cdclk()
+ */
+ skl_set_cdclk(dev_priv, req_cdclk);
+
+ dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -13379,9 +13446,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
* adjusted_mode bits in the crtc directly.
*/
if (dev_priv->display.modeset_calc_cdclk) {
+ if (!intel_state->cdclk_pll_vco)
+ intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
+
ret = dev_priv->display.modeset_calc_cdclk(state);
+ if (ret < 0)
+ return ret;
- if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
ret = intel_modeset_all_pipes(state);
if (ret < 0)
@@ -13753,7 +13826,8 @@ static int intel_atomic_commit(struct drm_device *dev,
drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
if (dev_priv->display.modeset_commit_cdclk &&
- intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
dev_priv->display.modeset_commit_cdclk(state);
}
@@ -15231,8 +15305,12 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.modeset_commit_cdclk =
+ skl_modeset_commit_cdclk;
+ dev_priv->display.modeset_calc_cdclk =
+ skl_modeset_calc_cdclk;
}
-
switch (INTEL_INFO(dev)->gen) {
case 2:
dev_priv->display.queue_flip = intel_gen2_queue_flip;
@@ -15968,7 +16046,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (crtc_state->base.active) {
dev_priv->active_crtcs |= 1 << crtc->pipe;
- if (IS_BROADWELL(dev_priv)) {
+ if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
+ IS_KABYLAKE(dev_priv)) {
pixclk = ilk_pipe_pixel_rate(crtc_state);
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 351a8f3..4298f89 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1228,6 +1228,7 @@ static void
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
{
u32 ctrl1;
+ u32 vco = 8100;
memset(&pipe_config->dpll_hw_state, 0,
sizeof(pipe_config->dpll_hw_state));
@@ -1260,13 +1261,17 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
SKL_DPLL0);
+ vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
SKL_DPLL0);
+ vco = 8640;
break;
}
+
+ to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b2d66d..17721b2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -301,6 +301,10 @@ struct intel_atomic_state {
* don't bother calculating intermediate watermarks.
*/
bool skip_intermediate_wm;
+
+ /* SKL/KBL Only */
+ unsigned int cdclk_pll_vco;
+
};
struct intel_plane_state {
@@ -1247,6 +1251,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev9)
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (12 preceding siblings ...)
2016-03-10 21:43 ` [PATCH V10] " clinton.a.taylor
@ 2016-03-11 7:09 ` Patchwork
2016-03-15 21:34 ` [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
2016-03-16 10:01 ` ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev10) Patchwork
15 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2016-03-11 7:09 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev9)
URL : https://patchwork.freedesktop.org/series/1609/
State : failure
== Summary ==
Series 1609v9 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-03-10T21:31:49.256426 http://patchwork.freedesktop.org/api/1.0/series/1609/revisions/9/mbox/
Applying: drm/i915/skl: SKL CDCLK change on modeset tracking VCO
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_drv.h
M drivers/gpu/drm/i915/intel_ddi.c
M drivers/gpu/drm/i915/intel_display.c
M drivers/gpu/drm/i915/intel_dp.c
M drivers/gpu/drm/i915/intel_drv.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_drv.h
Auto-merging drivers/gpu/drm/i915/intel_dp.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_dp.c
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/intel_ddi.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_ddi.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Patch failed at 0001 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (13 preceding siblings ...)
2016-03-11 7:09 ` ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev9) Patchwork
@ 2016-03-15 21:34 ` clinton.a.taylor
2016-03-16 7:27 ` Daniel Vetter
2016-03-16 10:01 ` ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev10) Patchwork
15 siblings, 1 reply; 39+ messages in thread
From: clinton.a.taylor @ 2016-03-15 21:34 UTC (permalink / raw)
To: Intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.
V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
V8: use dev_cdclk for tracking new cdclk during atomic
V9: correctly handle vco 8640 when crtcs==0
V10: Clean up if else in crtcs==0
V11: Rebase for new intel_dpll_mgr.c
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 111 ++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dpll_mgr.c | 9 +--
drivers/gpu/drm/i915/intel_drv.h | 5 ++
4 files changed, 106 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80b14f1..bf87e62 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1759,7 +1759,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_boot_cdclk;
+ unsigned int skl_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ce55f0b..fc5268c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5584,7 +5584,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
return (freq - 1000) / 500;
}
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
{
unsigned int i;
@@ -5742,17 +5742,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
void skl_init_cdclk(struct drm_i915_private *dev_priv)
{
- unsigned int required_vco;
+ unsigned int cdclk;
/* DPLL0 not enabled (happens on early BIOS versions) */
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
/* enable DPLL0 */
- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
- skl_dpll0_enable(dev_priv, required_vco);
+ if (dev_priv->skl_vco_freq != 8640)
+ dev_priv->skl_vco_freq = 8100;
+ skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+ cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+ } else {
+ cdclk = dev_priv->cdclk_freq;
}
- /* set CDCLK to the frequency the BIOS chose */
- skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+ /* set CDCLK to the lowest frequency, Modeset follows */
+ skl_set_cdclk(dev_priv, cdclk);
/* enable DBUF power */
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5768,7 +5772,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
uint32_t cdctl = I915_READ(CDCLK_CTL);
- int freq = dev_priv->skl_boot_cdclk;
+ int freq = dev_priv->cdclk_freq;
/*
* check if the pre-os intialized the display
@@ -5792,11 +5796,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
/* All well; nothing to sanitize */
return false;
sanitize:
- /*
- * As of now initialize with max cdclk till
- * we get dynamic cdclk support
- * */
- dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
skl_init_cdclk(dev_priv);
/* we did have to sanitize */
@@ -9753,6 +9753,73 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
broadwell_set_cdclk(dev, req_cdclk);
}
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ const int max_pixclk = ilk_max_pixel_rate(state);
+ int cdclk;
+
+ /*
+ * FIXME should also account for plane ratio
+ * once 64bpp pixel formats are supported.
+ */
+
+ if (intel_state->cdclk_pll_vco == 8640) {
+ /* vco 8640 */
+ if (max_pixclk > 540000)
+ cdclk = 617140;
+ else if (max_pixclk > 432000)
+ cdclk = 540000;
+ else if (max_pixclk > 308570)
+ cdclk = 432000;
+ else
+ cdclk = 308570;
+ } else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ cdclk = 675000;
+ else if (max_pixclk > 450000)
+ cdclk = 540000;
+ else if (max_pixclk > 337500)
+ cdclk = 450000;
+ else
+ cdclk = 337500;
+ }
+
+ /*
+ * FIXME move the cdclk caclulation to
+ * compute_config() so we can fail gracegully.
+ */
+ if (cdclk > dev_priv->max_cdclk_freq) {
+ DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+ cdclk, dev_priv->max_cdclk_freq);
+ cdclk = dev_priv->max_cdclk_freq;
+ }
+
+ intel_state->cdclk = intel_state->dev_cdclk = cdclk;
+ if (!intel_state->active_crtcs)
+ intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
+ 308570 : 337500);
+
+
+ return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+ struct drm_device *dev = old_state->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
+
+ /*
+ * FIXME disable/enable PLL should wrap set_cdclk()
+ */
+ skl_set_cdclk(dev_priv, req_cdclk);
+
+ dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
+}
+
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -13214,9 +13281,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
* adjusted_mode bits in the crtc directly.
*/
if (dev_priv->display.modeset_calc_cdclk) {
+ if (!intel_state->cdclk_pll_vco)
+ intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
+
ret = dev_priv->display.modeset_calc_cdclk(state);
+ if (ret < 0)
+ return ret;
- if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
ret = intel_modeset_all_pipes(state);
if (ret < 0)
@@ -13588,7 +13661,8 @@ static int intel_atomic_commit(struct drm_device *dev,
drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
if (dev_priv->display.modeset_commit_cdclk &&
- intel_state->dev_cdclk != dev_priv->cdclk_freq)
+ (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+ intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
dev_priv->display.modeset_commit_cdclk(state);
}
@@ -14964,8 +15038,12 @@ static void intel_init_display(struct drm_device *dev)
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ dev_priv->display.modeset_commit_cdclk =
+ skl_modeset_commit_cdclk;
+ dev_priv->display.modeset_calc_cdclk =
+ skl_modeset_calc_cdclk;
}
-
switch (INTEL_INFO(dev)->gen) {
case 2:
dev_priv->display.queue_flip = intel_gen2_queue_flip;
@@ -15672,7 +15750,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (crtc_state->base.active) {
dev_priv->active_crtcs |= 1 << crtc->pipe;
- if (IS_BROADWELL(dev_priv)) {
+ if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
+ IS_KABYLAKE(dev_priv)) {
pixclk = ilk_pipe_pixel_rate(crtc_state);
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 4b636c4..a5642b1 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1183,6 +1183,7 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
struct intel_shared_dpll *pll;
uint32_t ctrl1, cfgcr1, cfgcr2;
int clock = crtc_state->port_clock;
+ uint32_t vco = 8100;
/*
* See comment in intel_dpll_hw_state to understand why we always use 0
@@ -1225,17 +1226,17 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
case 162000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
break;
- /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
- results in CDCLK change. Need to handle the change of CDCLK by
- disabling pipes and re-enabling them */
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
+ vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
+ vco = 8640;
break;
}
+ to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
cfgcr1 = cfgcr2 = 0;
} else {
return NULL;
@@ -1628,7 +1629,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- dev_priv->skl_boot_cdclk = cdclk_freq;
+ dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
if (skl_sanitize_cdclk(dev_priv))
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 02b3d22..b23b129 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -301,6 +301,10 @@ struct intel_atomic_state {
* don't bother calculating intermediate watermarks.
*/
bool skip_intermediate_wm;
+
+ /* SKL/KBL Only */
+ unsigned int cdclk_pll_vco;
+
};
struct intel_plane_state {
@@ -1239,6 +1243,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-03-15 21:34 ` [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
@ 2016-03-16 7:27 ` Daniel Vetter
2016-03-16 23:28 ` Clint Taylor
0 siblings, 1 reply; 39+ messages in thread
From: Daniel Vetter @ 2016-03-16 7:27 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx
On Tue, Mar 15, 2016 at 02:34:05PM -0700, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
> to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
> is enabled when the cdclk is less then required. DP connected to DDI2
> and HPD on either port works correctly.
So this patch hard-hangs machines?
>
> Set cdclk based on the max required pixel clock based on VCO
> selected. Track boot vco instead of boot cdclk.
>
> The vco is now tracked at the atomic level and all CRTCs updated if
> the required vco is changed. Not tested with eDP v1.4 panels that
> require 8640 vco due to availability.
>
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> V4: track target vco is atomic state. modeset all CRTCs if vco changes
> V5: rename atomic variable, cleaner if/else logic, use existing vco if
> encoder does not return a new vco value. check_patch.pl cleanup
> V6: simplify logic in intel_modeset_checks.
> V7: reorder an IF for readability and whitespace fix.
> V8: use dev_cdclk for tracking new cdclk during atomic
> V9: correctly handle vco 8640 when crtcs==0
> V10: Clean up if else in crtcs==0
> V11: Rebase for new intel_dpll_mgr.c
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Is the r-b from Ville really for v11?
-Daniel
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 111 ++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 9 +--
> drivers/gpu/drm/i915/intel_drv.h | 5 ++
> 4 files changed, 106 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 80b14f1..bf87e62 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1759,7 +1759,7 @@ struct drm_i915_private {
> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>
> unsigned int fsb_freq, mem_freq, is_ddr3;
> - unsigned int skl_boot_cdclk;
> + unsigned int skl_vco_freq;
> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> unsigned int max_dotclk_freq;
> unsigned int rawclk_freq;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ce55f0b..fc5268c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5584,7 +5584,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
> return (freq - 1000) / 500;
> }
>
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> {
> unsigned int i;
>
> @@ -5742,17 +5742,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - unsigned int required_vco;
> + unsigned int cdclk;
>
> /* DPLL0 not enabled (happens on early BIOS versions) */
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> /* enable DPLL0 */
> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> - skl_dpll0_enable(dev_priv, required_vco);
> + if (dev_priv->skl_vco_freq != 8640)
> + dev_priv->skl_vco_freq = 8100;
> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
> + } else {
> + cdclk = dev_priv->cdclk_freq;
> }
>
> - /* set CDCLK to the frequency the BIOS chose */
> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> + /* set CDCLK to the lowest frequency, Modeset follows */
> + skl_set_cdclk(dev_priv, cdclk);
>
> /* enable DBUF power */
> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5768,7 +5772,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->skl_boot_cdclk;
> + int freq = dev_priv->cdclk_freq;
>
> /*
> * check if the pre-os intialized the display
> @@ -5792,11 +5796,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
> - /*
> - * As of now initialize with max cdclk till
> - * we get dynamic cdclk support
> - * */
> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
> skl_init_cdclk(dev_priv);
>
> /* we did have to sanitize */
> @@ -9753,6 +9753,73 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> broadwell_set_cdclk(dev, req_cdclk);
> }
>
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + const int max_pixclk = ilk_max_pixel_rate(state);
> + int cdclk;
> +
> + /*
> + * FIXME should also account for plane ratio
> + * once 64bpp pixel formats are supported.
> + */
> +
> + if (intel_state->cdclk_pll_vco == 8640) {
> + /* vco 8640 */
> + if (max_pixclk > 540000)
> + cdclk = 617140;
> + else if (max_pixclk > 432000)
> + cdclk = 540000;
> + else if (max_pixclk > 308570)
> + cdclk = 432000;
> + else
> + cdclk = 308570;
> + } else {
> + /* VCO 8100 */
> + if (max_pixclk > 540000)
> + cdclk = 675000;
> + else if (max_pixclk > 450000)
> + cdclk = 540000;
> + else if (max_pixclk > 337500)
> + cdclk = 450000;
> + else
> + cdclk = 337500;
> + }
> +
> + /*
> + * FIXME move the cdclk caclulation to
> + * compute_config() so we can fail gracegully.
> + */
> + if (cdclk > dev_priv->max_cdclk_freq) {
> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> + cdclk, dev_priv->max_cdclk_freq);
> + cdclk = dev_priv->max_cdclk_freq;
> + }
> +
> + intel_state->cdclk = intel_state->dev_cdclk = cdclk;
> + if (!intel_state->active_crtcs)
> + intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
> + 308570 : 337500);
> +
> +
> + return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> + struct drm_device *dev = old_state->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
> +
> + /*
> + * FIXME disable/enable PLL should wrap set_cdclk()
> + */
> + skl_set_cdclk(dev_priv, req_cdclk);
> +
> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> +}
> +
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> @@ -13214,9 +13281,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> * adjusted_mode bits in the crtc directly.
> */
> if (dev_priv->display.modeset_calc_cdclk) {
> + if (!intel_state->cdclk_pll_vco)
> + intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> +
> ret = dev_priv->display.modeset_calc_cdclk(state);
> + if (ret < 0)
> + return ret;
>
> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> + if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
> ret = intel_modeset_all_pipes(state);
>
> if (ret < 0)
> @@ -13588,7 +13661,8 @@ static int intel_atomic_commit(struct drm_device *dev,
> drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
>
> if (dev_priv->display.modeset_commit_cdclk &&
> - intel_state->dev_cdclk != dev_priv->cdclk_freq)
> + (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
> dev_priv->display.modeset_commit_cdclk(state);
> }
>
> @@ -14964,8 +15038,12 @@ static void intel_init_display(struct drm_device *dev)
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + dev_priv->display.modeset_commit_cdclk =
> + skl_modeset_commit_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> + skl_modeset_calc_cdclk;
> }
> -
> switch (INTEL_INFO(dev)->gen) {
> case 2:
> dev_priv->display.queue_flip = intel_gen2_queue_flip;
> @@ -15672,7 +15750,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> if (crtc_state->base.active) {
> dev_priv->active_crtcs |= 1 << crtc->pipe;
>
> - if (IS_BROADWELL(dev_priv)) {
> + if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
> + IS_KABYLAKE(dev_priv)) {
> pixclk = ilk_pipe_pixel_rate(crtc_state);
>
> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 4b636c4..a5642b1 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1183,6 +1183,7 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
> struct intel_shared_dpll *pll;
> uint32_t ctrl1, cfgcr1, cfgcr2;
> int clock = crtc_state->port_clock;
> + uint32_t vco = 8100;
>
> /*
> * See comment in intel_dpll_hw_state to understand why we always use 0
> @@ -1225,17 +1226,17 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
> case 162000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
> break;
> - /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
> - results in CDCLK change. Need to handle the change of CDCLK by
> - disabling pipes and re-enabling them */
> case 108000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
> + vco = 8640;
> break;
> case 216000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
> + vco = 8640;
> break;
> }
>
> + to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
> cfgcr1 = cfgcr2 = 0;
> } else {
> return NULL;
> @@ -1628,7 +1629,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
> int cdclk_freq;
>
> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> - dev_priv->skl_boot_cdclk = cdclk_freq;
> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> if (skl_sanitize_cdclk(dev_priv))
> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 02b3d22..b23b129 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -301,6 +301,10 @@ struct intel_atomic_state {
> * don't bother calculating intermediate watermarks.
> */
> bool skip_intermediate_wm;
> +
> + /* SKL/KBL Only */
> + unsigned int cdclk_pll_vco;
> +
> };
>
> struct intel_plane_state {
> @@ -1239,6 +1243,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-03-16 7:27 ` Daniel Vetter
@ 2016-03-16 23:28 ` Clint Taylor
2016-03-17 21:18 ` Rodrigo Vivi
0 siblings, 1 reply; 39+ messages in thread
From: Clint Taylor @ 2016-03-16 23:28 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel-gfx
On 03/16/2016 12:27 AM, Daniel Vetter wrote:
> On Tue, Mar 15, 2016 at 02:34:05PM -0700, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
>> to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
>> is enabled when the cdclk is less then required. DP connected to DDI2
>> and HPD on either port works correctly.
>
> So this patch hard-hangs machines?
The hard-hang only occurs in developer mode ChromeOS with Coreboot (FSP
version < 1.9) using DP on DDI1 using a USB-C->DP converter.
We have not been able to reproduce this issue since updating to FSP 1.9
and was never able to replicate the issue with UEFI and SKL RVP. The
warning was added to the commit message during development to make
everyone aware of the issue.
>
>>
>> Set cdclk based on the max required pixel clock based on VCO
>> selected. Track boot vco instead of boot cdclk.
>>
>> The vco is now tracked at the atomic level and all CRTCs updated if
>> the required vco is changed. Not tested with eDP v1.4 panels that
>> require 8640 vco due to availability.
>>
>> V1: initial version
>> V2: add vco tracking in intel_dp_compute_config(), rename
>> skl_boot_cdclk.
>> V3: rebase, V2 feedback not possible as encoders are not aware of
>> atomic.
>> V4: track target vco is atomic state. modeset all CRTCs if vco changes
>> V5: rename atomic variable, cleaner if/else logic, use existing vco if
>> encoder does not return a new vco value. check_patch.pl cleanup
>> V6: simplify logic in intel_modeset_checks.
>> V7: reorder an IF for readability and whitespace fix.
>> V8: use dev_cdclk for tracking new cdclk during atomic
>> V9: correctly handle vco 8640 when crtcs==0
>> V10: Clean up if else in crtcs==0
>> V11: Rebase for new intel_dpll_mgr.c
>>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Is the r-b from Ville really for v11?
r-b is from patch V9 and only his V8 comment change and a rebase has
occured since. I will submit a V12 with the warning and r-b removed if
necessary.
> -Daniel
>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/intel_display.c | 111 ++++++++++++++++++++++++++++-----
>> drivers/gpu/drm/i915/intel_dpll_mgr.c | 9 +--
>> drivers/gpu/drm/i915/intel_drv.h | 5 ++
>> 4 files changed, 106 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 80b14f1..bf87e62 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1759,7 +1759,7 @@ struct drm_i915_private {
>> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>>
>> unsigned int fsb_freq, mem_freq, is_ddr3;
>> - unsigned int skl_boot_cdclk;
>> + unsigned int skl_vco_freq;
>> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
>> unsigned int max_dotclk_freq;
>> unsigned int rawclk_freq;
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index ce55f0b..fc5268c 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5584,7 +5584,7 @@ static unsigned int skl_cdclk_decimal(unsigned int freq)
>> return (freq - 1000) / 500;
>> }
>>
>> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
>> +unsigned int skl_cdclk_get_vco(unsigned int freq)
>> {
>> unsigned int i;
>>
>> @@ -5742,17 +5742,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>>
>> void skl_init_cdclk(struct drm_i915_private *dev_priv)
>> {
>> - unsigned int required_vco;
>> + unsigned int cdclk;
>>
>> /* DPLL0 not enabled (happens on early BIOS versions) */
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
>> /* enable DPLL0 */
>> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
>> - skl_dpll0_enable(dev_priv, required_vco);
>> + if (dev_priv->skl_vco_freq != 8640)
>> + dev_priv->skl_vco_freq = 8100;
>> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
>> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
>> + } else {
>> + cdclk = dev_priv->cdclk_freq;
>> }
>>
>> - /* set CDCLK to the frequency the BIOS chose */
>> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
>> + /* set CDCLK to the lowest frequency, Modeset follows */
>> + skl_set_cdclk(dev_priv, cdclk);
>>
>> /* enable DBUF power */
>> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
>> @@ -5768,7 +5772,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>> {
>> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
>> uint32_t cdctl = I915_READ(CDCLK_CTL);
>> - int freq = dev_priv->skl_boot_cdclk;
>> + int freq = dev_priv->cdclk_freq;
>>
>> /*
>> * check if the pre-os intialized the display
>> @@ -5792,11 +5796,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>> /* All well; nothing to sanitize */
>> return false;
>> sanitize:
>> - /*
>> - * As of now initialize with max cdclk till
>> - * we get dynamic cdclk support
>> - * */
>> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
>> +
>> skl_init_cdclk(dev_priv);
>>
>> /* we did have to sanitize */
>> @@ -9753,6 +9753,73 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> broadwell_set_cdclk(dev, req_cdclk);
>> }
>>
>> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> +{
>> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>> + struct drm_i915_private *dev_priv = to_i915(state->dev);
>> + const int max_pixclk = ilk_max_pixel_rate(state);
>> + int cdclk;
>> +
>> + /*
>> + * FIXME should also account for plane ratio
>> + * once 64bpp pixel formats are supported.
>> + */
>> +
>> + if (intel_state->cdclk_pll_vco == 8640) {
>> + /* vco 8640 */
>> + if (max_pixclk > 540000)
>> + cdclk = 617140;
>> + else if (max_pixclk > 432000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 308570)
>> + cdclk = 432000;
>> + else
>> + cdclk = 308570;
>> + } else {
>> + /* VCO 8100 */
>> + if (max_pixclk > 540000)
>> + cdclk = 675000;
>> + else if (max_pixclk > 450000)
>> + cdclk = 540000;
>> + else if (max_pixclk > 337500)
>> + cdclk = 450000;
>> + else
>> + cdclk = 337500;
>> + }
>> +
>> + /*
>> + * FIXME move the cdclk caclulation to
>> + * compute_config() so we can fail gracegully.
>> + */
>> + if (cdclk > dev_priv->max_cdclk_freq) {
>> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>> + cdclk, dev_priv->max_cdclk_freq);
>> + cdclk = dev_priv->max_cdclk_freq;
>> + }
>> +
>> + intel_state->cdclk = intel_state->dev_cdclk = cdclk;
>> + if (!intel_state->active_crtcs)
>> + intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
>> + 308570 : 337500);
>> +
>> +
>> + return 0;
>> +}
>> +
>> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> +{
>> + struct drm_device *dev = old_state->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
>> +
>> + /*
>> + * FIXME disable/enable PLL should wrap set_cdclk()
>> + */
>> + skl_set_cdclk(dev_priv, req_cdclk);
>> +
>> + dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
>> +}
>> +
>> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>> struct intel_crtc_state *crtc_state)
>> {
>> @@ -13214,9 +13281,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>> * adjusted_mode bits in the crtc directly.
>> */
>> if (dev_priv->display.modeset_calc_cdclk) {
>> + if (!intel_state->cdclk_pll_vco)
>> + intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
>> +
>> ret = dev_priv->display.modeset_calc_cdclk(state);
>> + if (ret < 0)
>> + return ret;
>>
>> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
>> + if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
>> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
>> ret = intel_modeset_all_pipes(state);
>>
>> if (ret < 0)
>> @@ -13588,7 +13661,8 @@ static int intel_atomic_commit(struct drm_device *dev,
>> drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
>>
>> if (dev_priv->display.modeset_commit_cdclk &&
>> - intel_state->dev_cdclk != dev_priv->cdclk_freq)
>> + (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
>> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
>> dev_priv->display.modeset_commit_cdclk(state);
>> }
>>
>> @@ -14964,8 +15038,12 @@ static void intel_init_display(struct drm_device *dev)
>> broxton_modeset_commit_cdclk;
>> dev_priv->display.modeset_calc_cdclk =
>> broxton_modeset_calc_cdclk;
>> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
>> + dev_priv->display.modeset_commit_cdclk =
>> + skl_modeset_commit_cdclk;
>> + dev_priv->display.modeset_calc_cdclk =
>> + skl_modeset_calc_cdclk;
>> }
>> -
>> switch (INTEL_INFO(dev)->gen) {
>> case 2:
>> dev_priv->display.queue_flip = intel_gen2_queue_flip;
>> @@ -15672,7 +15750,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>> if (crtc_state->base.active) {
>> dev_priv->active_crtcs |= 1 << crtc->pipe;
>>
>> - if (IS_BROADWELL(dev_priv)) {
>> + if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
>> + IS_KABYLAKE(dev_priv)) {
>> pixclk = ilk_pipe_pixel_rate(crtc_state);
>>
>> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
>> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> index 4b636c4..a5642b1 100644
>> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> @@ -1183,6 +1183,7 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>> struct intel_shared_dpll *pll;
>> uint32_t ctrl1, cfgcr1, cfgcr2;
>> int clock = crtc_state->port_clock;
>> + uint32_t vco = 8100;
>>
>> /*
>> * See comment in intel_dpll_hw_state to understand why we always use 0
>> @@ -1225,17 +1226,17 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>> case 162000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
>> break;
>> - /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
>> - results in CDCLK change. Need to handle the change of CDCLK by
>> - disabling pipes and re-enabling them */
>> case 108000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
>> + vco = 8640;
>> break;
>> case 216000:
>> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
>> + vco = 8640;
>> break;
>> }
>>
>> + to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
>> cfgcr1 = cfgcr2 = 0;
>> } else {
>> return NULL;
>> @@ -1628,7 +1629,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>> int cdclk_freq;
>>
>> cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>> - dev_priv->skl_boot_cdclk = cdclk_freq;
>> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
>> if (skl_sanitize_cdclk(dev_priv))
>> DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
>> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 02b3d22..b23b129 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -301,6 +301,10 @@ struct intel_atomic_state {
>> * don't bother calculating intermediate watermarks.
>> */
>> bool skip_intermediate_wm;
>> +
>> + /* SKL/KBL Only */
>> + unsigned int cdclk_pll_vco;
>> +
>> };
>>
>> struct intel_plane_state {
>> @@ -1239,6 +1243,7 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>> void skl_init_cdclk(struct drm_i915_private *dev_priv);
>> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
>> +unsigned int skl_cdclk_get_vco(unsigned int freq);
>> void skl_enable_dc6(struct drm_i915_private *dev_priv);
>> void skl_disable_dc6(struct drm_i915_private *dev_priv);
>> void intel_dp_get_m_n(struct intel_crtc *crtc,
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-03-16 23:28 ` Clint Taylor
@ 2016-03-17 21:18 ` Rodrigo Vivi
2016-03-17 21:38 ` Clint Taylor
0 siblings, 1 reply; 39+ messages in thread
From: Rodrigo Vivi @ 2016-03-17 21:18 UTC (permalink / raw)
To: Clint Taylor, Daniel Vetter, Ville Syrjälä; +Cc: Intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 15518 bytes --]
On Wed, Mar 16, 2016 at 4:33 PM Clint Taylor <clinton.a.taylor@intel.com>
wrote:
> On 03/16/2016 12:27 AM, Daniel Vetter wrote:
> > On Tue, Mar 15, 2016 at 02:34:05PM -0700, clinton.a.taylor@intel.com
> wrote:
> >> From: Clint Taylor <clinton.a.taylor@intel.com>
> >>
> >> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor
> connected
> >> to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
> >> is enabled when the cdclk is less then required. DP connected to DDI2
> >> and HPD on either port works correctly.
> >
> > So this patch hard-hangs machines?
>
> The hard-hang only occurs in developer mode ChromeOS with Coreboot (FSP
> version < 1.9) using DP on DDI1 using a USB-C->DP converter.
>
> We have not been able to reproduce this issue since updating to FSP 1.9
> and was never able to replicate the issue with UEFI and SKL RVP. The
> warning was added to the commit message during development to make
> everyone aware of the issue.
>
What does this developer mode has special/different?
What are the risks of getting this in other platform out there non chrome?
>
> >
> >>
> >> Set cdclk based on the max required pixel clock based on VCO
> >> selected. Track boot vco instead of boot cdclk.
> >>
> >> The vco is now tracked at the atomic level and all CRTCs updated if
> >> the required vco is changed. Not tested with eDP v1.4 panels that
> >> require 8640 vco due to availability.
> >>
> >> V1: initial version
> >> V2: add vco tracking in intel_dp_compute_config(), rename
> >> skl_boot_cdclk.
> >> V3: rebase, V2 feedback not possible as encoders are not aware of
> >> atomic.
> >> V4: track target vco is atomic state. modeset all CRTCs if vco changes
> >> V5: rename atomic variable, cleaner if/else logic, use existing vco if
> >> encoder does not return a new vco value. check_patch.pl cleanup
> >> V6: simplify logic in intel_modeset_checks.
> >> V7: reorder an IF for readability and whitespace fix.
> >> V8: use dev_cdclk for tracking new cdclk during atomic
> >> V9: correctly handle vco 8640 when crtcs==0
> >> V10: Clean up if else in crtcs==0
> >> V11: Rebase for new intel_dpll_mgr.c
> >>
> >> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Is the r-b from Ville really for v11?
>
> r-b is from patch V9 and only his V8 comment change and a rebase has
> occured since. I will submit a V12 with the warning and r-b removed if
> necessary.
>
Ville?
>
> > -Daniel
> >
> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> >> drivers/gpu/drm/i915/intel_display.c | 111
> ++++++++++++++++++++++++++++-----
> >> drivers/gpu/drm/i915/intel_dpll_mgr.c | 9 +--
> >> drivers/gpu/drm/i915/intel_drv.h | 5 ++
> >> 4 files changed, 106 insertions(+), 21 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> >> index 80b14f1..bf87e62 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1759,7 +1759,7 @@ struct drm_i915_private {
> >> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
> >>
> >> unsigned int fsb_freq, mem_freq, is_ddr3;
> >> - unsigned int skl_boot_cdclk;
> >> + unsigned int skl_vco_freq;
> >> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> >> unsigned int max_dotclk_freq;
> >> unsigned int rawclk_freq;
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> >> index ce55f0b..fc5268c 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -5584,7 +5584,7 @@ static unsigned int skl_cdclk_decimal(unsigned
> int freq)
> >> return (freq - 1000) / 500;
> >> }
> >>
> >> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> >> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> >> {
> >> unsigned int i;
> >>
> >> @@ -5742,17 +5742,21 @@ void skl_uninit_cdclk(struct drm_i915_private
> *dev_priv)
> >>
> >> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> >> {
> >> - unsigned int required_vco;
> >> + unsigned int cdclk;
> >>
> >> /* DPLL0 not enabled (happens on early BIOS versions) */
> >> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> >> /* enable DPLL0 */
> >> - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> >> - skl_dpll0_enable(dev_priv, required_vco);
> >> + if (dev_priv->skl_vco_freq != 8640)
> >> + dev_priv->skl_vco_freq = 8100;
> >> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> >> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 :
> 308570);
> >> + } else {
> >> + cdclk = dev_priv->cdclk_freq;
> >> }
> >>
> >> - /* set CDCLK to the frequency the BIOS chose */
> >> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> >> + /* set CDCLK to the lowest frequency, Modeset follows */
> >> + skl_set_cdclk(dev_priv, cdclk);
> >>
> >> /* enable DBUF power */
> >> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> >> @@ -5768,7 +5772,7 @@ int skl_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
> >> {
> >> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> >> uint32_t cdctl = I915_READ(CDCLK_CTL);
> >> - int freq = dev_priv->skl_boot_cdclk;
> >> + int freq = dev_priv->cdclk_freq;
> >>
> >> /*
> >> * check if the pre-os intialized the display
> >> @@ -5792,11 +5796,7 @@ int skl_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
> >> /* All well; nothing to sanitize */
> >> return false;
> >> sanitize:
> >> - /*
> >> - * As of now initialize with max cdclk till
> >> - * we get dynamic cdclk support
> >> - * */
> >> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> >> +
> >> skl_init_cdclk(dev_priv);
> >>
> >> /* we did have to sanitize */
> >> @@ -9753,6 +9753,73 @@ static void
> broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> >> broadwell_set_cdclk(dev, req_cdclk);
> >> }
> >>
> >> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> +{
> >> + struct intel_atomic_state *intel_state =
> to_intel_atomic_state(state);
> >> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> >> + const int max_pixclk = ilk_max_pixel_rate(state);
> >> + int cdclk;
> >> +
> >> + /*
> >> + * FIXME should also account for plane ratio
> >> + * once 64bpp pixel formats are supported.
> >> + */
> >> +
> >> + if (intel_state->cdclk_pll_vco == 8640) {
> >> + /* vco 8640 */
> >> + if (max_pixclk > 540000)
> >> + cdclk = 617140;
> >> + else if (max_pixclk > 432000)
> >> + cdclk = 540000;
> >> + else if (max_pixclk > 308570)
> >> + cdclk = 432000;
> >> + else
> >> + cdclk = 308570;
> >> + } else {
> >> + /* VCO 8100 */
> >> + if (max_pixclk > 540000)
> >> + cdclk = 675000;
> >> + else if (max_pixclk > 450000)
> >> + cdclk = 540000;
> >> + else if (max_pixclk > 337500)
> >> + cdclk = 450000;
> >> + else
> >> + cdclk = 337500;
> >> + }
> >> +
> >> + /*
> >> + * FIXME move the cdclk caclulation to
> >> + * compute_config() so we can fail gracegully.
> >> + */
> >> + if (cdclk > dev_priv->max_cdclk_freq) {
> >> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d
> kHz)\n",
> >> + cdclk, dev_priv->max_cdclk_freq);
> >> + cdclk = dev_priv->max_cdclk_freq;
> >> + }
> >> +
> >> + intel_state->cdclk = intel_state->dev_cdclk = cdclk;
> >> + if (!intel_state->active_crtcs)
> >> + intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco ==
> 8640) ?
> >> + 308570 : 337500);
> >> +
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static void skl_modeset_commit_cdclk(struct drm_atomic_state
> *old_state)
> >> +{
> >> + struct drm_device *dev = old_state->dev;
> >> + struct drm_i915_private *dev_priv = dev->dev_private;
> >> + unsigned int req_cdclk =
> to_intel_atomic_state(old_state)->dev_cdclk;
> >> +
> >> + /*
> >> + * FIXME disable/enable PLL should wrap set_cdclk()
> >> + */
> >> + skl_set_cdclk(dev_priv, req_cdclk);
> >> +
> >> + dev_priv->skl_vco_freq =
> to_intel_atomic_state(old_state)->cdclk_pll_vco;
> >> +}
> >> +
> >> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> >> struct intel_crtc_state *crtc_state)
> >> {
> >> @@ -13214,9 +13281,15 @@ static int intel_modeset_checks(struct
> drm_atomic_state *state)
> >> * adjusted_mode bits in the crtc directly.
> >> */
> >> if (dev_priv->display.modeset_calc_cdclk) {
> >> + if (!intel_state->cdclk_pll_vco)
> >> + intel_state->cdclk_pll_vco =
> dev_priv->skl_vco_freq;
> >> +
> >> ret = dev_priv->display.modeset_calc_cdclk(state);
> >> + if (ret < 0)
> >> + return ret;
> >>
> >> - if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> >> + if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> >> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
> >> ret = intel_modeset_all_pipes(state);
> >>
> >> if (ret < 0)
> >> @@ -13588,7 +13661,8 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> >> drm_atomic_helper_update_legacy_modeset_state(state->dev,
> state);
> >>
> >> if (dev_priv->display.modeset_commit_cdclk &&
> >> - intel_state->dev_cdclk != dev_priv->cdclk_freq)
> >> + (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> >> + intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
> >> dev_priv->display.modeset_commit_cdclk(state);
> >> }
> >>
> >> @@ -14964,8 +15038,12 @@ static void intel_init_display(struct
> drm_device *dev)
> >> broxton_modeset_commit_cdclk;
> >> dev_priv->display.modeset_calc_cdclk =
> >> broxton_modeset_calc_cdclk;
> >> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> >> + dev_priv->display.modeset_commit_cdclk =
> >> + skl_modeset_commit_cdclk;
> >> + dev_priv->display.modeset_calc_cdclk =
> >> + skl_modeset_calc_cdclk;
> >> }
> >> -
> >> switch (INTEL_INFO(dev)->gen) {
> >> case 2:
> >> dev_priv->display.queue_flip = intel_gen2_queue_flip;
> >> @@ -15672,7 +15750,8 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
> >> if (crtc_state->base.active) {
> >> dev_priv->active_crtcs |= 1 << crtc->pipe;
> >>
> >> - if (IS_BROADWELL(dev_priv)) {
> >> + if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)
> ||
> >> + IS_KABYLAKE(dev_priv)) {
> >> pixclk = ilk_pipe_pixel_rate(crtc_state);
> >>
> >> /* pixel rate mustn't exceed 95% of cdclk
> with IPS on BDW */
> >> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> index 4b636c4..a5642b1 100644
> >> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> @@ -1183,6 +1183,7 @@ skl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> >> struct intel_shared_dpll *pll;
> >> uint32_t ctrl1, cfgcr1, cfgcr2;
> >> int clock = crtc_state->port_clock;
> >> + uint32_t vco = 8100;
> >>
> >> /*
> >> * See comment in intel_dpll_hw_state to understand why we always
> use 0
> >> @@ -1225,17 +1226,17 @@ skl_get_dpll(struct intel_crtc *crtc, struct
> intel_crtc_state *crtc_state,
> >> case 162000:
> >> ctrl1 |=
> DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
> >> break;
> >> - /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is
> 8640 which
> >> - results in CDCLK change. Need to handle the change of
> CDCLK by
> >> - disabling pipes and re-enabling them */
> >> case 108000:
> >> ctrl1 |=
> DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
> >> + vco = 8640;
> >> break;
> >> case 216000:
> >> ctrl1 |=
> DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
> >> + vco = 8640;
> >> break;
> >> }
> >>
> >> +
> to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
> >> cfgcr1 = cfgcr2 = 0;
> >> } else {
> >> return NULL;
> >> @@ -1628,7 +1629,7 @@ static void intel_ddi_pll_init(struct drm_device
> *dev)
> >> int cdclk_freq;
> >>
> >> cdclk_freq =
> dev_priv->display.get_display_clock_speed(dev);
> >> - dev_priv->skl_boot_cdclk = cdclk_freq;
> >> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> >> if (skl_sanitize_cdclk(dev_priv))
> >> DRM_DEBUG_KMS("Sanitized cdclk programmed by
> pre-os\n");
> >> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> >> index 02b3d22..b23b129 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -301,6 +301,10 @@ struct intel_atomic_state {
> >> * don't bother calculating intermediate watermarks.
> >> */
> >> bool skip_intermediate_wm;
> >> +
> >> + /* SKL/KBL Only */
> >> + unsigned int cdclk_pll_vco;
> >> +
> >> };
> >>
> >> struct intel_plane_state {
> >> @@ -1239,6 +1243,7 @@ void bxt_disable_dc9(struct drm_i915_private
> *dev_priv);
> >> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> >> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> >> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> >> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> >> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> >> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> >> void intel_dp_get_m_n(struct intel_crtc *crtc,
> >> --
> >> 1.7.9.5
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO
2016-03-17 21:18 ` Rodrigo Vivi
@ 2016-03-17 21:38 ` Clint Taylor
0 siblings, 0 replies; 39+ messages in thread
From: Clint Taylor @ 2016-03-17 21:38 UTC (permalink / raw)
To: Rodrigo Vivi, Daniel Vetter, Ville Syrjälä; +Cc: Intel-gfx
On 03/17/2016 02:18 PM, Rodrigo Vivi wrote:
>
>
> On Wed, Mar 16, 2016 at 4:33 PM Clint Taylor <clinton.a.taylor@intel.com
> <mailto:clinton.a.taylor@intel.com>> wrote:
>
> On 03/16/2016 12:27 AM, Daniel Vetter wrote:
> > On Tue, Mar 15, 2016 at 02:34:05PM -0700,
> clinton.a.taylor@intel.com <mailto:clinton.a.taylor@intel.com> wrote:
> >> From: Clint Taylor <clinton.a.taylor@intel.com
> <mailto:clinton.a.taylor@intel.com>>
> >>
> >> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor
> connected
> >> to DDI1 the system will hard hang during a cold boot. Occurs
> when DDI1
> >> is enabled when the cdclk is less then required. DP connected to
> DDI2
> >> and HPD on either port works correctly.
> >
> > So this patch hard-hangs machines?
>
> The hard-hang only occurs in developer mode ChromeOS with Coreboot (FSP
> version < 1.9) using DP on DDI1 using a USB-C->DP converter.
>
> We have not been able to reproduce this issue since updating to FSP 1.9
> and was never able to replicate the issue with UEFI and SKL RVP. The
> warning was added to the commit message during development to make
> everyone aware of the issue.
>
>
> What does this developer mode has special/different?
Developer mode initializes eDP and display a boot message, the boot
message stays enabled until the kernel takes over. Normal mode does not
initialize the display hardware.
> What are the risks of getting this in other platform out there non chrome?
FSP 1.8 and earlier are only used in coreboot for ChromeOS in
non-shipping platforms. Of course there is a risk since cdclk is so
important to the display subsystem and we haven't found exactly why
cdclk was not being computed correctly for DDI1.
-Clint
>
>
> >
> >>
> >> Set cdclk based on the max required pixel clock based on VCO
> >> selected. Track boot vco instead of boot cdclk.
> >>
> >> The vco is now tracked at the atomic level and all CRTCs updated if
> >> the required vco is changed. Not tested with eDP v1.4 panels that
> >> require 8640 vco due to availability.
> >>
> >> V1: initial version
> >> V2: add vco tracking in intel_dp_compute_config(), rename
> >> skl_boot_cdclk.
> >> V3: rebase, V2 feedback not possible as encoders are not aware of
> >> atomic.
> >> V4: track target vco is atomic state. modeset all CRTCs if vco
> changes
> >> V5: rename atomic variable, cleaner if/else logic, use existing
> vco if
> >> encoder does not return a new vco value. check_patch.pl
> <http://check_patch.pl> cleanup
> >> V6: simplify logic in intel_modeset_checks.
> >> V7: reorder an IF for readability and whitespace fix.
> >> V8: use dev_cdclk for tracking new cdclk during atomic
> >> V9: correctly handle vco 8640 when crtcs==0
> >> V10: Clean up if else in crtcs==0
> >> V11: Rebase for new intel_dpll_mgr.c
> >>
> >> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com
> <mailto:ville.syrjala@linux.intel.com>>
> >
> > Is the r-b from Ville really for v11?
>
> r-b is from patch V9 and only his V8 comment change and a rebase has
> occured since. I will submit a V12 with the warning and r-b removed if
> necessary.
>
>
> Ville?
>
>
> > -Daniel
> >
> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com
> <mailto:clinton.a.taylor@intel.com>>
> >> ---
> >> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> >> drivers/gpu/drm/i915/intel_display.c | 111
> ++++++++++++++++++++++++++++-----
> >> drivers/gpu/drm/i915/intel_dpll_mgr.c | 9 +--
> >> drivers/gpu/drm/i915/intel_drv.h | 5 ++
> >> 4 files changed, 106 insertions(+), 21 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> >> index 80b14f1..bf87e62 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1759,7 +1759,7 @@ struct drm_i915_private {
> >> int num_fence_regs; /* 8 on pre-965, 16 otherwise */
> >>
> >> unsigned int fsb_freq, mem_freq, is_ddr3;
> >> - unsigned int skl_boot_cdclk;
> >> + unsigned int skl_vco_freq;
> >> unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> >> unsigned int max_dotclk_freq;
> >> unsigned int rawclk_freq;
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> >> index ce55f0b..fc5268c 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -5584,7 +5584,7 @@ static unsigned int
> skl_cdclk_decimal(unsigned int freq)
> >> return (freq - 1000) / 500;
> >> }
> >>
> >> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> >> +unsigned int skl_cdclk_get_vco(unsigned int freq)
> >> {
> >> unsigned int i;
> >>
> >> @@ -5742,17 +5742,21 @@ void skl_uninit_cdclk(struct
> drm_i915_private *dev_priv)
> >>
> >> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> >> {
> >> - unsigned int required_vco;
> >> + unsigned int cdclk;
> >>
> >> /* DPLL0 not enabled (happens on early BIOS versions) */
> >> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> >> /* enable DPLL0 */
> >> - required_vco =
> skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> >> - skl_dpll0_enable(dev_priv, required_vco);
> >> + if (dev_priv->skl_vco_freq != 8640)
> >> + dev_priv->skl_vco_freq = 8100;
> >> + skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> >> + cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500
> : 308570);
> >> + } else {
> >> + cdclk = dev_priv->cdclk_freq;
> >> }
> >>
> >> - /* set CDCLK to the frequency the BIOS chose */
> >> - skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> >> + /* set CDCLK to the lowest frequency, Modeset follows */
> >> + skl_set_cdclk(dev_priv, cdclk);
> >>
> >> /* enable DBUF power */
> >> I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> >> @@ -5768,7 +5772,7 @@ int skl_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
> >> {
> >> uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> >> uint32_t cdctl = I915_READ(CDCLK_CTL);
> >> - int freq = dev_priv->skl_boot_cdclk;
> >> + int freq = dev_priv->cdclk_freq;
> >>
> >> /*
> >> * check if the pre-os intialized the display
> >> @@ -5792,11 +5796,7 @@ int skl_sanitize_cdclk(struct
> drm_i915_private *dev_priv)
> >> /* All well; nothing to sanitize */
> >> return false;
> >> sanitize:
> >> - /*
> >> - * As of now initialize with max cdclk till
> >> - * we get dynamic cdclk support
> >> - * */
> >> - dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> >> +
> >> skl_init_cdclk(dev_priv);
> >>
> >> /* we did have to sanitize */
> >> @@ -9753,6 +9753,73 @@ static void
> broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> >> broadwell_set_cdclk(dev, req_cdclk);
> >> }
> >>
> >> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> +{
> >> + struct intel_atomic_state *intel_state =
> to_intel_atomic_state(state);
> >> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> >> + const int max_pixclk = ilk_max_pixel_rate(state);
> >> + int cdclk;
> >> +
> >> + /*
> >> + * FIXME should also account for plane ratio
> >> + * once 64bpp pixel formats are supported.
> >> + */
> >> +
> >> + if (intel_state->cdclk_pll_vco == 8640) {
> >> + /* vco 8640 */
> >> + if (max_pixclk > 540000)
> >> + cdclk = 617140;
> >> + else if (max_pixclk > 432000)
> >> + cdclk = 540000;
> >> + else if (max_pixclk > 308570)
> >> + cdclk = 432000;
> >> + else
> >> + cdclk = 308570;
> >> + } else {
> >> + /* VCO 8100 */
> >> + if (max_pixclk > 540000)
> >> + cdclk = 675000;
> >> + else if (max_pixclk > 450000)
> >> + cdclk = 540000;
> >> + else if (max_pixclk > 337500)
> >> + cdclk = 450000;
> >> + else
> >> + cdclk = 337500;
> >> + }
> >> +
> >> + /*
> >> + * FIXME move the cdclk caclulation to
> >> + * compute_config() so we can fail gracegully.
> >> + */
> >> + if (cdclk > dev_priv->max_cdclk_freq) {
> >> + DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d
> kHz)\n",
> >> + cdclk, dev_priv->max_cdclk_freq);
> >> + cdclk = dev_priv->max_cdclk_freq;
> >> + }
> >> +
> >> + intel_state->cdclk = intel_state->dev_cdclk = cdclk;
> >> + if (!intel_state->active_crtcs)
> >> + intel_state->dev_cdclk =
> ((intel_state->cdclk_pll_vco == 8640) ?
> >> + 308570 : 337500);
> >> +
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static void skl_modeset_commit_cdclk(struct drm_atomic_state
> *old_state)
> >> +{
> >> + struct drm_device *dev = old_state->dev;
> >> + struct drm_i915_private *dev_priv = dev->dev_private;
> >> + unsigned int req_cdclk =
> to_intel_atomic_state(old_state)->dev_cdclk;
> >> +
> >> + /*
> >> + * FIXME disable/enable PLL should wrap set_cdclk()
> >> + */
> >> + skl_set_cdclk(dev_priv, req_cdclk);
> >> +
> >> + dev_priv->skl_vco_freq =
> to_intel_atomic_state(old_state)->cdclk_pll_vco;
> >> +}
> >> +
> >> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> >> struct intel_crtc_state
> *crtc_state)
> >> {
> >> @@ -13214,9 +13281,15 @@ static int intel_modeset_checks(struct
> drm_atomic_state *state)
> >> * adjusted_mode bits in the crtc directly.
> >> */
> >> if (dev_priv->display.modeset_calc_cdclk) {
> >> + if (!intel_state->cdclk_pll_vco)
> >> + intel_state->cdclk_pll_vco =
> dev_priv->skl_vco_freq;
> >> +
> >> ret = dev_priv->display.modeset_calc_cdclk(state);
> >> + if (ret < 0)
> >> + return ret;
> >>
> >> - if (!ret && intel_state->dev_cdclk !=
> dev_priv->cdclk_freq)
> >> + if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> >> + intel_state->cdclk_pll_vco !=
> dev_priv->skl_vco_freq)
> >> ret = intel_modeset_all_pipes(state);
> >>
> >> if (ret < 0)
> >> @@ -13588,7 +13661,8 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> >>
> drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
> >>
> >> if (dev_priv->display.modeset_commit_cdclk &&
> >> - intel_state->dev_cdclk != dev_priv->cdclk_freq)
> >> + (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> >> + intel_state->cdclk_pll_vco !=
> dev_priv->skl_vco_freq))
> >> dev_priv->display.modeset_commit_cdclk(state);
> >> }
> >>
> >> @@ -14964,8 +15038,12 @@ static void intel_init_display(struct
> drm_device *dev)
> >> broxton_modeset_commit_cdclk;
> >> dev_priv->display.modeset_calc_cdclk =
> >> broxton_modeset_calc_cdclk;
> >> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> >> + dev_priv->display.modeset_commit_cdclk =
> >> + skl_modeset_commit_cdclk;
> >> + dev_priv->display.modeset_calc_cdclk =
> >> + skl_modeset_calc_cdclk;
> >> }
> >> -
> >> switch (INTEL_INFO(dev)->gen) {
> >> case 2:
> >> dev_priv->display.queue_flip = intel_gen2_queue_flip;
> >> @@ -15672,7 +15750,8 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
> >> if (crtc_state->base.active) {
> >> dev_priv->active_crtcs |= 1 << crtc->pipe;
> >>
> >> - if (IS_BROADWELL(dev_priv)) {
> >> + if (IS_BROADWELL(dev_priv) ||
> IS_SKYLAKE(dev_priv) ||
> >> + IS_KABYLAKE(dev_priv)) {
> >> pixclk =
> ilk_pipe_pixel_rate(crtc_state);
> >>
> >> /* pixel rate mustn't exceed 95% of
> cdclk with IPS on BDW */
> >> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> index 4b636c4..a5642b1 100644
> >> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> >> @@ -1183,6 +1183,7 @@ skl_get_dpll(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state,
> >> struct intel_shared_dpll *pll;
> >> uint32_t ctrl1, cfgcr1, cfgcr2;
> >> int clock = crtc_state->port_clock;
> >> + uint32_t vco = 8100;
> >>
> >> /*
> >> * See comment in intel_dpll_hw_state to understand why we
> always use 0
> >> @@ -1225,17 +1226,17 @@ skl_get_dpll(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state,
> >> case 162000:
> >> ctrl1 |=
> DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
> >> break;
> >> - /* TBD: For DP link rates 2.16 GHz and 4.32 GHz,
> VCO is 8640 which
> >> - results in CDCLK change. Need to handle the change
> of CDCLK by
> >> - disabling pipes and re-enabling them */
> >> case 108000:
> >> ctrl1 |=
> DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
> >> + vco = 8640;
> >> break;
> >> case 216000:
> >> ctrl1 |=
> DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
> >> + vco = 8640;
> >> break;
> >> }
> >>
> >> +
> to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
> >> cfgcr1 = cfgcr2 = 0;
> >> } else {
> >> return NULL;
> >> @@ -1628,7 +1629,7 @@ static void intel_ddi_pll_init(struct
> drm_device *dev)
> >> int cdclk_freq;
> >>
> >> cdclk_freq =
> dev_priv->display.get_display_clock_speed(dev);
> >> - dev_priv->skl_boot_cdclk = cdclk_freq;
> >> + dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> >> if (skl_sanitize_cdclk(dev_priv))
> >> DRM_DEBUG_KMS("Sanitized cdclk programmed
> by pre-os\n");
> >> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> >> index 02b3d22..b23b129 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -301,6 +301,10 @@ struct intel_atomic_state {
> >> * don't bother calculating intermediate watermarks.
> >> */
> >> bool skip_intermediate_wm;
> >> +
> >> + /* SKL/KBL Only */
> >> + unsigned int cdclk_pll_vco;
> >> +
> >> };
> >>
> >> struct intel_plane_state {
> >> @@ -1239,6 +1243,7 @@ void bxt_disable_dc9(struct
> drm_i915_private *dev_priv);
> >> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> >> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> >> void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> >> +unsigned int skl_cdclk_get_vco(unsigned int freq);
> >> void skl_enable_dc6(struct drm_i915_private *dev_priv);
> >> void skl_disable_dc6(struct drm_i915_private *dev_priv);
> >> void intel_dp_get_m_n(struct intel_crtc *crtc,
> >> --
> >> 1.7.9.5
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> <mailto:Intel-gfx@lists.freedesktop.org>
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org <mailto:Intel-gfx@lists.freedesktop.org>
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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^ permalink raw reply [flat|nested] 39+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev10)
2015-12-09 0:15 [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
` (14 preceding siblings ...)
2016-03-15 21:34 ` [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO clinton.a.taylor
@ 2016-03-16 10:01 ` Patchwork
15 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2016-03-16 10:01 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev10)
URL : https://patchwork.freedesktop.org/series/1609/
State : failure
== Summary ==
Series 1609v10 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
http://patchwork.freedesktop.org/api/1.0/series/1609/revisions/10/mbox/
Test drv_module_reload_basic:
skip -> PASS (bdw-nuci7)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass -> DMESG-WARN (hsw-gt2)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (skl-nuci5)
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-WARN (bsw-nuc-2)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass -> DMESG-WARN (snb-dellxps)
Subgroup basic-rte:
dmesg-warn -> PASS (snb-dellxps)
bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:194 pass:156 dwarn:1 dfail:0 fail:0 skip:37
byt-nuc total:194 pass:155 dwarn:4 dfail:0 fail:0 skip:35
hsw-gt2 total:194 pass:176 dwarn:1 dfail:0 fail:0 skip:17
ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip:11
snb-dellxps total:194 pass:159 dwarn:1 dfail:0 fail:0 skip:34
snb-x220t total:194 pass:159 dwarn:1 dfail:0 fail:1 skip:33
Results at /archive/results/CI_IGT_test/Patchwork_1609/
fc881ebd9c3c26919c7d1113f8bf7014e1a05563 drm-intel-nightly: 2016y-03m-15d-13h-10m-41s UTC integration manifest
31aa1232a835a2b9d867f846acd8d73cc3340789 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
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^ permalink raw reply [flat|nested] 39+ messages in thread