All of lore.kernel.org
 help / color / mirror / Atom feed
diff for duplicates of <56C2C534.30704@de.bosch.com>

diff --git a/a/1.txt b/N1/1.txt
index 3dffb50..6c2c4cc 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -21,7 +21,7 @@ On 15.02.2016 21:38, Geert Uytterhoeven wrote:
 >   		cache-level = <2>;
 >   	};
 >
-> +	L2_CA53: cache-controller@1 {
+> +	L2_CA53: cache-controller at 1 {
 > +		compatible = "cache";
 > +		cache-unified;
 > +		cache-level = <2>;
diff --git a/a/content_digest b/N1/content_digest
index 7fb6d3c..864cb52 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,15 +1,9 @@
  "ref\01455568715-20880-1-git-send-email-geert+renesas@glider.be\0"
  "ref\01455568715-20880-8-git-send-email-geert+renesas@glider.be\0"
- "From\0Dirk Behme <dirk.behme@de.bosch.com>\0"
- "Subject\0Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node\0"
+ "From\0dirk.behme@de.bosch.com (Dirk Behme)\0"
+ "Subject\0[PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node\0"
  "Date\0Tue, 16 Feb 2016 07:44:04 +0100\0"
- "To\0Geert Uytterhoeven <geert+renesas@glider.be>"
-  Simon Horman <horms@verge.net.au>
- " Magnus Damm <magnus.damm@gmail.com>\0"
- "Cc\0Sudeep Holla <sudeep.holla@arm.com>"
-  <linux-renesas-soc@vger.kernel.org>
-  <devicetree@vger.kernel.org>
- " <linux-arm-kernel@lists.infradead.org>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On 15.02.2016 21:38, Geert Uytterhoeven wrote:\n"
@@ -35,7 +29,7 @@
  ">   \t\tcache-level = <2>;\n"
  ">   \t};\n"
  ">\n"
- "> +\tL2_CA53: cache-controller@1 {\n"
+ "> +\tL2_CA53: cache-controller at 1 {\n"
  "> +\t\tcompatible = \"cache\";\n"
  "> +\t\tcache-unified;\n"
  "> +\t\tcache-level = <2>;\n"
@@ -56,4 +50,4 @@
  "\n"
  Dirk
 
-5f3fca20a1e2b197705bcb99cc8e753e7e39817c932f060a40afcf90e67a8eed
+980790f9c2d0ddfadb0f80e7fb2f485731ca09e28b82ee3f34f0a75a5f04daef

diff --git a/a/1.txt b/N2/1.txt
index 3dffb50..a00f317 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -4,7 +4,7 @@ On 15.02.2016 21:38, Geert Uytterhoeven wrote:
 > The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
 > 32 KiB x 16 ways).
 >
-> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
 > ---
 > v3:
 >    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
@@ -41,3 +41,9 @@ want to add the unused cache-unified and cache-level, then, too.
 Best regards
 
 Dirk
+
+
+--
+To unsubscribe from this list: send the line "unsubscribe devicetree" in
+the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
diff --git a/a/content_digest b/N2/content_digest
index 7fb6d3c..853d046 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -1,15 +1,16 @@
  "ref\01455568715-20880-1-git-send-email-geert+renesas@glider.be\0"
  "ref\01455568715-20880-8-git-send-email-geert+renesas@glider.be\0"
- "From\0Dirk Behme <dirk.behme@de.bosch.com>\0"
+ "ref\01455568715-20880-8-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org\0"
+ "From\0Dirk Behme <dirk.behme-V5te9oGctAVWk0Htik3J/w@public.gmane.org>\0"
  "Subject\0Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node\0"
  "Date\0Tue, 16 Feb 2016 07:44:04 +0100\0"
- "To\0Geert Uytterhoeven <geert+renesas@glider.be>"
-  Simon Horman <horms@verge.net.au>
- " Magnus Damm <magnus.damm@gmail.com>\0"
- "Cc\0Sudeep Holla <sudeep.holla@arm.com>"
-  <linux-renesas-soc@vger.kernel.org>
-  <devicetree@vger.kernel.org>
- " <linux-arm-kernel@lists.infradead.org>\0"
+ "To\0Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>"
+  Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
+ " Magnus Damm <magnus.damm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0"
+ "Cc\0Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>"
+  linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+  devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+ " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0"
  "\00:1\0"
  "b\0"
  "On 15.02.2016 21:38, Geert Uytterhoeven wrote:\n"
@@ -18,7 +19,7 @@
  "> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as\n"
  "> 32 KiB x 16 ways).\n"
  ">\n"
- "> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>\n"
+ "> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>\n"
  "> ---\n"
  "> v3:\n"
  ">    - Remaining part of \"[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2\n"
@@ -54,6 +55,12 @@
  "\n"
  "Best regards\n"
  "\n"
- Dirk
+ "Dirk\n"
+ "\n"
+ "\n"
+ "--\n"
+ "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n"
+ "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n"
+ More majordomo info at  http://vger.kernel.org/majordomo-info.html
 
-5f3fca20a1e2b197705bcb99cc8e753e7e39817c932f060a40afcf90e67a8eed
+578d640be2285e72768cff13314f6df1129362891a2ac83c7840696fe6c30153

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.