* Re: [PATCH] drm/i915/gen9: Set value of Indirect Context Offset based on gen version
2016-02-19 14:05 [PATCH] drm/i915/gen9: Set value of Indirect Context Offset based on gen version Michel Thierry
@ 2016-02-19 14:25 ` Chris Wilson
2016-02-19 14:58 ` [PATCH v2] " Michel Thierry
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2016-02-19 14:25 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
On Fri, Feb 19, 2016 at 02:05:11PM +0000, Michel Thierry wrote:
> The cache line offset for the Indirect CS context (0x21C8) varies from gen
> to gen.
>
> Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 5c0bf02..e707937 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -226,7 +226,8 @@ enum {
> FAULT_AND_CONTINUE /* Unsupported */
> };
> #define GEN8_CTX_ID_SHIFT 32
> -#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
> +#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
> +#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
>
> static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
> static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
> @@ -2330,13 +2331,29 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
> if (ring->wa_ctx.obj) {
> struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
> uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
> + uint32_t indirect_ctx_offset;
>
> reg_state[CTX_RCS_INDIRECT_CTX+1] =
> (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
> (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
>
> + switch (INTEL_INFO(ring->dev)->gen) {
> + default:
> + DRM_ERROR("Unknown indirect ctx offset for GEN%d\n",
> + INTEL_INFO(ring->dev)->gen);
> + /* fall through */
MISSING_CASE()
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2] drm/i915/gen9: Set value of Indirect Context Offset based on gen version
2016-02-19 14:05 [PATCH] drm/i915/gen9: Set value of Indirect Context Offset based on gen version Michel Thierry
2016-02-19 14:25 ` Chris Wilson
@ 2016-02-19 14:58 ` Michel Thierry
2016-02-19 15:19 ` Arun Siluvery
2016-02-19 16:42 ` ✗ Fi.CI.BAT: failure for drm/i915/gen9: Set value of Indirect Context Offset based on gen version (rev2) Patchwork
2016-02-22 10:14 ` [PATCH v3] drm/i915/gen9: Set value of Indirect Context Offset based on gen version Michel Thierry
3 siblings, 1 reply; 6+ messages in thread
From: Michel Thierry @ 2016-02-19 14:58 UTC (permalink / raw)
To: intel-gfx
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
v2: Move it into a function (Arun), use MISSING_CASE (Chris)
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5c0bf02..b1f2886 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -226,7 +226,8 @@ enum {
FAULT_AND_CONTINUE /* Unsupported */
};
#define GEN8_CTX_ID_SHIFT 32
-#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
+#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
+#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
@@ -2264,6 +2265,27 @@ make_rpcs(struct drm_device *dev)
return rpcs;
}
+static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *ring)
+{
+ u32 indirect_ctx_offset;
+
+ switch (INTEL_INFO(ring->dev)->gen) {
+ default:
+ MISSING_CASE(INTEL_INFO(ring->dev)->gen);
+ /* fall through */
+ case 9:
+ indirect_ctx_offset =
+ GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
+ break;
+ case 8:
+ indirect_ctx_offset =
+ GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
+ break;
+ }
+
+ return indirect_ctx_offset;
+}
+
static int
populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
@@ -2336,7 +2358,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
- CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
+ intel_lr_indirect_ctx_offset(ring) << 6;
reg_state[CTX_BB_PER_CTX_PTR+1] =
(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
--
2.7.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2] drm/i915/gen9: Set value of Indirect Context Offset based on gen version
2016-02-19 14:58 ` [PATCH v2] " Michel Thierry
@ 2016-02-19 15:19 ` Arun Siluvery
0 siblings, 0 replies; 6+ messages in thread
From: Arun Siluvery @ 2016-02-19 15:19 UTC (permalink / raw)
To: Michel Thierry, intel-gfx
On 19/02/2016 14:58, Michel Thierry wrote:
> The cache line offset for the Indirect CS context (0x21C8) varies from gen
> to gen.
>
> v2: Move it into a function (Arun), use MISSING_CASE (Chris)
>
> Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 26 ++++++++++++++++++++++++--
> 1 file changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 5c0bf02..b1f2886 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -226,7 +226,8 @@ enum {
> FAULT_AND_CONTINUE /* Unsupported */
> };
> #define GEN8_CTX_ID_SHIFT 32
> -#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
> +#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
> +#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
>
> static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
> static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
> @@ -2264,6 +2265,27 @@ make_rpcs(struct drm_device *dev)
> return rpcs;
> }
>
> +static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *ring)
> +{
> + u32 indirect_ctx_offset;
> +
> + switch (INTEL_INFO(ring->dev)->gen) {
> + default:
> + MISSING_CASE(INTEL_INFO(ring->dev)->gen);
> + /* fall through */
> + case 9:
> + indirect_ctx_offset =
> + GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> + break;
> + case 8:
> + indirect_ctx_offset =
> + GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> + break;
> + }
> +
> + return indirect_ctx_offset;
> +}
> +
> static int
> populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
> struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
> @@ -2336,7 +2358,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
> (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
>
> reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
> - CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
> + intel_lr_indirect_ctx_offset(ring) << 6;
>
> reg_state[CTX_BB_PER_CTX_PTR+1] =
> (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
>
Agrees with spec, looks good to me,
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
regards
Arun
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^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/gen9: Set value of Indirect Context Offset based on gen version (rev2)
2016-02-19 14:05 [PATCH] drm/i915/gen9: Set value of Indirect Context Offset based on gen version Michel Thierry
2016-02-19 14:25 ` Chris Wilson
2016-02-19 14:58 ` [PATCH v2] " Michel Thierry
@ 2016-02-19 16:42 ` Patchwork
2016-02-22 10:14 ` [PATCH v3] drm/i915/gen9: Set value of Indirect Context Offset based on gen version Michel Thierry
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2016-02-19 16:42 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
== Summary ==
Series 3629v2 drm/i915/gen9: Set value of Indirect Context Offset based on gen version
2016-02-19T14:57:22.102741 http://patchwork.freedesktop.org/api/1.0/series/3629/revisions/2/mbox/
Applying: drm/i915/gen9: Set value of Indirect Context Offset based on gen version
Repository lacks necessary blobs to fall back on 3-way merge.
Cannot fall back to three-way merge.
Patch failed at 0001 drm/i915/gen9: Set value of Indirect Context Offset based on gen version
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] drm/i915/gen9: Set value of Indirect Context Offset based on gen version
2016-02-19 14:05 [PATCH] drm/i915/gen9: Set value of Indirect Context Offset based on gen version Michel Thierry
` (2 preceding siblings ...)
2016-02-19 16:42 ` ✗ Fi.CI.BAT: failure for drm/i915/gen9: Set value of Indirect Context Offset based on gen version (rev2) Patchwork
@ 2016-02-22 10:14 ` Michel Thierry
3 siblings, 0 replies; 6+ messages in thread
From: Michel Thierry @ 2016-02-22 10:14 UTC (permalink / raw)
To: intel-gfx
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
v2: Move it into a function (Arun), use MISSING_CASE (Chris)
v3: Rebased (catched by ci bat)
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2dca5e1..e12fcab 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -223,7 +223,8 @@ enum {
FAULT_AND_CONTINUE /* Unsupported */
};
#define GEN8_CTX_ID_SHIFT 32
-#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
+#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
+#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
static int intel_lr_context_pin(struct intel_context *ctx,
struct intel_engine_cs *engine);
@@ -2317,6 +2318,27 @@ make_rpcs(struct drm_device *dev)
return rpcs;
}
+static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *ring)
+{
+ u32 indirect_ctx_offset;
+
+ switch (INTEL_INFO(ring->dev)->gen) {
+ default:
+ MISSING_CASE(INTEL_INFO(ring->dev)->gen);
+ /* fall through */
+ case 9:
+ indirect_ctx_offset =
+ GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
+ break;
+ case 8:
+ indirect_ctx_offset =
+ GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
+ break;
+ }
+
+ return indirect_ctx_offset;
+}
+
static int
populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
@@ -2389,7 +2411,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
- CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
+ intel_lr_indirect_ctx_offset(ring) << 6;
reg_state[CTX_BB_PER_CTX_PTR+1] =
(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
--
2.7.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread