* [PATCH 2/5] drm/amdgpu: fix locking in force performance level
2016-02-19 23:17 [PATCH 1/5] drm/amdgpu/gfx8: fix priv reg interrupt enable Alex Deucher
@ 2016-02-19 23:17 ` Alex Deucher
2016-02-19 23:17 ` [PATCH 3/5] drm/amdgpu/pm: add some checks for PX Alex Deucher
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2016-02-19 23:17 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Looks like a copy paste typo when we added powerplay
support.
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7d8d84e..5ed5598 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -157,6 +157,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
mutex_lock(&adev->pm.mutex);
if (adev->pm.dpm.thermal_active) {
count = -EINVAL;
+ mutex_unlock(&adev->pm.mutex);
goto fail;
}
ret = amdgpu_dpm_force_performance_level(adev, level);
@@ -167,8 +168,6 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
mutex_unlock(&adev->pm.mutex);
}
fail:
- mutex_unlock(&adev->pm.mutex);
-
return count;
}
--
2.5.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/5] drm/amdgpu/pm: add some checks for PX
2016-02-19 23:17 [PATCH 1/5] drm/amdgpu/gfx8: fix priv reg interrupt enable Alex Deucher
2016-02-19 23:17 ` [PATCH 2/5] drm/amdgpu: fix locking in force performance level Alex Deucher
@ 2016-02-19 23:17 ` Alex Deucher
2016-02-19 23:17 ` [PATCH 4/5] drm/amdgpu/pm: adjust display configuration after powerstate Alex Deucher
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2016-02-19 23:17 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
I.e., doesn't make sense to change power states or check the
temperature when the asic is powered off.
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 5ed5598..8de765d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -113,6 +113,10 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
+ if ((adev->flags & AMD_IS_PX) &&
+ (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ return snprintf(buf, PAGE_SIZE, "off\n");
+
if (adev->pp_enabled) {
enum amd_dpm_forced_level level;
@@ -140,6 +144,11 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
enum amdgpu_dpm_forced_level level;
int ret = 0;
+ /* Can't force performance level when the card is off */
+ if ((adev->flags & AMD_IS_PX) &&
+ (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ return -EINVAL;
+
if (strncmp("low", buf, strlen("low")) == 0) {
level = AMDGPU_DPM_FORCED_LEVEL_LOW;
} else if (strncmp("high", buf, strlen("high")) == 0) {
@@ -181,8 +190,14 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
char *buf)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
+ struct drm_device *ddev = adev->ddev;
int temp;
+ /* Can't get temperature when the card is off */
+ if ((adev->flags & AMD_IS_PX) &&
+ (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ return -EINVAL;
+
if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
temp = 0;
else
@@ -846,12 +861,16 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct amdgpu_device *adev = dev->dev_private;
+ struct drm_device *ddev = adev->ddev;
if (!adev->pm.dpm_enabled) {
seq_printf(m, "dpm not enabled\n");
return 0;
}
- if (adev->pp_enabled) {
+ if ((adev->flags & AMD_IS_PX) &&
+ (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
+ seq_printf(m, "PX asic powered off\n");
+ } else if (adev->pp_enabled) {
amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
} else {
mutex_lock(&adev->pm.mutex);
--
2.5.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/5] drm/amdgpu/pm: adjust display configuration after powerstate
2016-02-19 23:17 [PATCH 1/5] drm/amdgpu/gfx8: fix priv reg interrupt enable Alex Deucher
2016-02-19 23:17 ` [PATCH 2/5] drm/amdgpu: fix locking in force performance level Alex Deucher
2016-02-19 23:17 ` [PATCH 3/5] drm/amdgpu/pm: add some checks for PX Alex Deucher
@ 2016-02-19 23:17 ` Alex Deucher
2016-02-19 23:17 ` [PATCH 5/5] drm/radeon/pm: " Alex Deucher
2016-02-20 12:10 ` [PATCH 1/5] drm/amdgpu/gfx8: fix priv reg interrupt enable Christian König
4 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2016-02-19 23:17 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, stable
set_power_state defaults to no displays, so we need to update
the display configuration after setting up the powerstate on the
first call. In most cases this is not an issue since ends up
getting called multiple times at any given modeset and the proper
order is achieved in the display changed handling at the top of
the function.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 8de765d..66855b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -648,8 +648,6 @@ force:
/* update display watermarks based on new power state */
amdgpu_display_bandwidth_update(adev);
- /* update displays */
- amdgpu_dpm_display_configuration_changed(adev);
adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
@@ -669,6 +667,9 @@ force:
amdgpu_dpm_post_set_power_state(adev);
+ /* update displays */
+ amdgpu_dpm_display_configuration_changed(adev);
+
if (adev->pm.funcs->force_performance_level) {
if (adev->pm.dpm.thermal_active) {
enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
--
2.5.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 5/5] drm/radeon/pm: adjust display configuration after powerstate
2016-02-19 23:17 [PATCH 1/5] drm/amdgpu/gfx8: fix priv reg interrupt enable Alex Deucher
` (2 preceding siblings ...)
2016-02-19 23:17 ` [PATCH 4/5] drm/amdgpu/pm: adjust display configuration after powerstate Alex Deucher
@ 2016-02-19 23:17 ` Alex Deucher
2016-02-20 12:10 ` [PATCH 1/5] drm/amdgpu/gfx8: fix priv reg interrupt enable Christian König
4 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2016-02-19 23:17 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, stable
set_power_state defaults to no displays, so we need to update
the display configuration after setting up the powerstate on the
first call. In most cases this is not an issue since ends up
getting called multiple times at any given modeset and the proper
order is achieved in the display changed handling at the top of
the function.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/radeon/radeon_pm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 248c5a9..ca3be90 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1079,8 +1079,6 @@ force:
/* update display watermarks based on new power state */
radeon_bandwidth_update(rdev);
- /* update displays */
- radeon_dpm_display_configuration_changed(rdev);
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
@@ -1101,6 +1099,9 @@ force:
radeon_dpm_post_set_power_state(rdev);
+ /* update displays */
+ radeon_dpm_display_configuration_changed(rdev);
+
if (rdev->asic->dpm.force_performance_level) {
if (rdev->pm.dpm.thermal_active) {
enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
--
2.5.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/5] drm/amdgpu/gfx8: fix priv reg interrupt enable
2016-02-19 23:17 [PATCH 1/5] drm/amdgpu/gfx8: fix priv reg interrupt enable Alex Deucher
` (3 preceding siblings ...)
2016-02-19 23:17 ` [PATCH 5/5] drm/radeon/pm: " Alex Deucher
@ 2016-02-20 12:10 ` Christian König
4 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2016-02-20 12:10 UTC (permalink / raw)
To: Alex Deucher, dri-devel; +Cc: Alex Deucher
Am 20.02.2016 um 00:17 schrieb Alex Deucher:
> Looks like a copy/paste typo.
>
> Noticed-by: David Panariti <David.Panariti@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
I'm not so deep into the pm stuff, but that all looks reasonable to me.
Whole set is Reviewed-by: Christian König <christian.koenig@amd.com>
Regards,
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 8f8ec37..1c40bd9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4995,7 +4995,7 @@ static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
> case AMDGPU_IRQ_STATE_ENABLE:
> cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
> cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
> - PRIV_REG_INT_ENABLE, 0);
> + PRIV_REG_INT_ENABLE, 1);
> WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
> break;
> default:
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^ permalink raw reply [flat|nested] 6+ messages in thread