* [PATCH v5] Fix sun7i pin assignment for IRQ's
@ 2016-02-22 8:20 ` Henry Paulissen
0 siblings, 0 replies; 13+ messages in thread
From: Henry Paulissen @ 2016-02-22 8:20 UTC (permalink / raw)
To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Cc: Linus Walleij, Maxime Ripard, Chen-Yu Tsai, Fabian Frederick,
Maxime Coquelin, Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
After testing IRQ pins we found some bugs in the pinctrl declaration.
Both PI* and PC* pins didn't work. PI* pins seemed to be connected
to the wrong mux and PC* pins waren't working at all.
Please note that the A20 soc manual is contradicting between version
and even within the same document for both the PI and PC pins.
Patch is based on testing with the hardware itself.
Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
---
Changes in v2:
After some more testing we found irq on PI pins.
they where on mux6 so this is included in my patch.
Also included is a warning for PI17, this pin was not working
on apritzel his bPI and he thinks it might be correlated to
GIC and IRQ 29.
Changes in v3:
Changed name from nickname to realname in email and SoB.
Changes in v4:
Added closing parenthesis for the C pins.
Changes in v5:
Added a more detailed description.
---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 33 ++++++++++++++-----------------
1 file changed, 15 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..ca7b9a3 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
- SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
- SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
- SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
- SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
+ SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
+ SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
+ SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
+ SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
- SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
+ SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
- SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
+ SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
- SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
+ SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
- SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
+ SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
+ /* EINT29 might not work - more testing needed */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
+ SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
+ SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
--
2.5.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5] Fix sun7i pin assignment for IRQ's @ 2016-02-22 8:20 ` Henry Paulissen 0 siblings, 0 replies; 13+ messages in thread From: Henry Paulissen @ 2016-02-22 8:20 UTC (permalink / raw) To: linux-sunxi Cc: Linus Walleij, Maxime Ripard, Chen-Yu Tsai, Fabian Frederick, Maxime Coquelin, Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, linux-gpio, linux-arm-kernel, linux-kernel After testing IRQ pins we found some bugs in the pinctrl declaration. Both PI* and PC* pins didn't work. PI* pins seemed to be connected to the wrong mux and PC* pins waren't working at all. Please note that the A20 soc manual is contradicting between version and even within the same document for both the PI and PC pins. Patch is based on testing with the hardware itself. Signed-off-by: Henry Paulissen <henry@nitronetworks.nl> --- Changes in v2: After some more testing we found irq on PI pins. they where on mux6 so this is included in my patch. Also included is a warning for PI17, this pin was not working on apritzel his bPI and he thinks it might be correlated to GIC and IRQ 29. Changes in v3: Changed name from nickname to realname in email and SoB. Changes in v4: Added closing parenthesis for the C pins. Changes in v5: Added a more detailed description. --- drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 33 ++++++++++++++----------------- 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c index cf1ce0c..ca7b9a3 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c @@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ - SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */ - SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ - SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ - SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ - SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ - SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ - SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ - SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ SUNXI_FUNCTION(0x3, "uart5"), /* TX */ - SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */ + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ SUNXI_FUNCTION(0x3, "uart5"), /* RX */ - SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */ + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ SUNXI_FUNCTION(0x3, "uart6"), /* TX */ SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */ - SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ SUNXI_FUNCTION(0x3, "uart6"), /* RX */ SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */ - SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */ + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ - SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */ + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ - SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */ + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ - SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */ + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ - SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */ + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ + /* EINT29 might not work - more testing needed */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ SUNXI_FUNCTION(0x3, "uart2"), /* TX */ - SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */ + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ SUNXI_FUNCTION(0x3, "uart2"), /* RX */ - SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */ + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), -- 2.5.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5] Fix sun7i pin assignment for IRQ's @ 2016-02-22 8:20 ` Henry Paulissen 0 siblings, 0 replies; 13+ messages in thread From: Henry Paulissen @ 2016-02-22 8:20 UTC (permalink / raw) To: linux-arm-kernel After testing IRQ pins we found some bugs in the pinctrl declaration. Both PI* and PC* pins didn't work. PI* pins seemed to be connected to the wrong mux and PC* pins waren't working at all. Please note that the A20 soc manual is contradicting between version and even within the same document for both the PI and PC pins. Patch is based on testing with the hardware itself. Signed-off-by: Henry Paulissen <henry@nitronetworks.nl> --- Changes in v2: After some more testing we found irq on PI pins. they where on mux6 so this is included in my patch. Also included is a warning for PI17, this pin was not working on apritzel his bPI and he thinks it might be correlated to GIC and IRQ 29. Changes in v3: Changed name from nickname to realname in email and SoB. Changes in v4: Added closing parenthesis for the C pins. Changes in v5: Added a more detailed description. --- drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 33 ++++++++++++++----------------- 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c index cf1ce0c..ca7b9a3 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c @@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ - SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */ - SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ - SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ - SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ - SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ - SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ - SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ - SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ SUNXI_FUNCTION(0x3, "uart5"), /* TX */ - SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */ + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ SUNXI_FUNCTION(0x3, "uart5"), /* RX */ - SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */ + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ SUNXI_FUNCTION(0x3, "uart6"), /* TX */ SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */ - SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ SUNXI_FUNCTION(0x3, "uart6"), /* RX */ SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */ - SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */ + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ - SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */ + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ - SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */ + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ - SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */ + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ - SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */ + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ + /* EINT29 might not work - more testing needed */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ SUNXI_FUNCTION(0x3, "uart2"), /* TX */ - SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */ + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ SUNXI_FUNCTION(0x3, "uart2"), /* RX */ - SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */ + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), -- 2.5.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
[parent not found: <1456129208-11490-1-git-send-email-henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>]
* Re: [PATCH v5] Fix sun7i pin assignment for IRQ's 2016-02-22 8:20 ` Henry Paulissen (?) @ 2016-02-22 15:26 ` Andre Przywara -1 siblings, 0 replies; 13+ messages in thread From: Andre Przywara @ 2016-02-22 15:26 UTC (permalink / raw) To: henry-oxlTVf6CAJF4HdFT58BDcQ, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw Cc: Linus Walleij, Maxime Ripard, Chen-Yu Tsai, Fabian Frederick, Maxime Coquelin, Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, linux-gpio-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA Hi Henry, On 22/02/16 08:20, Henry Paulissen wrote: > After testing IRQ pins we found some bugs in the pinctrl declaration. > Both PI* and PC* pins didn't work. PI* pins seemed to be connected > to the wrong mux and PC* pins waren't working at all. > > Please note that the A20 soc manual is contradicting between version > and even within the same document for both the PI and PC pins. > > Patch is based on testing with the hardware itself. So I tested this on the BananaPi M1: None of the PIxx interrupts worked before, but now with this patch on top of 4.5-rc5 all PI pins accessible on CON3 (expect PI3, which does not provide an EINT) trigger interrupts as expected. Also PH0, PH1, PH2, PH20 and PH21 trigger interrupts (as before). I cannot say anything about the PC ports, because neither PC19-PC22 nor PH12-PH15 are on a header on the BPi, but now the mapping: PH0-PH21: EINT0-EINT21, PI10-PI19: EINT22-EINT31 looks reasonable enough to me. Also PI17 now worked in my latest testing, so not sure if that was a hiccup at my test setup or the different kernel base I used at the weekend. So dear committer, feel free to drop the comment there. > Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org> Tested-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org> Reviewed-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org> Cheers, Andre. > > --- > > Changes in v2: > After some more testing we found irq on PI pins. > they where on mux6 so this is included in my patch. > > Also included is a warning for PI17, this pin was not working > on apritzel his bPI and he thinks it might be correlated to > GIC and IRQ 29. > > Changes in v3: > Changed name from nickname to realname in email and SoB. > > Changes in v4: > Added closing parenthesis for the C pins. > > Changes in v5: > Added a more detailed description. > --- > drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 33 ++++++++++++++----------------- > 1 file changed, 15 insertions(+), 18 deletions(-) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > index cf1ce0c..ca7b9a3 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > @@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */ > - SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ > - SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ > - SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ > - SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > @@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ > SUNXI_FUNCTION(0x3, "uart5"), /* TX */ > - SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */ > + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ > SUNXI_FUNCTION(0x3, "uart5"), /* RX */ > - SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */ > + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ > SUNXI_FUNCTION(0x3, "uart6"), /* TX */ > SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */ > - SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */ > + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ > SUNXI_FUNCTION(0x3, "uart6"), /* RX */ > SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */ > - SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */ > + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ > SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ > SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ > - SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */ > + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ > SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ > SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ > - SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */ > + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ > SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ > - SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */ > + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ > SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ > - SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */ > + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ > + /* EINT29 might not work - more testing needed */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ > SUNXI_FUNCTION(0x3, "uart2"), /* TX */ > - SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */ > + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ > SUNXI_FUNCTION(0x3, "uart2"), /* RX */ > - SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */ > + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [linux-sunxi] [PATCH v5] Fix sun7i pin assignment for IRQ's @ 2016-02-22 15:26 ` Andre Przywara 0 siblings, 0 replies; 13+ messages in thread From: Andre Przywara @ 2016-02-22 15:26 UTC (permalink / raw) To: henry, linux-sunxi Cc: Linus Walleij, Maxime Ripard, Chen-Yu Tsai, Fabian Frederick, Maxime Coquelin, Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, linux-gpio, linux-arm-kernel, linux-kernel Hi Henry, On 22/02/16 08:20, Henry Paulissen wrote: > After testing IRQ pins we found some bugs in the pinctrl declaration. > Both PI* and PC* pins didn't work. PI* pins seemed to be connected > to the wrong mux and PC* pins waren't working at all. > > Please note that the A20 soc manual is contradicting between version > and even within the same document for both the PI and PC pins. > > Patch is based on testing with the hardware itself. So I tested this on the BananaPi M1: None of the PIxx interrupts worked before, but now with this patch on top of 4.5-rc5 all PI pins accessible on CON3 (expect PI3, which does not provide an EINT) trigger interrupts as expected. Also PH0, PH1, PH2, PH20 and PH21 trigger interrupts (as before). I cannot say anything about the PC ports, because neither PC19-PC22 nor PH12-PH15 are on a header on the BPi, but now the mapping: PH0-PH21: EINT0-EINT21, PI10-PI19: EINT22-EINT31 looks reasonable enough to me. Also PI17 now worked in my latest testing, so not sure if that was a hiccup at my test setup or the different kernel base I used at the weekend. So dear committer, feel free to drop the comment there. > Signed-off-by: Henry Paulissen <henry@nitronetworks.nl> Tested-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre. > > --- > > Changes in v2: > After some more testing we found irq on PI pins. > they where on mux6 so this is included in my patch. > > Also included is a warning for PI17, this pin was not working > on apritzel his bPI and he thinks it might be correlated to > GIC and IRQ 29. > > Changes in v3: > Changed name from nickname to realname in email and SoB. > > Changes in v4: > Added closing parenthesis for the C pins. > > Changes in v5: > Added a more detailed description. > --- > drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 33 ++++++++++++++----------------- > 1 file changed, 15 insertions(+), 18 deletions(-) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > index cf1ce0c..ca7b9a3 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > @@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */ > - SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ > - SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ > - SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ > - SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > @@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ > SUNXI_FUNCTION(0x3, "uart5"), /* TX */ > - SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */ > + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ > SUNXI_FUNCTION(0x3, "uart5"), /* RX */ > - SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */ > + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ > SUNXI_FUNCTION(0x3, "uart6"), /* TX */ > SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */ > - SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */ > + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ > SUNXI_FUNCTION(0x3, "uart6"), /* RX */ > SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */ > - SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */ > + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ > SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ > SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ > - SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */ > + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ > SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ > SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ > - SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */ > + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ > SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ > - SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */ > + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ > SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ > - SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */ > + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ > + /* EINT29 might not work - more testing needed */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ > SUNXI_FUNCTION(0x3, "uart2"), /* TX */ > - SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */ > + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ > SUNXI_FUNCTION(0x3, "uart2"), /* RX */ > - SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */ > + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [linux-sunxi] [PATCH v5] Fix sun7i pin assignment for IRQ's @ 2016-02-22 15:26 ` Andre Przywara 0 siblings, 0 replies; 13+ messages in thread From: Andre Przywara @ 2016-02-22 15:26 UTC (permalink / raw) To: linux-arm-kernel Hi Henry, On 22/02/16 08:20, Henry Paulissen wrote: > After testing IRQ pins we found some bugs in the pinctrl declaration. > Both PI* and PC* pins didn't work. PI* pins seemed to be connected > to the wrong mux and PC* pins waren't working at all. > > Please note that the A20 soc manual is contradicting between version > and even within the same document for both the PI and PC pins. > > Patch is based on testing with the hardware itself. So I tested this on the BananaPi M1: None of the PIxx interrupts worked before, but now with this patch on top of 4.5-rc5 all PI pins accessible on CON3 (expect PI3, which does not provide an EINT) trigger interrupts as expected. Also PH0, PH1, PH2, PH20 and PH21 trigger interrupts (as before). I cannot say anything about the PC ports, because neither PC19-PC22 nor PH12-PH15 are on a header on the BPi, but now the mapping: PH0-PH21: EINT0-EINT21, PI10-PI19: EINT22-EINT31 looks reasonable enough to me. Also PI17 now worked in my latest testing, so not sure if that was a hiccup at my test setup or the different kernel base I used at the weekend. So dear committer, feel free to drop the comment there. > Signed-off-by: Henry Paulissen <henry@nitronetworks.nl> Tested-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre. > > --- > > Changes in v2: > After some more testing we found irq on PI pins. > they where on mux6 so this is included in my patch. > > Also included is a warning for PI17, this pin was not working > on apritzel his bPI and he thinks it might be correlated to > GIC and IRQ 29. > > Changes in v3: > Changed name from nickname to realname in email and SoB. > > Changes in v4: > Added closing parenthesis for the C pins. > > Changes in v5: > Added a more detailed description. > --- > drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 33 ++++++++++++++----------------- > 1 file changed, 15 insertions(+), 18 deletions(-) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > index cf1ce0c..ca7b9a3 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > @@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */ > - SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ > - SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ > - SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ > - SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ > - SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ > + SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > @@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ > SUNXI_FUNCTION(0x3, "uart5"), /* TX */ > - SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */ > + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ > SUNXI_FUNCTION(0x3, "uart5"), /* RX */ > - SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */ > + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ > SUNXI_FUNCTION(0x3, "uart6"), /* TX */ > SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */ > - SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */ > + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ > SUNXI_FUNCTION(0x3, "uart6"), /* RX */ > SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */ > - SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */ > + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ > SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ > SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ > - SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */ > + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ > SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ > SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ > - SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */ > + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ > SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ > - SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */ > + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ > SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ > - SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */ > + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ > + /* EINT29 might not work - more testing needed */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ > SUNXI_FUNCTION(0x3, "uart2"), /* TX */ > - SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */ > + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ > SUNXI_FUNCTION(0x3, "uart2"), /* RX */ > - SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */ > + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5] Fix sun7i pin assignment for IRQ's 2016-02-22 8:20 ` Henry Paulissen (?) @ 2016-02-25 9:36 ` Linus Walleij -1 siblings, 0 replies; 13+ messages in thread From: Linus Walleij @ 2016-02-25 9:36 UTC (permalink / raw) To: Henry Paulissen Cc: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Fabian Frederick, Maxime Coquelin, Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On Mon, Feb 22, 2016 at 9:20 AM, Henry Paulissen <draakje197-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > After testing IRQ pins we found some bugs in the pinctrl declaration. > Both PI* and PC* pins didn't work. PI* pins seemed to be connected > to the wrong mux and PC* pins waren't working at all. > > Please note that the A20 soc manual is contradicting between version > and even within the same document for both the PI and PC pins. > > Patch is based on testing with the hardware itself. > > Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org> (...) > Changes in v5: > Added a more detailed description. Aha there is a v5. I took out the v4 and applied this instead. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5] Fix sun7i pin assignment for IRQ's @ 2016-02-25 9:36 ` Linus Walleij 0 siblings, 0 replies; 13+ messages in thread From: Linus Walleij @ 2016-02-25 9:36 UTC (permalink / raw) To: Henry Paulissen Cc: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Fabian Frederick, Maxime Coquelin, Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org On Mon, Feb 22, 2016 at 9:20 AM, Henry Paulissen <draakje197@gmail.com> wrote: > After testing IRQ pins we found some bugs in the pinctrl declaration. > Both PI* and PC* pins didn't work. PI* pins seemed to be connected > to the wrong mux and PC* pins waren't working at all. > > Please note that the A20 soc manual is contradicting between version > and even within the same document for both the PI and PC pins. > > Patch is based on testing with the hardware itself. > > Signed-off-by: Henry Paulissen <henry@nitronetworks.nl> (...) > Changes in v5: > Added a more detailed description. Aha there is a v5. I took out the v4 and applied this instead. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5] Fix sun7i pin assignment for IRQ's @ 2016-02-25 9:36 ` Linus Walleij 0 siblings, 0 replies; 13+ messages in thread From: Linus Walleij @ 2016-02-25 9:36 UTC (permalink / raw) To: linux-arm-kernel On Mon, Feb 22, 2016 at 9:20 AM, Henry Paulissen <draakje197@gmail.com> wrote: > After testing IRQ pins we found some bugs in the pinctrl declaration. > Both PI* and PC* pins didn't work. PI* pins seemed to be connected > to the wrong mux and PC* pins waren't working at all. > > Please note that the A20 soc manual is contradicting between version > and even within the same document for both the PI and PC pins. > > Patch is based on testing with the hardware itself. > > Signed-off-by: Henry Paulissen <henry@nitronetworks.nl> (...) > Changes in v5: > Added a more detailed description. Aha there is a v5. I took out the v4 and applied this instead. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 13+ messages in thread
[parent not found: <CACRpkdbbOyp-=5n64QBhigtAebKV5BmFcnvFumjXv3f8bj8pbg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v5] Fix sun7i pin assignment for IRQ's [not found] ` <CACRpkdbbOyp-=5n64QBhigtAebKV5BmFcnvFumjXv3f8bj8pbg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2016-02-25 9:37 ` Henry Paulissen [not found] ` <fe1c8052-f313-415d-a5aa-cac61b492dd6-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org> 0 siblings, 1 reply; 13+ messages in thread From: Henry Paulissen @ 2016-02-25 9:37 UTC (permalink / raw) To: linux-sunxi Cc: draakje197-Re5JQEeQqe8AvxtiuMwx3w, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, wens-jdAy2FN1RRM, fabf-AgBVmzD5pcezQB+pC5nmwQ, maxime.coquelin-qxv4g6HH51o, plagnioj-sclMFOaUSTBWk0Htik3J/w, hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w, linux-gpio-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linus.walleij-QSEj5FYQhm4dnm+yROfE0A [-- Attachment #1.1: Type: text/plain, Size: 484 bytes --] Op donderdag 25 februari 2016 10:36:38 UTC+1 schreef Linus Walleij: > Aha there is a v5. I took out the v4 and applied this > instead. > > > There is also a v6. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. [-- Attachment #1.2: Type: text/html, Size: 845 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
[parent not found: <fe1c8052-f313-415d-a5aa-cac61b492dd6-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>]
* Re: [PATCH v5] Fix sun7i pin assignment for IRQ's 2016-02-25 9:37 ` Henry Paulissen [not found] ` <fe1c8052-f313-415d-a5aa-cac61b492dd6-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org> @ 2016-03-07 3:25 ` Linus Walleij 0 siblings, 0 replies; 13+ messages in thread From: Linus Walleij @ 2016-03-07 3:25 UTC (permalink / raw) To: Henry Paulissen Cc: linux-sunxi, Henry P, Maxime Ripard, Chen-Yu Tsai, Fabian Frederick, Maxime Coquelin, Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On Thu, Feb 25, 2016 at 4:37 PM, Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org> wrote: > Op donderdag 25 februari 2016 10:36:38 UTC+1 schreef Linus Walleij: >> >> Aha there is a v5. I took out the v4 and applied this >> instead. > > There is also a v6. Sigh this is too high iteration rate for me. At this point any changes need to come as patches on top of v5. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5] Fix sun7i pin assignment for IRQ's @ 2016-03-07 3:25 ` Linus Walleij 0 siblings, 0 replies; 13+ messages in thread From: Linus Walleij @ 2016-03-07 3:25 UTC (permalink / raw) To: Henry Paulissen Cc: linux-sunxi, Henry P, Maxime Ripard, Chen-Yu Tsai, Fabian Frederick, Maxime Coquelin, Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org On Thu, Feb 25, 2016 at 4:37 PM, Henry Paulissen <henry@nitronetworks.nl> wrote: > Op donderdag 25 februari 2016 10:36:38 UTC+1 schreef Linus Walleij: >> >> Aha there is a v5. I took out the v4 and applied this >> instead. > > There is also a v6. Sigh this is too high iteration rate for me. At this point any changes need to come as patches on top of v5. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5] Fix sun7i pin assignment for IRQ's @ 2016-03-07 3:25 ` Linus Walleij 0 siblings, 0 replies; 13+ messages in thread From: Linus Walleij @ 2016-03-07 3:25 UTC (permalink / raw) To: linux-arm-kernel On Thu, Feb 25, 2016 at 4:37 PM, Henry Paulissen <henry@nitronetworks.nl> wrote: > Op donderdag 25 februari 2016 10:36:38 UTC+1 schreef Linus Walleij: >> >> Aha there is a v5. I took out the v4 and applied this >> instead. > > There is also a v6. Sigh this is too high iteration rate for me. At this point any changes need to come as patches on top of v5. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2016-03-07 3:25 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
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2016-02-22 8:20 [PATCH v5] Fix sun7i pin assignment for IRQ's Henry Paulissen
2016-02-22 8:20 ` Henry Paulissen
2016-02-22 8:20 ` Henry Paulissen
[not found] ` <1456129208-11490-1-git-send-email-henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
2016-02-22 15:26 ` Andre Przywara
2016-02-22 15:26 ` [linux-sunxi] " Andre Przywara
2016-02-22 15:26 ` Andre Przywara
2016-02-25 9:36 ` Linus Walleij
2016-02-25 9:36 ` Linus Walleij
2016-02-25 9:36 ` Linus Walleij
[not found] ` <CACRpkdbbOyp-=5n64QBhigtAebKV5BmFcnvFumjXv3f8bj8pbg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-02-25 9:37 ` Henry Paulissen
[not found] ` <fe1c8052-f313-415d-a5aa-cac61b492dd6-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>
2016-03-07 3:25 ` Linus Walleij
2016-03-07 3:25 ` Linus Walleij
2016-03-07 3:25 ` Linus Walleij
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