From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: Re: [Qemu-arm] [PATCH] target-arm: Implement MRS (banked) and MSR (banked) instructions
Date: Mon, 29 Feb 2016 19:24:25 +0300 [thread overview]
Message-ID: <56D470B9.3090609@gmail.com> (raw)
In-Reply-To: <1456762734-23939-1-git-send-email-peter.maydell@linaro.org>
On 29.02.2016 19:18, Peter Maydell wrote:
> Starting with the ARMv7 Virtualization Extensions, the A32 and T32
> instruction sets provide instructions "MSR (banked)" and "MRS
> (banked)" which can be used to access registers for a mode other
> than the current one:
> * R<m>_<mode>
> * ELR_hyp
> * SPSR_<mode>
>
> Implement the missing instructions.
Likely, there is no disassembling support in QEMU for these instructions
as well. Are you going to add it?
Best regards,
Sergey
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> We don't support EL2 yet, but you can get at these on a v8 CPU in
> 32-bit EL1 if EL3 is enabled. Obviously there's not going to be much
> 32-bit EL1 code out there that uses the insns though, as it wouldn't
> work on v7 if it did...
WARNING: multiple messages have this Message-ID (diff)
From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, qemu-arm@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] target-arm: Implement MRS (banked) and MSR (banked) instructions
Date: Mon, 29 Feb 2016 19:24:25 +0300 [thread overview]
Message-ID: <56D470B9.3090609@gmail.com> (raw)
In-Reply-To: <1456762734-23939-1-git-send-email-peter.maydell@linaro.org>
On 29.02.2016 19:18, Peter Maydell wrote:
> Starting with the ARMv7 Virtualization Extensions, the A32 and T32
> instruction sets provide instructions "MSR (banked)" and "MRS
> (banked)" which can be used to access registers for a mode other
> than the current one:
> * R<m>_<mode>
> * ELR_hyp
> * SPSR_<mode>
>
> Implement the missing instructions.
Likely, there is no disassembling support in QEMU for these instructions
as well. Are you going to add it?
Best regards,
Sergey
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> We don't support EL2 yet, but you can get at these on a v8 CPU in
> 32-bit EL1 if EL3 is enabled. Obviously there's not going to be much
> 32-bit EL1 code out there that uses the insns though, as it wouldn't
> work on v7 if it did...
next prev parent reply other threads:[~2016-02-29 16:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-29 16:18 [Qemu-arm] [PATCH] target-arm: Implement MRS (banked) and MSR (banked) instructions Peter Maydell
2016-02-29 16:18 ` [Qemu-devel] " Peter Maydell
2016-02-29 16:24 ` Sergey Fedorov [this message]
2016-02-29 16:24 ` Sergey Fedorov
2016-02-29 16:25 ` [Qemu-arm] " Peter Maydell
2016-02-29 16:25 ` [Qemu-devel] " Peter Maydell
2016-02-29 21:22 ` [Qemu-arm] " Edgar E. Iglesias
2016-02-29 21:22 ` [Qemu-devel] " Edgar E. Iglesias
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