Re: Debugging second dvi output on quadro fx380 not working

* Re: Debugging second dvi output on quadro fx380 not working
       [not found]           ` <56D65CC3.1060405-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
@ 2016-03-02 16:24             ` Hans de Goede
  0 siblings, 0 replies; only message in thread
From: Hans de Goede @ 2016-03-02 16:24 UTC (permalink / raw)
  To: Ben Skeggs,
	nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org

<adding nouveau-devel to the Cc>

Hi Ben,

On 02-03-16 04:23, Ben Skeggs wrote:
> On 03/01/2016 09:37 PM, Hans de Goede wrote:

<snip>

>> Ok, I've but an mmiotrace of the blob starting with a monitor connected
>> to the troubesome connector here:
>>
>> https://fedorapeople.org/~jwrdegoede/mmiotrace.log.xz
>>
>> And a demmio-ed version (with color esc sequences) here:
>>
>> https://fedorapeople.org/~jwrdegoede/demmio.log.xz
>>
>> Some pointers where in this can I find the relevant parts (the supervisor
>> irq handling) for this problem would be welcome :)
> Look for reads from register 0x610024.  A value of 0x10 is the start of
> supervisor 0 (nv50_disp_intr_unk10), 0x20 for supervisor 1
> (nv50_disp_intr_unk20), 0x40 for supervisor 2 (nv50_disp_intr_unk40).
>
> The end of supervisor handling can be detected with a write to 0x610030.
>   But, for supervisor 1 this isn't obvious (NVIDIA offload it to some
> other on-board processor, we do it from the host instead), but
> supervisor 2 generally follows it immediately anyway.

Ok, so I've been analyzing mmiotraces / bios scripts the entire day. You're
right that the 2nd connector uses a different script, but this script matches
with the mmiotrace of the blob, so I believe that this is the right thing to-do.

However things start to deviate when the script finishes, here at the last
2 io-accesses from the script with the blob, followed by what it does before
finishing the supervisor req.

[0] 443.963270 MMIO32 R 0x000008 0x00000000 PMC.BOOT_2 => 0
[0] 443.963295 MMIO32 R 0x619494 0x00080060 PDISPLAY.VGA.CR+0x94 => 0x80060
---bios script ends here---
[0] 443.963325 MMIO32 R 0x614200 0x00000080 PDISPLAY.CLOCK.VPLL_CTRL2[0] => 0x80
[0] 443.963340 MMIO32 W 0x614200 0x00000080 PDISPLAY.CLOCK.VPLL_CTRL2[0] <= 0x80
[0] 443.963358 MMIO32 R 0x614b00 0x00074080 PDISPLAY.CLOCK.SOR[0x1] => 0x74080
---blob does ton of extra stuff before finishing the supervisor task---
[0] 443.963375 MMIO32 R 0x61c804 0x10000001 PDISPLAY.SOR[0x1].PWR => { NORMAL_STATE = PU | NORMAL_START = NORMAL | SAFE_STATE = PD | SAFE_START = NORMAL | MODE }
[0] 443.963394 MMIO32 R 0x00e840 0x80080000 PNVIO.RPLL2.CTRL => { UNK0 = 0 | UNK19 = 0x1 | UNK31 }
[0] 443.963413 MMIO32 W 0x00e840 0x80080000 PNVIO.RPLL2.CTRL <= { UNK0 = 0 | UNK19 = 0x1 | UNK31 }
[0] 443.963430 MMIO32 R 0x614b00 0x00074080 PDISPLAY.CLOCK.SOR[0x1] => 0x74080
[0] 443.963445 MMIO32 W 0x614b00 0x03074080 PDISPLAY.CLOCK.SOR[0x1] <= 0x3074080
[0] 443.963462 MMIO32 R 0x61c90c 0x00401101 PDISPLAY.SOR[0x1].LINK[0].DP_CTRL => { LANE_MASK = 0 | TRAINING_PATTERN = DISABLED | 0x401101 }
[0] 443.963477 MMIO32 W 0x61c90c 0x00401101 PDISPLAY.SOR[0x1].LINK[0].DP_CTRL <= { LANE_MASK = 0 | TRAINING_PATTERN = DISABLED | 0x401101 }
[0] 443.963494 MMIO32 R 0x61c80c 0x01000000 PDISPLAY.SOR[0x1].PLL0 => 0x1000000
[0] 443.963510 MMIO32 W 0x61c80c 0x00000000 PDISPLAY.SOR[0x1].PLL0 <= 0
[0] 443.963527 MMIO32 R 0x61c808 0x00800000 PDISPLAY.SOR[0x1]+0x8 => 0x800000
[0] 443.963542 MMIO32 W 0x61c808 0x14800000 PDISPLAY.SOR[0x1]+0x8 <= 0x14800000
[0] 443.963564 MMIO32 R 0x009200 0x00000288 PTIMER.CLOCK_DIV => 0x288
[0] 443.963588 MMIO32 R 0x009210 0x000000fa PTIMER.CLOCK_MUL => 0xfa
[0] 443.963608 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963627 MMIO32 R 0x009400 0xb8957340 PTIMER.TIME_LOW => 0xb8957340
[0] 443.963647 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963667 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963686 MMIO32 R 0x009400 0xb8965940 PTIMER.TIME_LOW => 0xb8965940
[0] 443.963706 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963725 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963745 MMIO32 R 0x009400 0xb8973f00 PTIMER.TIME_LOW => 0xb8973f00
[0] 443.963765 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963784 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963804 MMIO32 R 0x009400 0xb8982520 PTIMER.TIME_LOW => 0xb8982520
[0] 443.963824 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963843 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963863 MMIO32 R 0x009400 0xb8990ac0 PTIMER.TIME_LOW => 0xb8990ac0
[0] 443.963882 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963902 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963922 MMIO32 R 0x009400 0xb899f080 PTIMER.TIME_LOW => 0xb899f080
[0] 443.963941 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963961 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.963980 MMIO32 R 0x009400 0xb89ad660 PTIMER.TIME_LOW => 0xb89ad660
[0] 443.964000 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.964020 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.964039 MMIO32 R 0x009400 0xb89bbc20 PTIMER.TIME_LOW => 0xb89bbc20
[0] 443.964059 MMIO32 R 0x009410 0x1437a9bf PTIMER.TIME_HIGH => 0x1437a9bf
[0] 443.964076 MMIO32 R 0x61c808 0x14800000 PDISPLAY.SOR[0x1]+0x8 => 0x14800000
[0] 443.964091 MMIO32 W 0x61c808 0x00800000 PDISPLAY.SOR[0x1]+0x8 <= 0x800000
[0] 443.964108 MMIO32 R 0x61c80c 0x00000000 PDISPLAY.SOR[0x1].PLL0 => 0
[0] 443.964124 MMIO32 W 0x61c80c 0x01000000 PDISPLAY.SOR[0x1].PLL0 <= 0x1000000
[0] 443.964141 MMIO32 R 0x61c804 0x10000001 PDISPLAY.SOR[0x1].PWR => { NORMAL_STATE = PU | NORMAL_START = NORMAL | SAFE_STATE = PD | SAFE_START = NORMAL | MODE }
[0] 443.964158 MMIO32 R 0x61c830 0x000b8800 PDISPLAY.SOR[0x1].BLANK => 0xb8800
[0] 443.964174 MMIO32 W 0x61c840 0x1f008000 PDISPLAY.SOR[0x1].SEQ_INST[0] <= 0x1f008000
[0] 443.964191 MMIO32 R 0x617334 0x00000000 PDISPLAY.AUDIO+0x34 => 0
[0] 443.964207 MMIO32 R 0x61733c 0x11000000 PDISPLAY.AUDIO.N => { VALUE = 0 | GENERATE = ALTERNATIVE | LOOKUP_ENABLE }
[0] 443.964224 MMIO32 R 0x6165a4 0x00020038 PDISPLAY.HDMI[0].ACR+0x3c => 0x20038
[0] 443.964240 MMIO32 W 0x6165a4 0x00020038 PDISPLAY.HDMI[0].ACR+0x3c <= 0x20038
[0] 443.964256 MMIO32 W 0x617334 0x00000001 PDISPLAY.AUDIO+0x34 <= 0x1
[0] 443.964272 MMIO32 R 0x614b00 0x03074080 PDISPLAY.CLOCK.SOR[0x1] => 0x3074080
[0] 443.964288 MMIO32 W 0x614b00 0x03074080 PDISPLAY.CLOCK.SOR[0x1] <= 0x3074080
[0] 443.964307 MMIO32 R 0x61630c 0x01220000 PDISPLAY+0x630c => 0x1220000
[0] 443.964322 MMIO32 W 0x61630c 0x01220000 PDISPLAY+0x630c <= 0x1220000
[0] 443.964347 MMIO32 R 0x00e1b8 0x7fffffff PNVIO.IBUF_ENABLE_0 => { GPIO_0_15 = 0xffff | I2C_0_3 = 0xf | I2C_5 | UNK21 = 0x1f | UNK26 | UNK27 = 0xf }
[0] 443.964366 MMIO32 W 0x00e1b8 0x7e7fffff PNVIO.IBUF_ENABLE_0 <= { GPIO_0_15 = 0xffff | I2C_0_3 = 0xf | I2C_5 | UNK21 = 0x13 | UNK26 | UNK27 = 0xf }
[0] 443.964386 MMIO32 R 0x00e600 0xa0400000 PNVIO+0x600 => 0xa0400000
[0] 443.964406 MMIO32 R 0x00e610 0x7c0a000f PNVIO+0x610 => 0x7c0a000f
[0] 443.964425 MMIO32 R 0x00e61c 0x000a000f PNVIO+0x61c => 0xa000f
[0] 443.964444 MMIO32 W 0x00e600 0xa0400000 PNVIO+0x600 <= 0xa0400000
[0] 443.964463 MMIO32 W 0x00e610 0x7c0a000f PNVIO+0x610 <= 0x7c0a000f
[0] 443.964482 MMIO32 W 0x00e61c 0x000a000f PNVIO+0x61c <= 0xa000f
[0] 443.964499 MMIO32 R 0x61e018 0x00000302 PDISPLAY.EXT[0]+0x18 => 0x302
[0] 443.964515 MMIO32 W 0x61e018 0x00000302 PDISPLAY.EXT[0]+0x18 <= 0x302
[0] 443.964532 MMIO32 R 0x61e028 0x00000000 PDISPLAY.EXT[0]+0x28 => 0
[0] 443.964549 MMIO32 R 0x61e034 0x00000000 PDISPLAY.EXT[0]+0x34 => 0
[0] 443.964568 MMIO32 W 0x61e028 0x00000000 PDISPLAY.EXT[0]+0x28 <= 0
[0] 443.964584 MMIO32 W 0x61e034 0x00000000 PDISPLAY.EXT[0]+0x34 <= 0
[0] 443.964601 MMIO32 R 0x61e818 0x00000302 PDISPLAY.EXT[0x1]+0x18 => 0x302
[0] 443.964616 MMIO32 W 0x61e818 0x00000302 PDISPLAY.EXT[0x1]+0x18 <= 0x302
[0] 443.964633 MMIO32 R 0x61e828 0x00000000 PDISPLAY.EXT[0x1]+0x28 => 0
[0] 443.964650 MMIO32 R 0x61e834 0x00000000 PDISPLAY.EXT[0x1]+0x34 => 0
[0] 443.964666 MMIO32 W 0x61e828 0x00000000 PDISPLAY.EXT[0x1]+0x28 <= 0
[0] 443.964681 MMIO32 W 0x61e834 0x00000000 PDISPLAY.EXT[0x1]+0x34 <= 0
[0] 443.964698 MMIO32 R 0x61f018 0x00020306 PDISPLAY.EXT[0x2]+0x18 => 0x20306
[0] 443.964713 MMIO32 W 0x61f018 0x00020306 PDISPLAY.EXT[0x2]+0x18 <= 0x20306
[0] 443.964730 MMIO32 R 0x61f028 0x00000000 PDISPLAY.EXT[0x2]+0x28 => 0
[0] 443.964747 MMIO32 R 0x61f034 0x00000000 PDISPLAY.EXT[0x2]+0x34 => 0
[0] 443.964763 MMIO32 W 0x61f028 0x00000000 PDISPLAY.EXT[0x2]+0x28 <= 0
[0] 443.964778 MMIO32 W 0x61f034 0x00000000 PDISPLAY.EXT[0x2]+0x34 <= 0
[0] 443.964794 MMIO32 R 0x610040 0x00000000 PDISPLAY+0x40 => 0
[0] 443.964810 MMIO32 W 0x610040 0x00000000 PDISPLAY+0x40 <= 0
[0] 443.964826 MMIO32 R 0x616300 0x00000000 PDISPLAY+0x6300 => 0
[0] 443.964842 MMIO32 W 0x616300 0x00000000 PDISPLAY+0x6300 <= 0
[0] 443.964858 MMIO32 R 0x610044 0x00000000 PDISPLAY+0x44 => 0
[0] 443.964873 MMIO32 W 0x610044 0x00000000 PDISPLAY+0x44 <= 0
[0] 443.964890 MMIO32 R 0x616b00 0x00000000 PDISPLAY+0x6b00 => 0
[0] 443.964905 MMIO32 W 0x616b00 0x00000000 PDISPLAY+0x6b00 <= 0
[0] 443.964938 MMIO32 R 0x100674 0x0009000b PFB+0x674 => 0x9000b
[0] 443.964958 MMIO32 R 0x100578 0x000a0003 PFB+0x578 => 0xa0003
[0] 443.964976 MMIO32 W 0x100674 0x00090002 PFB+0x674 <= 0x90002
[0] 443.964994 MMIO32 W 0x100578 0x000a0001 PFB+0x578 <= 0xa0001
[0] 443.965013 MMIO32 R 0x100b0c 0x00080003 PFB+0xb0c => 0x80003
[0] 443.965031 MMIO32 W 0x100b0c 0x00080001 PFB+0xb0c <= 0x80001
[0] 443.965051 MMIO32 R 0x100e04 0x80044881 PFB+0xe04 => 0x80044881
[0] 443.965070 MMIO32 R 0x100b28 0x00048521 PFB+0xb28 => 0x48521
[0] 443.965089 MMIO32 R 0x100b28 0x00048521 PFB+0xb28 => 0x48521
[0] 443.965109 MMIO32 R 0x100b90 0x0000000f PFB+0xb90 => 0xf
[0] 443.965128 MMIO32 R 0x100b80 0x00780078 PFB+0xb80 => 0x780078
[0] 443.965148 MMIO32 R 0x100b84 0x00780078 PFB+0xb84 => 0x780078
[0] 443.965167 MMIO32 R 0x100b90 0x0000000f PFB+0xb90 => 0xf
[0] 443.965185 MMIO32 W 0x100b80 0x000003f4 PFB+0xb80 <= 0x3f4
[0] 443.965203 MMIO32 W 0x100b84 0x00000000 PFB+0xb84 <= 0
[0] 443.965223 MMIO32 R 0x100b00 0x23000305 PFB+0xb00 => 0x23000305
[0] 443.965242 MMIO32 R 0x100e04 0x80044881 PFB+0xe04 => 0x80044881
[0] 443.965262 MMIO32 R 0x100b50 0x00000058 PFB+0xb50 => 0x58
[0] 443.965280 MMIO32 W 0x100b50 0x00000008 PFB+0xb50 <= 0x8
[0] 443.965299 MMIO32 R 0x100b54 0x00000058 PFB+0xb54 => 0x58
[0] 443.965317 MMIO32 W 0x100b54 0x00000008 PFB+0xb54 <= 0x8
[0] 443.965335 MMIO32 W 0x100b00 0x23000305 PFB+0xb00 <= 0x23000305
[0] 443.965354 MMIO32 R 0x100b28 0x00048521 PFB+0xb28 => 0x48521
[0] 443.965372 MMIO32 W 0x100b28 0x0000223a PFB+0xb28 <= 0x223a
[0] 443.965390 MMIO32 W 0x100e04 0x80020d01 PFB+0xe04 <= 0x80020d01
[0] 443.965413 MMIO32 R 0x001098 0x21ca003c PBUS.DEBUG_6 => { HWSQ_ENABLE | HWSQ_OVERRIDE_MODE = READ_OVERRIDE | CLOCK_GATING_1588 | 0x21ca0004 }
[0] 443.965431 MMIO32 W 0x001098 0x21ca0034 PBUS.DEBUG_6 <= { HWSQ_OVERRIDE_MODE = READ_OVERRIDE | CLOCK_GATING_1588 | 0x21ca0004 }
[0] 443.965450 MMIO32 W 0x001304 0x00000000 PBUS.HWSQ.ENTRY_POINT <= { 0 = 0 | 1 = 0 | 2 = 0 | 3 = 0 }
[0] 443.965469 MMIO32 W 0x001318 0x00000000 PBUS.HWSQ.ENTRY_POINT_HIGH <= { 0 }
[0] HWSQ     0x080000            PBUS_HWSQ_NEW_CODE[0]
00000000: e2 00 00 00 80     data 0x80000000
00000005: e0 30 00 61 00     addr 0x610030
0000000a: e2 01 00 00 00     data 0x1
0000000f: e0 50 11 00 00     addr 0x1150
00000014: 7f                 exit
00000015: 7f                 exit
00000016: 7f                 exit
00000017: 7f                 exit

Whereas nouveau does a lot less:

[0] 108.304143 MMIO32 R 0x000008 0x00000000 PMC.BOOT_2 => 0
[0] 108.304162 MMIO8 W 0x6013d4 0x00000094 PRMIO.CRX <= 0x94
[0] 108.304176 CRTC0 R     0x94       0x68 0x94 => 0x68
---bios script ends here---
[0] 108.304195 MMIO32 R 0x614200 0x00800080 PDISPLAY.CLOCK.VPLL_CTRL2[0] => 0x800080
[0] 108.304208 MMIO32 W 0x614200 0x00800080 PDISPLAY.CLOCK.VPLL_CTRL2[0] <= 0x800080
[0] 108.304222 MMIO32 R 0x614b00 0x00874080 PDISPLAY.CLOCK.SOR[0x1] => 0x874080
[0] 108.304235 MMIO32 W 0x614b00 0x00874080 PDISPLAY.CLOCK.SOR[0x1] <= 0x874080
---nouveau is done here---
[0] 108.304248 MMIO32 W 0x610030 0x80000000 PDISPLAY.UNK30_CTRL <= { PENDING }

Which is weird, what happened to nv50_disp_intr_unk20_2() ?

Also for some reason nouveau does seem to do a bunch of stuff before
executing the script, for which I cannot directly find the code where this comes from:

[0] 108.302966 MMIO32 R 0x610024 0x00000020 PDISPLAY.INTR_1 => { CLK_UNK1 }
[0] 108.302980 MMIO32 W 0x610024 0x00000020 PDISPLAY.INTR_1 <= { CLK_UNK1 }
[0] 108.302996 MMIO32 W 0x000140 0x00000001 PMC.INTR_EN_HOST <= { HARDWARE }
SLEEP 0.257000ms
[0] 108.303253 MMIO32 R 0x610030 0x000002b0 PDISPLAY.UNK30_CTRL => { UPDATE_VCLK0 | 0xb0 }
---here the script should begin---
---but these do not come from the script---
[0] 108.303271 MMIO32 R 0x610b5c 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL[0][0x1] => 0
[0] 108.303285 MMIO32 R 0x610b64 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL[0x1][0x1] => 0
[0] 108.303298 MMIO32 R 0x610b6c 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL[0x2][0x1] => 0
[0] 108.303312 MMIO32 R 0x610798 0x00000000 PDISPLAY.SOR_VAL_MODE_CTRL[0][0x1] => 0
[0] 108.303326 MMIO32 R 0x6107a0 0x00000000 PDISPLAY.SOR_VAL_MODE_CTRL[0x1][0x1] => 0
[0] 108.303340 MMIO32 R 0x6107a8 0x00000000 PDISPLAY.SOR_VAL_MODE_CTRL[0x2][0x1] => 0
[0] 108.303354 MMIO32 R 0x6107b0 0x00000000 PDISPLAY+0x7b0 => 0
[0] 108.303367 MMIO32 R 0x610b84 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL2[0][0x1] => 0
[0] 108.303381 MMIO32 R 0x610b8c 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL2[0x1][0x1] => 0
[0] 108.303395 MMIO32 R 0x610b94 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL2[0x2][0x1] => 0
[0] 108.303409 MMIO32 R 0x610ad0 0x00824414 PDISPLAY.CRTC_VAL[0].CLOCK[0] => 0x824414
[0] 108.303425 MMIO32 W 0x614100 0x10000611 PDISPLAY.CLOCK.VPLL_CTRL1[0] <= { UNK0 = 0x11 | STAGES = 2 | CONNECTED = 0x3 | UNK12 = 0 | UNK23 = 0 | UNK28 }
[0] 108.303439 MMIO32 R 0x614104 0x00020016 PDISPLAY.CLOCK.VPLL_S1[0] => { N1 = 0x16 | M1 = 0x2 }
[0] 108.303452 MMIO32 W 0x614104 0x00020016 PDISPLAY.CLOCK.VPLL_S1[0] <= { N1 = 0x16 | M1 = 0x2 }
[0] 108.303466 MMIO32 R 0x614108 0x2007000e PDISPLAY.CLOCK.VPLL_S2[0] => { N2 = 0xe | M2 = 0x7 | P = 0x2 }
[0] 108.303479 MMIO32 W 0x614108 0x2007000e PDISPLAY.CLOCK.VPLL_S2[0] <= { N2 = 0xe | M2 = 0x7 | P = 0x2 }
[0] 108.303493 MMIO32 R 0x610ad0 0x00824414 PDISPLAY.CRTC_VAL[0].CLOCK[0] => 0x824414
[0] 108.303507 MMIO32 R 0x610b58 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL[0][0] => 0
[0] 108.303520 MMIO32 R 0x610b60 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL[0x1][0] => 0
[0] 108.303534 MMIO32 R 0x610b68 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL[0x2][0] => 0
[0] 108.303548 MMIO32 R 0x610794 0x00000000 PDISPLAY.SOR_VAL_MODE_CTRL[0][0] => 0
[0] 108.303562 MMIO32 R 0x61079c 0x00000101 PDISPLAY.SOR_VAL_MODE_CTRL[0x1][0] => 0x101
[0] 108.303578 MMIO32 R 0x610b58 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL[0][0] => 0
[0] 108.303592 MMIO32 R 0x610b60 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL[0x1][0] => 0
[0] 108.303605 MMIO32 R 0x610b68 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL[0x2][0] => 0
[0] 108.303619 MMIO32 R 0x610794 0x00000000 PDISPLAY.SOR_VAL_MODE_CTRL[0][0] => 0
[0] 108.303633 MMIO32 R 0x61079c 0x00000101 PDISPLAY.SOR_VAL_MODE_CTRL[0x1][0] => 0x101
---end then the script runs as expected---

So any hints on how to continue debugging this are appreciated.

Regards,

Hans
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