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From: Marc Zyngier <marc.zyngier@arm.com>
To: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Andrew Jones <drjones@redhat.com>,
	linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
	kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v2 17/17] arm64: KVM: vgic-v3: Do not save ICH_AP0Rn_EL2 for GICv2 emulation
Date: Fri, 4 Mar 2016 08:54:11 +0000	[thread overview]
Message-ID: <56D94D33.1020101@arm.com> (raw)
In-Reply-To: <20160303192154.GJ9634@cbox>

On 03/03/16 19:21, Christoffer Dall wrote:
> On Wed, Feb 17, 2016 at 04:40:49PM +0000, Marc Zyngier wrote:
>> The GICv3 specification mandates that ICH_AP0Rn_EL2 are set to
>> zero when running guests that use the memory mapped registers.
>>
>> This is fine, as we initialize all ICH_AP0Rn_EL2 registers to
>> zero, and restore them on entry. But it also means that we
>> do not need to save these registers on exit. Profit!
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>>  arch/arm64/kvm/hyp/vgic-v3-sr.c | 19 +++++++++++--------
>>  1 file changed, 11 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> index 5f12c57..c2f173d 100644
>> --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> @@ -202,14 +202,17 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
>>  			__gic_v3_set_lr(0, i);
>>  		}
>>  
>> -		switch (nr_pri_bits) {
>> -		case 7:
>> -			cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
>> -			cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
>> -		case 6:
>> -			cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
>> -		default:
>> -			cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
>> +		/* ICH_AP0Rn is only valid for SRE==1 */
>> +		if (cpu_if->vgic_sre & ICC_SRE_EL1_SRE) {
>> +			switch (nr_pri_bits) {
>> +			case 7:
>> +				cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
>> +				cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
>> +			case 6:
>> +				cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
>> +			default:
>> +				cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
>> +			}
>>  		}
>>  
>>  		switch (nr_pri_bits) {
>> -- 
>> 2.1.4
>>
> 
> Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
> 

Looks like this patch, despite working fine on A57+GIC500, introduces a
regression on an internal build of the AEMv8 model. I'm chasing the
modelling guys in order to find out about it. In the meantime, I'll keep
it on the back-burner, just in case.

Thanks.

	M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 17/17] arm64: KVM: vgic-v3: Do not save ICH_AP0Rn_EL2 for GICv2 emulation
Date: Fri, 4 Mar 2016 08:54:11 +0000	[thread overview]
Message-ID: <56D94D33.1020101@arm.com> (raw)
In-Reply-To: <20160303192154.GJ9634@cbox>

On 03/03/16 19:21, Christoffer Dall wrote:
> On Wed, Feb 17, 2016 at 04:40:49PM +0000, Marc Zyngier wrote:
>> The GICv3 specification mandates that ICH_AP0Rn_EL2 are set to
>> zero when running guests that use the memory mapped registers.
>>
>> This is fine, as we initialize all ICH_AP0Rn_EL2 registers to
>> zero, and restore them on entry. But it also means that we
>> do not need to save these registers on exit. Profit!
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>>  arch/arm64/kvm/hyp/vgic-v3-sr.c | 19 +++++++++++--------
>>  1 file changed, 11 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> index 5f12c57..c2f173d 100644
>> --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> @@ -202,14 +202,17 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
>>  			__gic_v3_set_lr(0, i);
>>  		}
>>  
>> -		switch (nr_pri_bits) {
>> -		case 7:
>> -			cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
>> -			cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
>> -		case 6:
>> -			cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
>> -		default:
>> -			cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
>> +		/* ICH_AP0Rn is only valid for SRE==1 */
>> +		if (cpu_if->vgic_sre & ICC_SRE_EL1_SRE) {
>> +			switch (nr_pri_bits) {
>> +			case 7:
>> +				cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
>> +				cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
>> +			case 6:
>> +				cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
>> +			default:
>> +				cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
>> +			}
>>  		}
>>  
>>  		switch (nr_pri_bits) {
>> -- 
>> 2.1.4
>>
> 
> Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
> 

Looks like this patch, despite working fine on A57+GIC500, introduces a
regression on an internal build of the AEMv8 model. I'm chasing the
modelling guys in order to find out about it. In the meantime, I'll keep
it on the back-burner, just in case.

Thanks.

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2016-03-04  8:54 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-17 16:40 [PATCH v2 00/17] KVM/ARM: Guest Entry/Exit optimizations Marc Zyngier
2016-02-17 16:40 ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 01/17] arm64: KVM: Switch the sys_reg search to be a binary search Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 02/17] ARM: KVM: Properly sort the invariant table Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 03/17] ARM: KVM: Enforce sorting of all CP tables Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 04/17] ARM: KVM: Rename struct coproc_reg::is_64 to is_64bit Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 05/17] ARM: KVM: Switch the CP reg search to be a binary search Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 06/17] KVM: arm/arm64: timer: Add active state caching Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 07/17] arm64: KVM: vgic-v2: Avoid accessing GICH registers Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-02 23:08   ` Christoffer Dall
2016-03-02 23:08     ` Christoffer Dall
2016-02-17 16:40 ` [PATCH v2 08/17] arm64: KVM: vgic-v2: Save maintenance interrupt state only if required Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-02 23:08   ` Christoffer Dall
2016-03-02 23:08     ` Christoffer Dall
2016-03-03  8:28     ` Marc Zyngier
2016-03-03  8:28       ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 09/17] arm64: KVM: vgic-v2: Move GICH_ELRSR saving to its own function Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-02 23:08   ` Christoffer Dall
2016-03-02 23:08     ` Christoffer Dall
2016-02-17 16:40 ` [PATCH v2 10/17] arm64: KVM: vgic-v2: Do not save an LR known to be empty Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-02 23:08   ` Christoffer Dall
2016-03-02 23:08     ` Christoffer Dall
2016-02-17 16:40 ` [PATCH v2 11/17] arm64: KVM: vgic-v2: Only wipe LRs on vcpu exit Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-02 23:08   ` Christoffer Dall
2016-03-02 23:08     ` Christoffer Dall
2016-03-03  8:14     ` Marc Zyngier
2016-03-03  8:14       ` Marc Zyngier
2016-03-03 15:58     ` Marc Zyngier
2016-03-03 15:58       ` Marc Zyngier
2016-03-04 11:36       ` Christoffer Dall
2016-03-04 11:36         ` Christoffer Dall
2016-03-04 11:45         ` Marc Zyngier
2016-03-04 11:45           ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 12/17] arm64: KVM: vgic-v2: Make GICD_SGIR quicker to hit Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-02 23:08   ` Christoffer Dall
2016-03-02 23:08     ` Christoffer Dall
2016-02-17 16:40 ` [PATCH v2 13/17] arm64: KVM: vgic-v3: Avoid accessing ICH registers Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-02-17 16:40 ` [PATCH v2 14/17] arm64: KVM: vgic-v3: Save maintenance interrupt state only if required Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-03 19:21   ` Christoffer Dall
2016-03-03 19:21     ` Christoffer Dall
2016-02-17 16:40 ` [PATCH v2 15/17] arm64: KVM: vgic-v3: Do not save an LR known to be empty Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-03 19:21   ` Christoffer Dall
2016-03-03 19:21     ` Christoffer Dall
2016-02-17 16:40 ` [PATCH v2 16/17] arm64: KVM: vgic-v3: Only wipe LRs on vcpu exit Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-03 19:21   ` Christoffer Dall
2016-03-03 19:21     ` Christoffer Dall
2016-02-17 16:40 ` [PATCH v2 17/17] arm64: KVM: vgic-v3: Do not save ICH_AP0Rn_EL2 for GICv2 emulation Marc Zyngier
2016-02-17 16:40   ` Marc Zyngier
2016-03-03 19:21   ` Christoffer Dall
2016-03-03 19:21     ` Christoffer Dall
2016-03-04  8:54     ` Marc Zyngier [this message]
2016-03-04  8:54       ` Marc Zyngier
2016-02-29  0:57 ` [PATCH v2 00/17] KVM/ARM: Guest Entry/Exit optimizations Mihai Claudiu Caraman
2016-02-29  0:57   ` Mihai Claudiu Caraman
2016-02-29  8:26   ` Marc Zyngier
2016-02-29  8:26     ` Marc Zyngier
2016-02-29 10:43     ` Mihai Claudiu Caraman
2016-02-29 10:43       ` Mihai Claudiu Caraman

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