[PATCH 0/6] MIPS: BMIPS: Random fixes for BMIPS5000/5200

[PATCH 0/6] MIPS: BMIPS: Random fixes for BMIPS5000/5200

[Florian Fainelli]

Hi all,

This patch series contains a bunch of fixes for the BMIPS5000 processor class.

The first 4 patches are addressing some functional and cosmetic issues, while
the last 2 patches fix the existing code to support BMIPS5200 processors.

Kevin, Jon, Jonas, please review!

These were tested on BCM7425 and BCM7435.

BMIPS5200 SMP patches will be submitted on top of this patch series

Florian Fainelli (6):
  MIPS: BMIPS: BMIPS5000 has I cache filing from D cache
  MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlier
  BMIPS: BMIPS: local_r4k___flush_cache_all needs to blast S-cache
  MIPS: BMIPS: Add cpu-feature-overrides.h
  MIPS: BMIPS: Pretty print BMIPS5200 processor name
  MIPS: BMIPS: Fix PRID_IMP_BMIPS5000 masking for BMIPS5200

 .../include/asm/mach-bmips/cpu-feature-overrides.h |   14 ++++++++++++++
 arch/mips/kernel/bmips_vec.S                       |    9 +++++++--
 arch/mips/kernel/cpu-probe.c                       |    5 ++++-
 arch/mips/mm/c-r4k.c                               |   13 +++++++++++--
 4 files changed, 36 insertions(+), 5 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h

[PATCH 1/6] MIPS: BMIPS: BMIPS5000 has I cache filing from D cache

[Florian Fainelli]

BMIPS5000 and BMIPS52000 processors have their I-cache filling from the
D-cache. Since BMIPS_GENERIC does not provide (yet) a
cpu-feature-overrides.h file, this was not set anywhere, so make sure
the R4K cache detection takes care of that.

Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/mips/mm/c-r4k.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index caac3d7..30459aa 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1307,6 +1307,10 @@ static void probe_pcache(void)
 		c->icache.flags |= MIPS_CACHE_IC_F_DC;
 		break;
 
+	case CPU_BMIPS5000:
+		c->icache.flags |= MIPS_CACHE_IC_F_DC;
+		break;
+
 	case CPU_LOONGSON2:
 		/*
 		 * LOONGSON2 has 4 way icache, but when using indexed cache op,
-- 
1.7.1

[PATCH 2/6] MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlier

[Florian Fainelli]

BMIPS5000 and BMIPS5200 processor have no D cache aliases, and this is
properly handled by the per-CPU override added at the end of
r4k_cache_init(), the problem is that the output of probe_pcache()
disagrees with that, since this is too late:

Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes

With the change moved earlier, we now have a consistent output with the
settings we are intending to have:

Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, VIPT, no aliases, linesize 32 bytes

Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/mips/mm/c-r4k.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 30459aa..6bf6c6b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1309,6 +1309,8 @@ static void probe_pcache(void)
 
 	case CPU_BMIPS5000:
 		c->icache.flags |= MIPS_CACHE_IC_F_DC;
+		/* Cache aliases are handled in hardware; allow HIGHMEM */
+		c->dcache.flags &= ~MIPS_CACHE_ALIASES;
 		break;
 
 	case CPU_LOONGSON2:
@@ -1748,8 +1750,6 @@ void r4k_cache_init(void)
 		flush_icache_range = (void *)b5k_instruction_hazard;
 		local_flush_icache_range = (void *)b5k_instruction_hazard;
 
-		/* Cache aliases are handled in hardware; allow HIGHMEM */
-		current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
 
 		/* Optimization: an L2 flush implicitly flushes the L1 */
 		current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
-- 
1.7.1

[PATCH 3/6] BMIPS: BMIPS: local_r4k___flush_cache_all needs to blast S-cache

[Florian Fainelli]

local_r4k___flush_cache_all() is missing a special check for BMIPS5000
processors, we need to blast the S-cache, just like other MTI processors
since we have an inclusive cache. We also need an additional __sync() to
make sure this is completed.

Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/mips/mm/c-r4k.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6bf6c6b..d4dfb21 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -447,6 +447,11 @@ static inline void local_r4k___flush_cache_all(void * args)
 		r4k_blast_scache();
 		break;
 
+	case CPU_BMIPS5000:
+		r4k_blast_scache();
+		__sync();
+		break;
+
 	default:
 		r4k_blast_dcache();
 		r4k_blast_icache();
-- 
1.7.1

[PATCH 4/6] MIPS: BMIPS: Add cpu-feature-overrides.h

[Florian Fainelli]

BMIPS_GENERIC being multiplatform and intended to support BMIPS3200,
BMIPS3300, BMIPS4350, BMIPS4380 and BMIPS5000-class processors, there is
not much more we can put in there since they do not share the same I and
D cache line sizes at all (doubled for every new generation
essentially), some processors have a S-cache, some don't, some have a
FPU, some don't.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 .../include/asm/mach-bmips/cpu-feature-overrides.h |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h

diff --git a/arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h
new file mode 100644
index 0000000..fa0583e
--- /dev/null
+++ b/arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_MACH_BMIPS_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BMIPS_CPU_FEATURE_OVERRIDES_H
+
+/* Invariants across all BMIPS processors */
+#define cpu_has_vtag_icache		0
+#define cpu_icache_snoops_remote_store	1
+
+/* Processor ISA compatibility is MIPS32R1 */
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+
+#endif /* __ASM_MACH_BMIPS_CPU_FEATURE_OVERRIDES_H */
-- 
1.7.1

[PATCH 5/6] MIPS: BMIPS: Pretty print BMIPS5200 processor name

[Florian Fainelli]

Just to ease debugging of multiplatform kernel, make sure we print
"Broadcom BMIPS5200" for the BMIPS5200 implementation instead of
Broadcom BMIPS5000.

Fixes: 68e6a78373a6d ("MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/mips/kernel/cpu-probe.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b725b71..f8cc8ec 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1445,7 +1445,10 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 	case PRID_IMP_BMIPS5000:
 	case PRID_IMP_BMIPS5200:
 		c->cputype = CPU_BMIPS5000;
-		__cpu_name[cpu] = "Broadcom BMIPS5000";
+		if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
+			__cpu_name[cpu] = "Broadcom BMIPS5200";
+		else
+			__cpu_name[cpu] = "Broadcom BMIPS5000";
 		set_elf_platform(cpu, "bmips5000");
 		c->options |= MIPS_CPU_ULRI;
 		break;
-- 
1.7.1

[PATCH 6/6] MIPS: BMIPS: Fix PRID_IMP_BMIPS5000 masking for BMIPS5200

[Florian Fainelli]

BMIPS5000 have a PrID value of 0x5A00 and BMIPS5200 have a PrID value of
0x5B00, which, masked with 0x5A00, returns 0x5A00. Update all conditionals on
the PrID to cover both variants since we are going to need this to enable
BMIPS5200 SMP. The existing check, masking with 0xFF00 would not cover
BMIPS5200 at all.

Fixes: 68e6a78373a6d ("MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)")
Fixes: 6465460c92a85 ("MIPS: BMIPS: change compile time checks to runtime checks")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/mips/kernel/bmips_vec.S |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index 8649507..d9495f3 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -93,7 +93,8 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
 #if defined(CONFIG_CPU_BMIPS5000)
 	mfc0	k0, CP0_PRID
 	li	k1, PRID_IMP_BMIPS5000
-	andi	k0, 0xff00
+	/* mask with PRID_IMP_BMIPS5000 to cover both variants */
+	andi	k0, PRID_IMP_BMIPS5000
 	bne	k0, k1, 1f
 
 	/* if we're not on core 0, this must be the SMP boot signal */
@@ -166,10 +167,12 @@ bmips_smp_entry:
 2:
 #endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
 #if defined(CONFIG_CPU_BMIPS5000)
-	/* set exception vector base */
+	/* mask with PRID_IMP_BMIPS5000 to cover both variants */
 	li	k1, PRID_IMP_BMIPS5000
+	andi	k0, PRID_IMP_BMIPS5000
 	bne	k0, k1, 3f
 
+	/* set exception vector base */
 	la	k0, ebase
 	lw	k0, 0(k0)
 	mtc0	k0, $15, 1
@@ -263,6 +266,8 @@ LEAF(bmips_enable_xks01)
 #endif /* CONFIG_CPU_BMIPS4380 */
 #if defined(CONFIG_CPU_BMIPS5000)
 	li	t1, PRID_IMP_BMIPS5000
+	/* mask with PRID_IMP_BMIPS5000 to cover both variants */
+	andi	t2, PRID_IMP_BMIPS5000
 	bne	t2, t1, 2f
 
 	mfc0	t0, $22, 5
-- 
1.7.1

Re: [PATCH 0/6] MIPS: BMIPS: Random fixes for BMIPS5000/5200

[Florian Fainelli]

Le 29/01/2016 21:17, Florian Fainelli a écrit :
> Hi all,
> 
> This patch series contains a bunch of fixes for the BMIPS5000 processor class.
> 
> The first 4 patches are addressing some functional and cosmetic issues, while
> the last 2 patches fix the existing code to support BMIPS5200 processors.
> 
> Kevin, Jon, Jonas, please review!
> 
> These were tested on BCM7425 and BCM7435.
> 
> BMIPS5200 SMP patches will be submitted on top of this patch series

Ralf, can you queue these patches for 4.6? Thank you!

> 
> Florian Fainelli (6):
>   MIPS: BMIPS: BMIPS5000 has I cache filing from D cache
>   MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlier
>   BMIPS: BMIPS: local_r4k___flush_cache_all needs to blast S-cache
>   MIPS: BMIPS: Add cpu-feature-overrides.h
>   MIPS: BMIPS: Pretty print BMIPS5200 processor name
>   MIPS: BMIPS: Fix PRID_IMP_BMIPS5000 masking for BMIPS5200
> 
>  .../include/asm/mach-bmips/cpu-feature-overrides.h |   14 ++++++++++++++
>  arch/mips/kernel/bmips_vec.S                       |    9 +++++++--
>  arch/mips/kernel/cpu-probe.c                       |    5 ++++-
>  arch/mips/mm/c-r4k.c                               |   13 +++++++++++--
>  4 files changed, 36 insertions(+), 5 deletions(-)
>  create mode 100644 arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h
> 


-- 
Florian

Re: [PATCH 0/6] MIPS: BMIPS: Random fixes for BMIPS5000/5200

[Florian Fainelli]

Le 28/03/2016 18:35, Florian Fainelli a écrit :
> Le 29/01/2016 21:17, Florian Fainelli a écrit :
>> Hi all,
>>
>> This patch series contains a bunch of fixes for the BMIPS5000 processor class.
>>
>> The first 4 patches are addressing some functional and cosmetic issues, while
>> the last 2 patches fix the existing code to support BMIPS5200 processors.
>>
>> Kevin, Jon, Jonas, please review!
>>
>> These were tested on BCM7425 and BCM7435.
>>
>> BMIPS5200 SMP patches will be submitted on top of this patch series
> 
> Ralf, can you queue these patches for 4.6? Thank you!

Ping? Any chance we can get these patches in 4.6?

> 
>>
>> Florian Fainelli (6):
>>   MIPS: BMIPS: BMIPS5000 has I cache filing from D cache
>>   MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlier
>>   BMIPS: BMIPS: local_r4k___flush_cache_all needs to blast S-cache
>>   MIPS: BMIPS: Add cpu-feature-overrides.h
>>   MIPS: BMIPS: Pretty print BMIPS5200 processor name
>>   MIPS: BMIPS: Fix PRID_IMP_BMIPS5000 masking for BMIPS5200
>>
>>  .../include/asm/mach-bmips/cpu-feature-overrides.h |   14 ++++++++++++++
>>  arch/mips/kernel/bmips_vec.S                       |    9 +++++++--
>>  arch/mips/kernel/cpu-probe.c                       |    5 ++++-
>>  arch/mips/mm/c-r4k.c                               |   13 +++++++++++--
>>  4 files changed, 36 insertions(+), 5 deletions(-)
>>  create mode 100644 arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h
>>
> 
> 


-- 
Florian