All of lore.kernel.org
 help / color / mirror / Atom feed
From: Kefeng Wang <wangkefeng.wang@huawei.com>
To: Noam Camus <noamc@ezchip.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Heikki Krogerus <heikki.krogerus@linux.intel.com>,
	linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org,
	guohanjun@huawei.com, xuwei5@hisilicon.com
Subject: Re: [PATCH v2] serial: 8250_dw: fix wrong logic in dw8250_check_lcr()
Date: Tue, 5 Apr 2016 10:53:14 +0800	[thread overview]
Message-ID: <5703289A.5090505@huawei.com> (raw)
In-Reply-To: <1459824546-9942-1-git-send-email-wangkefeng.wang@huawei.com>

Please ignore, sorry for typos, and will resend.

On 2016/4/5 10:49, Kefeng Wang wrote:
> Commit cdcea058e510("serial: 8250_dw: Avoid serial_outx code duplicate
> with new dw8250_check_lcr()") introduce a wrong logic when write val to
> LCR reg. When CONFIG_64BIT enabled, __raw_writeq is used unconditionally.
> 
> The __raw_readq/__raw_writeq is introduced by commit bca2092d7897("serial:
> 8250_dw: Use 64-bit access for OCTEON") for OCTEON, so for !PORT_OCTEON,
> we better to use coincident write func.
> 
> Fixes: cdcea058e510("serial: 8250_dw: Avoid serial_outx code duplicate with new dw8250_check_lcr()")
> Signe:-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  drivers/tty/serial/8250/8250_dw.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index a3fb95d..003ce60 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -103,16 +103,14 @@ static void dw8250_check_lcr(struct uart_port *p, int value)
>  
>  		dw8250_force_idle(p);
>  
> -#ifdef CONFIG_64BIT
> -		__raw_writeq(value & 0xff, offset);
> -#else
> -		if (p->iotype == UPIO_MEM32)
> +		if (IS_ENABLED(CONFIG_64BIT) && p->type == PORT_OCTEON)
> +			__raw_writeq(value & 0xff, offset);
> +		else if (p->iotype == UPIO_MEM32)
>  			writel(value, offset);
>  		else if (p->iotype == UPIO_MEM32BE)
>  			iowrite32be(value, offset);
>  		else
>  			writeb(value, offset);
> -#endif
>  	}
>  	/*
>  	 * FIXME: this deadlocks if port->lock is already held
> 

WARNING: multiple messages have this Message-ID (diff)
From: Kefeng Wang <wangkefeng.wang@huawei.com>
To: Noam Camus <noamc@ezchip.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Heikki Krogerus <heikki.krogerus@linux.intel.com>,
	<linux-serial@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<guohanjun@huawei.com>, <xuwei5@hisilicon.com>
Subject: Re: [PATCH v2] serial: 8250_dw: fix wrong logic in dw8250_check_lcr()
Date: Tue, 5 Apr 2016 10:53:14 +0800	[thread overview]
Message-ID: <5703289A.5090505@huawei.com> (raw)
In-Reply-To: <1459824546-9942-1-git-send-email-wangkefeng.wang@huawei.com>

Please ignore, sorry for typos, and will resend.

On 2016/4/5 10:49, Kefeng Wang wrote:
> Commit cdcea058e510("serial: 8250_dw: Avoid serial_outx code duplicate
> with new dw8250_check_lcr()") introduce a wrong logic when write val to
> LCR reg. When CONFIG_64BIT enabled, __raw_writeq is used unconditionally.
> 
> The __raw_readq/__raw_writeq is introduced by commit bca2092d7897("serial:
> 8250_dw: Use 64-bit access for OCTEON") for OCTEON, so for !PORT_OCTEON,
> we better to use coincident write func.
> 
> Fixes: cdcea058e510("serial: 8250_dw: Avoid serial_outx code duplicate with new dw8250_check_lcr()")
> Signe:-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  drivers/tty/serial/8250/8250_dw.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index a3fb95d..003ce60 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -103,16 +103,14 @@ static void dw8250_check_lcr(struct uart_port *p, int value)
>  
>  		dw8250_force_idle(p);
>  
> -#ifdef CONFIG_64BIT
> -		__raw_writeq(value & 0xff, offset);
> -#else
> -		if (p->iotype == UPIO_MEM32)
> +		if (IS_ENABLED(CONFIG_64BIT) && p->type == PORT_OCTEON)
> +			__raw_writeq(value & 0xff, offset);
> +		else if (p->iotype == UPIO_MEM32)
>  			writel(value, offset);
>  		else if (p->iotype == UPIO_MEM32BE)
>  			iowrite32be(value, offset);
>  		else
>  			writeb(value, offset);
> -#endif
>  	}
>  	/*
>  	 * FIXME: this deadlocks if port->lock is already held
> 

  reply	other threads:[~2016-04-05  2:53 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-05  2:49 [PATCH v2] serial: 8250_dw: fix wrong logic in dw8250_check_lcr() Kefeng Wang
2016-04-05  2:49 ` Kefeng Wang
2016-04-05  2:53 ` Kefeng Wang [this message]
2016-04-05  2:53   ` Kefeng Wang
2016-04-05  2:59 ` kbuild test robot
2016-04-05  2:59   ` kbuild test robot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5703289A.5090505@huawei.com \
    --to=wangkefeng.wang@huawei.com \
    --cc=andriy.shevchenko@linux.intel.com \
    --cc=gregkh@linuxfoundation.org \
    --cc=guohanjun@huawei.com \
    --cc=heikki.krogerus@linux.intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-serial@vger.kernel.org \
    --cc=noamc@ezchip.com \
    --cc=xuwei5@hisilicon.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.