From: Murali Karicheri <m-karicheri2@ti.com>
To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Hot reset in downstream direction (RC to EP)
Date: Fri, 8 Apr 2016 17:51:17 -0400 [thread overview]
Message-ID: <570827D5.5060201@ti.com> (raw)
I see that hot reset is something the RC port initiate to have EP reset
through link management.
==========================================================================
PCIe reset sequences – The PCI Express protocol specifies a hot reset
mechanism, where downstream components reset through link notification.
Root ports should validate that this mechanism can be applied and the
hot reset indication is properly detected by a remote device.
Endpoint applications should determine the level of chip reset desired
in case of hot reset detection on the link to validate proper functionality.
===========================================================================
Does this happen during the enumeration? As this goes in in band, the EP's
link should be up. Can someone tell me what are the triggering points for
this from RC to EP? Does Linux RC support this? It is supposed to a bit
in RC's bridge configuration space that triggers this reset.
--
Murali Karicheri
Linux Kernel, Keystone
next reply other threads:[~2016-04-08 21:51 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-08 21:51 Murali Karicheri [this message]
2016-04-12 18:28 ` Hot reset in downstream direction (RC to EP) L H
2016-04-12 19:44 ` Murali Karicheri
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