Re: Hot reset in downstream direction (RC to EP)

[Murali Karicheri <m-karicheri2@ti.com>]

On 04/12/2016 02:28 PM, L H wrote:
> I've never observed a hot reset during enumeration.  One of the
> possible triggers for the RC to issue a hot reset is after receipt of
> a fatal AER message (assuming AER is enabled).
> 
Lance,

Ok. Thanks for the response.

Murali

> Lance
> 
> On Fri, Apr 8, 2016 at 4:51 PM, Murali Karicheri <m-karicheri2@ti.com> wrote:
>> I see that hot reset is something the RC port initiate to have EP reset
>> through link management.
>>
>> ==========================================================================
>> PCIe reset sequences – The PCI Express protocol specifies a hot reset
>> mechanism, where downstream components reset through link notification.
>> Root ports should validate that this mechanism can be applied and the
>> hot reset indication is properly detected by a remote device.
>> Endpoint applications should determine the level of chip reset desired
>> in case of hot reset detection on the link to validate proper functionality.
>> ===========================================================================
>>
>> Does this happen during the enumeration? As this goes in in band, the EP's
>> link should be up. Can someone tell me what are the triggering points for
>> this from RC to EP? Does Linux RC support this? It is supposed to a bit
>> in RC's bridge configuration space that triggers this reset.
>>
>> --
>> Murali Karicheri
>> Linux Kernel, Keystone
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-- 
Murali Karicheri
Linux Kernel, Keystone