From: Stephen Warren <swarren@wwwdotorg.org>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Alexandre Courbot <gnurou@gmail.com>,
linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v4 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs
Date: Mon, 11 Apr 2016 11:38:49 -0600 [thread overview]
Message-ID: <570BE129.40907@wwwdotorg.org> (raw)
In-Reply-To: <1460131994-24493-1-git-send-email-thierry.reding@gmail.com>
On 04/08/2016 10:13 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Changes to the pad controller device tree binding have required that
> each lane be associated with a separate PHY. Update the PCI host bridge
> device tree binding to allow each root port to define the list of PHYs
> required to drive the lanes associated with it.
I think the feedback I gave on v3 still applies here (I'm talking about
the comments on the patch, not the commit description).
http://www.spinics.net/lists/linux-pci/msg49718.html
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v4 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs
Date: Mon, 11 Apr 2016 11:38:49 -0600 [thread overview]
Message-ID: <570BE129.40907@wwwdotorg.org> (raw)
In-Reply-To: <1460131994-24493-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 04/08/2016 10:13 AM, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Changes to the pad controller device tree binding have required that
> each lane be associated with a separate PHY. Update the PCI host bridge
> device tree binding to allow each root port to define the list of PHYs
> required to drive the lanes associated with it.
I think the feedback I gave on v3 still applies here (I'm talking about
the comments on the patch, not the commit description).
http://www.spinics.net/lists/linux-pci/msg49718.html
next prev parent reply other threads:[~2016-04-11 17:38 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-08 16:13 [PATCH v4 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs Thierry Reding
2016-04-08 16:13 ` [PATCH v4 2/2] PCI: tegra: Support " Thierry Reding
2016-04-08 16:13 ` Thierry Reding
2016-04-08 18:05 ` Bjorn Helgaas
2016-04-08 18:05 ` Bjorn Helgaas
2016-04-11 11:11 ` Thierry Reding
2016-04-11 17:41 ` Stephen Warren
2016-04-08 16:48 ` [PATCH v4 1/2] dt-bindings: pci: tegra: Update for " Bjorn Helgaas
2016-04-08 16:48 ` Bjorn Helgaas
2016-04-11 10:23 ` Thierry Reding
2016-04-11 10:23 ` Thierry Reding
2016-04-08 19:11 ` Bjorn Helgaas
2016-04-08 19:11 ` Bjorn Helgaas
2016-04-11 11:26 ` Thierry Reding
2016-04-11 11:26 ` Thierry Reding
2016-04-11 16:55 ` Stephen Warren
2016-04-11 16:55 ` Stephen Warren
2016-04-11 17:38 ` Stephen Warren [this message]
2016-04-11 17:38 ` Stephen Warren
2016-04-13 16:23 ` Thierry Reding
2016-04-13 16:23 ` Thierry Reding
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