diff for duplicates of <57151048.2090806@wwwdotorg.org> diff --git a/a/1.txt b/N1/1.txt index 5e737d7..0f843a3 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On 04/18/2016 08:51 AM, Thierry Reding wrote: -> From: Thierry Reding <treding@nvidia.com> +> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > The XUSB pad controller allows PCIe lanes to be controlled individually, > providing fine-grained control over their power state. Previous attempts @@ -13,4 +13,4 @@ On 04/18/2016 08:51 AM, Thierry Reding wrote: > up and down all of the lanes as necessary. The series, -Acked-by: Stephen Warren <swarren@nvidia.com> +Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> diff --git a/a/content_digest b/N1/content_digest index be85ca5..1e8da0d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,18 @@ "ref\01460991105-22861-1-git-send-email-thierry.reding@gmail.com\0" - "From\0Stephen Warren <swarren@wwwdotorg.org>\0" + "ref\01460991105-22861-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>\0" "Subject\0Re: [PATCH v5 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs\0" "Date\0Mon, 18 Apr 2016 10:50:16 -0600\0" - "To\0Thierry Reding <thierry.reding@gmail.com>" - " Bjorn Helgaas <bhelgaas@google.com>\0" - "Cc\0Alexandre Courbot <gnurou@gmail.com>" - linux-tegra@vger.kernel.org - linux-pci@vger.kernel.org - " devicetree@vger.kernel.org\0" + "To\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>" + " Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>\0" + "Cc\0Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>" + linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "On 04/18/2016 08:51 AM, Thierry Reding wrote:\n" - "> From: Thierry Reding <treding@nvidia.com>\n" + "> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" ">\n" "> The XUSB pad controller allows PCIe lanes to be controlled individually,\n" "> providing fine-grained control over their power state. Previous attempts\n" @@ -25,6 +26,6 @@ "> up and down all of the lanes as necessary.\n" "\n" "The series,\n" - Acked-by: Stephen Warren <swarren@nvidia.com> + Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> -589de535aea15583e0ba1ab8f95738deadb77005a38d04ae5596b174d752198a +f00a2bb319adc42b230c461f7186bb1955bb278870d422ed6378fc26464898a4
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