From: Stephen Warren <swarren@wwwdotorg.org>
To: Thierry Reding <thierry.reding@gmail.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Alexandre Courbot <gnurou@gmail.com>,
linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v5 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs
Date: Mon, 18 Apr 2016 10:50:16 -0600 [thread overview]
Message-ID: <57151048.2090806@wwwdotorg.org> (raw)
In-Reply-To: <1460991105-22861-1-git-send-email-thierry.reding@gmail.com>
On 04/18/2016 08:51 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The XUSB pad controller allows PCIe lanes to be controlled individually,
> providing fine-grained control over their power state. Previous attempts
> at describing the XUSB pad controller in DT had erroneously assumed that
> all PCIe lanes were driven by the same PHY, and hence the PCI host
> controller would reference only a single PHY.
>
> Moving to a representation of per-lane PHYs requires that the operating
> system driver for the PCI host controller have access to the set of PHY
> devices that make up the connection of each root port in order to power
> up and down all of the lanes as necessary.
The series,
Acked-by: Stephen Warren <swarren@nvidia.com>
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Cc: Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v5 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs
Date: Mon, 18 Apr 2016 10:50:16 -0600 [thread overview]
Message-ID: <57151048.2090806@wwwdotorg.org> (raw)
In-Reply-To: <1460991105-22861-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 04/18/2016 08:51 AM, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> The XUSB pad controller allows PCIe lanes to be controlled individually,
> providing fine-grained control over their power state. Previous attempts
> at describing the XUSB pad controller in DT had erroneously assumed that
> all PCIe lanes were driven by the same PHY, and hence the PCI host
> controller would reference only a single PHY.
>
> Moving to a representation of per-lane PHYs requires that the operating
> system driver for the PCI host controller have access to the set of PHY
> devices that make up the connection of each root port in order to power
> up and down all of the lanes as necessary.
The series,
Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
next prev parent reply other threads:[~2016-04-18 16:50 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-18 14:51 [PATCH v5 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs Thierry Reding
2016-04-18 14:51 ` [PATCH v5 2/2] PCI: tegra: Support " Thierry Reding
2016-04-18 14:51 ` Thierry Reding
2016-04-28 13:38 ` Thierry Reding
2016-04-28 13:38 ` Thierry Reding
2016-04-28 14:50 ` Bjorn Helgaas
2016-04-28 14:50 ` Bjorn Helgaas
2016-04-28 18:56 ` Bjorn Helgaas
2016-04-28 18:56 ` Bjorn Helgaas
2016-04-18 14:54 ` [PATCH v5 1/2] dt-bindings: pci: tegra: Update for " Thierry Reding
2016-04-18 16:50 ` Stephen Warren [this message]
2016-04-18 16:50 ` Stephen Warren
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