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* [PATCH v3] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf
@ 2016-04-21 11:23 tim.gore
  2016-04-21 11:36 ` Michel Thierry
  2016-04-21 17:59 ` ✗ Fi.CI.BAT: failure for drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf (rev3) Patchwork
  0 siblings, 2 replies; 4+ messages in thread
From: tim.gore @ 2016-04-21 11:23 UTC (permalink / raw)
  To: intel-gfx

From: Tim Gore <tim.gore@intel.com>

This patch applies a performance enhancement workaround
based on analysis of DX and OCL S-Curve workloads. We
increase the General Priority Credits for L3SQ from the
hardware default of 56 to the max value 62, and decrease
the High Priority credits from 8 to 2.

v2: Only apply to B0 onwards

v3: Move w/a to per engine init, ie bxt_init_workarounds

Signed-off-by: Tim Gore <tim.gore@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c21b71c..efd36c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6074,6 +6074,7 @@ enum skl_disp_power_wells {
 
 #define GEN8_L3SQCREG1				_MMIO(0xB100)
 #define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
+#define  BXT_WA_L3SQCREG1_DEFAULT		0xF84000
 
 #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 245386e..f6e8e7e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1180,6 +1180,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 			return ret;
 	}
 
+	/* WaProgramL3SqcReg1DefaultForPerf:bxt */
+	if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
+		I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT);
+
 	return 0;
 }
 
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH v3] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf
  2016-04-21 11:23 [PATCH v3] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf tim.gore
@ 2016-04-21 11:36 ` Michel Thierry
  2016-04-21 17:59 ` ✗ Fi.CI.BAT: failure for drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf (rev3) Patchwork
  1 sibling, 0 replies; 4+ messages in thread
From: Michel Thierry @ 2016-04-21 11:36 UTC (permalink / raw)
  To: tim.gore, intel-gfx

On 4/21/2016 12:23 PM, tim.gore@intel.com wrote:
> From: Tim Gore <tim.gore@intel.com>
>
> This patch applies a performance enhancement workaround
> based on analysis of DX and OCL S-Curve workloads. We
> increase the General Priority Credits for L3SQ from the
> hardware default of 56 to the max value 62, and decrease
> the High Priority credits from 8 to 2.
>
> v2: Only apply to B0 onwards
>
> v3: Move w/a to per engine init, ie bxt_init_workarounds
>
> Signed-off-by: Tim Gore <tim.gore@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 1 +
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
>   2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c21b71c..efd36c3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6074,6 +6074,7 @@ enum skl_disp_power_wells {
>
>   #define GEN8_L3SQCREG1				_MMIO(0xB100)
>   #define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
> +#define  BXT_WA_L3SQCREG1_DEFAULT		0xF84000
>
>   #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
>   #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 245386e..f6e8e7e 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1180,6 +1180,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>   			return ret;
>   	}
>
> +	/* WaProgramL3SqcReg1DefaultForPerf:bxt */
> +	if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
> +		I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT);
> +
>   	return 0;
>   }
>
>

lgtm,

Reviewed-by: Michel Thierry <michel.thierry@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf (rev3)
  2016-04-21 11:23 [PATCH v3] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf tim.gore
  2016-04-21 11:36 ` Michel Thierry
@ 2016-04-21 17:59 ` Patchwork
  1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2016-04-21 17:59 UTC (permalink / raw)
  To: tim.gore; +Cc: intel-gfx

== Series Details ==

Series: drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf (rev3)
URL   : https://patchwork.freedesktop.org/series/5990/
State : failure

== Summary ==

Series 5990v3 drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf
http://patchwork.freedesktop.org/api/1.0/series/5990/revisions/3/mbox/

Test drv_module_reload_basic:
                pass       -> INCOMPLETE (hsw-brixbox)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                fail       -> PASS       (ilk-hp8440p) UNSTABLE

bdw-nuci7        total:194  pass:182  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:194  pass:170  dwarn:0   dfail:0   fail:1   skip:23 
bsw-nuc-2        total:193  pass:153  dwarn:0   dfail:0   fail:0   skip:40 
byt-nuc          total:193  pass:155  dwarn:0   dfail:0   fail:0   skip:38 
hsw-brixbox      total:29   pass:27   dwarn:0   dfail:0   fail:0   skip:1  
hsw-gt2          total:194  pass:175  dwarn:0   dfail:0   fail:0   skip:19 
ilk-hp8440p      total:194  pass:137  dwarn:0   dfail:0   fail:0   skip:57 
ivb-t430s        total:194  pass:166  dwarn:0   dfail:0   fail:0   skip:28 
skl-i7k-2        total:194  pass:168  dwarn:0   dfail:0   fail:1   skip:25 
skl-nuci5        total:194  pass:183  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:193  pass:155  dwarn:0   dfail:0   fail:0   skip:38 
snb-x220t        total:193  pass:155  dwarn:0   dfail:0   fail:1   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_1978/

d5b5101bd09a7b7e48b1cd78fe8f8a40b21d4deb drm-intel-nightly: 2016y-04m-21d-16h-37m-06s UTC integration manifest
c68ba4a drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [PATCH v3] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf
@ 2016-04-22  8:46 tim.gore
  0 siblings, 0 replies; 4+ messages in thread
From: tim.gore @ 2016-04-22  8:46 UTC (permalink / raw)
  To: intel-gfx

From: Tim Gore <tim.gore@intel.com>

This patch applies a performance enhancement workaround
based on analysis of DX and OCL S-Curve workloads. We
increase the General Priority Credits for L3SQ from the
hardware default of 56 to the max value 62, and decrease
the High Priority credits from 8 to 2.

v2: Only apply to B0 onwards

v3: Move w/a to per engine init, ie bxt_init_workarounds

Signed-off-by: Tim Gore <tim.gore@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c21b71c..efd36c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6074,6 +6074,7 @@ enum skl_disp_power_wells {
 
 #define GEN8_L3SQCREG1				_MMIO(0xB100)
 #define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
+#define  BXT_WA_L3SQCREG1_DEFAULT		0xF84000
 
 #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 245386e..f6e8e7e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1180,6 +1180,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 			return ret;
 	}
 
+	/* WaProgramL3SqcReg1DefaultForPerf:bxt */
+	if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
+		I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT);
+
 	return 0;
 }
 
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
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2016-04-21 11:23 [PATCH v3] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf tim.gore
2016-04-21 11:36 ` Michel Thierry
2016-04-21 17:59 ` ✗ Fi.CI.BAT: failure for drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf (rev3) Patchwork
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2016-04-22  8:46 [PATCH v3] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf tim.gore

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