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From: Stefan Roese <sr-ynQEQJNshbs@public.gmane.org>
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Thomas Petazzoni
	<thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
	Gregory CLEMENT
	<gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
	Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
	Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
Subject: Re: [PATCH v6] spi: orion.c: Add direct access mode
Date: Mon, 2 May 2016 08:47:15 +0200	[thread overview]
Message-ID: <5726F7F3.9070700@denx.de> (raw)
In-Reply-To: <1461147068-4829-1-git-send-email-sr-ynQEQJNshbs@public.gmane.org>

On 20.04.2016 12:11, Stefan Roese wrote:
> This patch adds support for the direct write mode to the Orion SPI
> driver which is used on the Marvell Armada based SoCs. In this direct
> mode, all data written to (or read from) a specifically mapped MBus
> window (linked to one SPI chip-select on one of the SPI controllers)
> will be transferred directly to the SPI bus. Without the need to control
> the SPI registers in between. This can improve the SPI transfer rate in
> such cases.
> 
> Currently only the direct write mode is supported. This mode especially
> benefits from the SPI direct mode, as the data bytes are written
> head-to-head to the SPI bus, without any additional addresses, that
> are also written in the direct read mode.
> 
> One use-case for this direct write mode is, programming a FPGA bitstream
> image into the FPGA connected to the SPI bus at maximum speed.
> 
> This mode is described in chapter "22.5.2 Direct Write to SPI" in the
> Marvell Armada XP Functional Spec Datasheet.
> 
> It should be possible to support SPI-NOR and SPI-NAND devices via
> this direct access mode as well. But this needs further work, e.g.:
> - The mapping of the MBus window needs to get extended to span
>    the complete flash device size
> - The address / control data needs to get inserted into the SPI
>    controller registers
> 
> Signed-off-by: Stefan Roese <sr-ynQEQJNshbs@public.gmane.org>
> Cc: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> Cc: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> Cc: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Its been a while since v6 of this direct write access mode has been
posted. This is a gentle ping on its status.

Arnd / Mark, do you have any additional change requests or are you okay
with the current version?

Thanks,
Stefan
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WARNING: multiple messages have this Message-ID (diff)
From: sr@denx.de (Stefan Roese)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6] spi: orion.c: Add direct access mode
Date: Mon, 2 May 2016 08:47:15 +0200	[thread overview]
Message-ID: <5726F7F3.9070700@denx.de> (raw)
In-Reply-To: <1461147068-4829-1-git-send-email-sr@denx.de>

On 20.04.2016 12:11, Stefan Roese wrote:
> This patch adds support for the direct write mode to the Orion SPI
> driver which is used on the Marvell Armada based SoCs. In this direct
> mode, all data written to (or read from) a specifically mapped MBus
> window (linked to one SPI chip-select on one of the SPI controllers)
> will be transferred directly to the SPI bus. Without the need to control
> the SPI registers in between. This can improve the SPI transfer rate in
> such cases.
> 
> Currently only the direct write mode is supported. This mode especially
> benefits from the SPI direct mode, as the data bytes are written
> head-to-head to the SPI bus, without any additional addresses, that
> are also written in the direct read mode.
> 
> One use-case for this direct write mode is, programming a FPGA bitstream
> image into the FPGA connected to the SPI bus at maximum speed.
> 
> This mode is described in chapter "22.5.2 Direct Write to SPI" in the
> Marvell Armada XP Functional Spec Datasheet.
> 
> It should be possible to support SPI-NOR and SPI-NAND devices via
> this direct access mode as well. But this needs further work, e.g.:
> - The mapping of the MBus window needs to get extended to span
>    the complete flash device size
> - The address / control data needs to get inserted into the SPI
>    controller registers
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Mark Brown <broonie@kernel.org>

Its been a while since v6 of this direct write access mode has been
posted. This is a gentle ping on its status.

Arnd / Mark, do you have any additional change requests or are you okay
with the current version?

Thanks,
Stefan

  parent reply	other threads:[~2016-05-02  6:47 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-20 10:11 [PATCH v6] spi: orion.c: Add direct access mode Stefan Roese
2016-04-20 10:11 ` Stefan Roese
     [not found] ` <1461147068-4829-1-git-send-email-sr-ynQEQJNshbs@public.gmane.org>
2016-04-20 11:58   ` Gregory CLEMENT
2016-04-20 11:58     ` Gregory CLEMENT
     [not found]     ` <87k2jswky0.fsf-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2016-04-20 12:09       ` Stefan Roese
2016-04-20 12:09         ` Stefan Roese
     [not found]         ` <5717715D.6030701-ynQEQJNshbs@public.gmane.org>
2016-06-16  9:23           ` Gregory CLEMENT
2016-06-16  9:23             ` Gregory CLEMENT
     [not found]             ` <87d1nhbi83.fsf-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2016-06-16  9:42               ` Stefan Roese
2016-06-16  9:42                 ` Stefan Roese
2016-05-02  6:47   ` Stefan Roese [this message]
2016-05-02  6:47     ` Stefan Roese
     [not found]     ` <5726F7F3.9070700-ynQEQJNshbs@public.gmane.org>
2016-05-02  7:28       ` Arnd Bergmann
2016-05-02  7:28         ` Arnd Bergmann
2016-05-02 10:33         ` Stefan Roese
2016-05-02 10:33           ` Stefan Roese
2016-05-02 15:40         ` Mark Brown
2016-05-02 15:40           ` Mark Brown

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