* [PATCH] iommu/arm-smmu: clear cache lock bit of ACR
@ 2016-05-03 10:15 ` Peng Fan
0 siblings, 0 replies; 9+ messages in thread
From: Peng Fan @ 2016-05-03 10:15 UTC (permalink / raw)
To: will.deacon-5wv7dgnIgG8
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
van.freenix-Re5JQEeQqe8AvxtiuMwx3w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
According MMU-500 TRM, section 3.7.1 Auxiliary Control registers,
You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
need clear CACHE_LOCK bit of ACR register first.
Signed-off-by: Peng Fan <van.freenix-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
Cc: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
---
Hi Will,
Patch based on iommu/devel branch.
drivers/iommu/arm-smmu.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index acff332..d094a5a 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -98,6 +98,9 @@
#define sCR0_BSU_SHIFT 14
#define sCR0_BSU_MASK 0x3
+/* Auxiliary Configuration register */
+#define ARM_SMMU_GR0_sACR 0x10
+
/* Identification registers */
#define ARM_SMMU_GR0_ID0 0x20
#define ARM_SMMU_GR0_ID1 0x24
@@ -235,6 +238,8 @@
#define ARM_MMU500_ACTLR_CPRE (1 << 1)
+#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
+
#define CB_PAR_F (1 << 0)
#define ATSR_ACTIVE (1 << 0)
@@ -1506,6 +1511,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
}
+ /*
+ * Before clearing ARM_MMU500_ACTLR_CPRE, need to
+ * clear CACHE_LOCK bit of ACR first.
+ */
+ if (smmu->model == ARM_MMU500) {
+ reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
+ reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
+ writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
+ }
+
/* Make sure all context banks are disabled and clear CB_FSR */
for (i = 0; i < smmu->num_context_banks; ++i) {
cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
--
2.6.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH] iommu/arm-smmu: clear cache lock bit of ACR
@ 2016-05-03 10:15 ` Peng Fan
0 siblings, 0 replies; 9+ messages in thread
From: Peng Fan @ 2016-05-03 10:15 UTC (permalink / raw)
To: will.deacon
Cc: robin.murphy, joro, linux-arm-kernel, iommu, linux-kernel,
van.freenix
According MMU-500 TRM, section 3.7.1 Auxiliary Control registers,
You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
need clear CACHE_LOCK bit of ACR register first.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
---
Hi Will,
Patch based on iommu/devel branch.
drivers/iommu/arm-smmu.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index acff332..d094a5a 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -98,6 +98,9 @@
#define sCR0_BSU_SHIFT 14
#define sCR0_BSU_MASK 0x3
+/* Auxiliary Configuration register */
+#define ARM_SMMU_GR0_sACR 0x10
+
/* Identification registers */
#define ARM_SMMU_GR0_ID0 0x20
#define ARM_SMMU_GR0_ID1 0x24
@@ -235,6 +238,8 @@
#define ARM_MMU500_ACTLR_CPRE (1 << 1)
+#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
+
#define CB_PAR_F (1 << 0)
#define ATSR_ACTIVE (1 << 0)
@@ -1506,6 +1511,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
}
+ /*
+ * Before clearing ARM_MMU500_ACTLR_CPRE, need to
+ * clear CACHE_LOCK bit of ACR first.
+ */
+ if (smmu->model == ARM_MMU500) {
+ reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
+ reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
+ writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
+ }
+
/* Make sure all context banks are disabled and clear CB_FSR */
for (i = 0; i < smmu->num_context_banks; ++i) {
cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
--
2.6.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH] iommu/arm-smmu: clear cache lock bit of ACR
@ 2016-05-03 10:15 ` Peng Fan
0 siblings, 0 replies; 9+ messages in thread
From: Peng Fan @ 2016-05-03 10:15 UTC (permalink / raw)
To: linux-arm-kernel
According MMU-500 TRM, section 3.7.1 Auxiliary Control registers,
You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
need clear CACHE_LOCK bit of ACR register first.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
---
Hi Will,
Patch based on iommu/devel branch.
drivers/iommu/arm-smmu.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index acff332..d094a5a 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -98,6 +98,9 @@
#define sCR0_BSU_SHIFT 14
#define sCR0_BSU_MASK 0x3
+/* Auxiliary Configuration register */
+#define ARM_SMMU_GR0_sACR 0x10
+
/* Identification registers */
#define ARM_SMMU_GR0_ID0 0x20
#define ARM_SMMU_GR0_ID1 0x24
@@ -235,6 +238,8 @@
#define ARM_MMU500_ACTLR_CPRE (1 << 1)
+#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
+
#define CB_PAR_F (1 << 0)
#define ATSR_ACTIVE (1 << 0)
@@ -1506,6 +1511,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
}
+ /*
+ * Before clearing ARM_MMU500_ACTLR_CPRE, need to
+ * clear CACHE_LOCK bit of ACR first.
+ */
+ if (smmu->model == ARM_MMU500) {
+ reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
+ reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
+ writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
+ }
+
/* Make sure all context banks are disabled and clear CB_FSR */
for (i = 0; i < smmu->num_context_banks; ++i) {
cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
--
2.6.2
^ permalink raw reply related [flat|nested] 9+ messages in thread[parent not found: <1462270527-17074-1-git-send-email-van.freenix-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH] iommu/arm-smmu: clear cache lock bit of ACR
2016-05-03 10:15 ` Peng Fan
(?)
@ 2016-05-03 11:15 ` Robin Murphy
-1 siblings, 0 replies; 9+ messages in thread
From: Robin Murphy @ 2016-05-03 11:15 UTC (permalink / raw)
To: Peng Fan, will.deacon-5wv7dgnIgG8
Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 03/05/16 11:15, Peng Fan wrote:
> According MMU-500 TRM, section 3.7.1 Auxiliary Control registers,
> You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
>
> So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
> need clear CACHE_LOCK bit of ACR register first.
Ah, good catch - I think I misread CACHE_LOCK as resetting to 0, and
proceeded to forget about it. However, it's only present in MMU-500r2
onwards, so we'd also want to check IDR7 before touching ACR.
Thanks,
Robin.
> Signed-off-by: Peng Fan <van.freenix-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
> Cc: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
> ---
>
> Hi Will,
>
> Patch based on iommu/devel branch.
>
>
> drivers/iommu/arm-smmu.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index acff332..d094a5a 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -98,6 +98,9 @@
> #define sCR0_BSU_SHIFT 14
> #define sCR0_BSU_MASK 0x3
>
> +/* Auxiliary Configuration register */
> +#define ARM_SMMU_GR0_sACR 0x10
> +
> /* Identification registers */
> #define ARM_SMMU_GR0_ID0 0x20
> #define ARM_SMMU_GR0_ID1 0x24
> @@ -235,6 +238,8 @@
>
> #define ARM_MMU500_ACTLR_CPRE (1 << 1)
>
> +#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
> +
> #define CB_PAR_F (1 << 0)
>
> #define ATSR_ACTIVE (1 << 0)
> @@ -1506,6 +1511,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
> writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
> }
>
> + /*
> + * Before clearing ARM_MMU500_ACTLR_CPRE, need to
> + * clear CACHE_LOCK bit of ACR first.
> + */
> + if (smmu->model == ARM_MMU500) {
> + reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
> + reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
> + writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
> + }
> +
> /* Make sure all context banks are disabled and clear CB_FSR */
> for (i = 0; i < smmu->num_context_banks; ++i) {
> cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] iommu/arm-smmu: clear cache lock bit of ACR
@ 2016-05-03 11:15 ` Robin Murphy
0 siblings, 0 replies; 9+ messages in thread
From: Robin Murphy @ 2016-05-03 11:15 UTC (permalink / raw)
To: Peng Fan, will.deacon; +Cc: joro, linux-arm-kernel, iommu, linux-kernel
On 03/05/16 11:15, Peng Fan wrote:
> According MMU-500 TRM, section 3.7.1 Auxiliary Control registers,
> You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
>
> So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
> need clear CACHE_LOCK bit of ACR register first.
Ah, good catch - I think I misread CACHE_LOCK as resetting to 0, and
proceeded to forget about it. However, it's only present in MMU-500r2
onwards, so we'd also want to check IDR7 before touching ACR.
Thanks,
Robin.
> Signed-off-by: Peng Fan <van.freenix@gmail.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Robin Murphy <robin.murphy@arm.com>
> ---
>
> Hi Will,
>
> Patch based on iommu/devel branch.
>
>
> drivers/iommu/arm-smmu.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index acff332..d094a5a 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -98,6 +98,9 @@
> #define sCR0_BSU_SHIFT 14
> #define sCR0_BSU_MASK 0x3
>
> +/* Auxiliary Configuration register */
> +#define ARM_SMMU_GR0_sACR 0x10
> +
> /* Identification registers */
> #define ARM_SMMU_GR0_ID0 0x20
> #define ARM_SMMU_GR0_ID1 0x24
> @@ -235,6 +238,8 @@
>
> #define ARM_MMU500_ACTLR_CPRE (1 << 1)
>
> +#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
> +
> #define CB_PAR_F (1 << 0)
>
> #define ATSR_ACTIVE (1 << 0)
> @@ -1506,6 +1511,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
> writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
> }
>
> + /*
> + * Before clearing ARM_MMU500_ACTLR_CPRE, need to
> + * clear CACHE_LOCK bit of ACR first.
> + */
> + if (smmu->model == ARM_MMU500) {
> + reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
> + reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
> + writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
> + }
> +
> /* Make sure all context banks are disabled and clear CB_FSR */
> for (i = 0; i < smmu->num_context_banks; ++i) {
> cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
>
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH] iommu/arm-smmu: clear cache lock bit of ACR
@ 2016-05-03 11:15 ` Robin Murphy
0 siblings, 0 replies; 9+ messages in thread
From: Robin Murphy @ 2016-05-03 11:15 UTC (permalink / raw)
To: linux-arm-kernel
On 03/05/16 11:15, Peng Fan wrote:
> According MMU-500 TRM, section 3.7.1 Auxiliary Control registers,
> You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
>
> So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
> need clear CACHE_LOCK bit of ACR register first.
Ah, good catch - I think I misread CACHE_LOCK as resetting to 0, and
proceeded to forget about it. However, it's only present in MMU-500r2
onwards, so we'd also want to check IDR7 before touching ACR.
Thanks,
Robin.
> Signed-off-by: Peng Fan <van.freenix@gmail.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Robin Murphy <robin.murphy@arm.com>
> ---
>
> Hi Will,
>
> Patch based on iommu/devel branch.
>
>
> drivers/iommu/arm-smmu.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index acff332..d094a5a 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -98,6 +98,9 @@
> #define sCR0_BSU_SHIFT 14
> #define sCR0_BSU_MASK 0x3
>
> +/* Auxiliary Configuration register */
> +#define ARM_SMMU_GR0_sACR 0x10
> +
> /* Identification registers */
> #define ARM_SMMU_GR0_ID0 0x20
> #define ARM_SMMU_GR0_ID1 0x24
> @@ -235,6 +238,8 @@
>
> #define ARM_MMU500_ACTLR_CPRE (1 << 1)
>
> +#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
> +
> #define CB_PAR_F (1 << 0)
>
> #define ATSR_ACTIVE (1 << 0)
> @@ -1506,6 +1511,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
> writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
> }
>
> + /*
> + * Before clearing ARM_MMU500_ACTLR_CPRE, need to
> + * clear CACHE_LOCK bit of ACR first.
> + */
> + if (smmu->model == ARM_MMU500) {
> + reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
> + reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
> + writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
> + }
> +
> /* Make sure all context banks are disabled and clear CB_FSR */
> for (i = 0; i < smmu->num_context_banks; ++i) {
> cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
>
^ permalink raw reply [flat|nested] 9+ messages in thread[parent not found: <57288868.9020908-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH] iommu/arm-smmu: clear cache lock bit of ACR
2016-05-03 11:15 ` Robin Murphy
(?)
@ 2016-05-03 12:50 ` Peng Fan
-1 siblings, 0 replies; 9+ messages in thread
From: Peng Fan @ 2016-05-03 12:50 UTC (permalink / raw)
To: Robin Murphy
Cc: will.deacon-5wv7dgnIgG8,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Hi Robin,
On Tue, May 03, 2016 at 12:15:52PM +0100, Robin Murphy wrote:
>On 03/05/16 11:15, Peng Fan wrote:
>>According MMU-500 TRM, section 3.7.1 Auxiliary Control registers,
>>You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
>>
>>So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
>>need clear CACHE_LOCK bit of ACR register first.
>
>Ah, good catch - I think I misread CACHE_LOCK as resetting to 0, and
>proceeded to forget about it. However, it's only present in MMU-500r2
>onwards, so we'd also want to check IDR7 before touching ACR.
Thanks for comments. I'll add code to check IDR7 and send out V2.
Thanks,
Peng.
>
>Thanks,
>Robin.
>
>>Signed-off-by: Peng Fan <van.freenix-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
>>Cc: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
>>---
>>
>>Hi Will,
>>
>> Patch based on iommu/devel branch.
>>
>>
>> drivers/iommu/arm-smmu.c | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>>diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>>index acff332..d094a5a 100644
>>--- a/drivers/iommu/arm-smmu.c
>>+++ b/drivers/iommu/arm-smmu.c
>>@@ -98,6 +98,9 @@
>> #define sCR0_BSU_SHIFT 14
>> #define sCR0_BSU_MASK 0x3
>>
>>+/* Auxiliary Configuration register */
>>+#define ARM_SMMU_GR0_sACR 0x10
>>+
>> /* Identification registers */
>> #define ARM_SMMU_GR0_ID0 0x20
>> #define ARM_SMMU_GR0_ID1 0x24
>>@@ -235,6 +238,8 @@
>>
>> #define ARM_MMU500_ACTLR_CPRE (1 << 1)
>>
>>+#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
>>+
>> #define CB_PAR_F (1 << 0)
>>
>> #define ATSR_ACTIVE (1 << 0)
>>@@ -1506,6 +1511,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
>> writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
>> }
>>
>>+ /*
>>+ * Before clearing ARM_MMU500_ACTLR_CPRE, need to
>>+ * clear CACHE_LOCK bit of ACR first.
>>+ */
>>+ if (smmu->model == ARM_MMU500) {
>>+ reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
>>+ reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
>>+ writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
>>+ }
>>+
>> /* Make sure all context banks are disabled and clear CB_FSR */
>> for (i = 0; i < smmu->num_context_banks; ++i) {
>> cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
>>
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] iommu/arm-smmu: clear cache lock bit of ACR
@ 2016-05-03 12:50 ` Peng Fan
0 siblings, 0 replies; 9+ messages in thread
From: Peng Fan @ 2016-05-03 12:50 UTC (permalink / raw)
To: Robin Murphy; +Cc: will.deacon, joro, linux-arm-kernel, iommu, linux-kernel
Hi Robin,
On Tue, May 03, 2016 at 12:15:52PM +0100, Robin Murphy wrote:
>On 03/05/16 11:15, Peng Fan wrote:
>>According MMU-500 TRM, section 3.7.1 Auxiliary Control registers,
>>You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
>>
>>So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
>>need clear CACHE_LOCK bit of ACR register first.
>
>Ah, good catch - I think I misread CACHE_LOCK as resetting to 0, and
>proceeded to forget about it. However, it's only present in MMU-500r2
>onwards, so we'd also want to check IDR7 before touching ACR.
Thanks for comments. I'll add code to check IDR7 and send out V2.
Thanks,
Peng.
>
>Thanks,
>Robin.
>
>>Signed-off-by: Peng Fan <van.freenix@gmail.com>
>>Cc: Will Deacon <will.deacon@arm.com>
>>Cc: Robin Murphy <robin.murphy@arm.com>
>>---
>>
>>Hi Will,
>>
>> Patch based on iommu/devel branch.
>>
>>
>> drivers/iommu/arm-smmu.c | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>>diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>>index acff332..d094a5a 100644
>>--- a/drivers/iommu/arm-smmu.c
>>+++ b/drivers/iommu/arm-smmu.c
>>@@ -98,6 +98,9 @@
>> #define sCR0_BSU_SHIFT 14
>> #define sCR0_BSU_MASK 0x3
>>
>>+/* Auxiliary Configuration register */
>>+#define ARM_SMMU_GR0_sACR 0x10
>>+
>> /* Identification registers */
>> #define ARM_SMMU_GR0_ID0 0x20
>> #define ARM_SMMU_GR0_ID1 0x24
>>@@ -235,6 +238,8 @@
>>
>> #define ARM_MMU500_ACTLR_CPRE (1 << 1)
>>
>>+#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
>>+
>> #define CB_PAR_F (1 << 0)
>>
>> #define ATSR_ACTIVE (1 << 0)
>>@@ -1506,6 +1511,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
>> writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
>> }
>>
>>+ /*
>>+ * Before clearing ARM_MMU500_ACTLR_CPRE, need to
>>+ * clear CACHE_LOCK bit of ACR first.
>>+ */
>>+ if (smmu->model == ARM_MMU500) {
>>+ reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
>>+ reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
>>+ writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
>>+ }
>>+
>> /* Make sure all context banks are disabled and clear CB_FSR */
>> for (i = 0; i < smmu->num_context_banks; ++i) {
>> cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
>>
>
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH] iommu/arm-smmu: clear cache lock bit of ACR
@ 2016-05-03 12:50 ` Peng Fan
0 siblings, 0 replies; 9+ messages in thread
From: Peng Fan @ 2016-05-03 12:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi Robin,
On Tue, May 03, 2016 at 12:15:52PM +0100, Robin Murphy wrote:
>On 03/05/16 11:15, Peng Fan wrote:
>>According MMU-500 TRM, section 3.7.1 Auxiliary Control registers,
>>You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
>>
>>So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
>>need clear CACHE_LOCK bit of ACR register first.
>
>Ah, good catch - I think I misread CACHE_LOCK as resetting to 0, and
>proceeded to forget about it. However, it's only present in MMU-500r2
>onwards, so we'd also want to check IDR7 before touching ACR.
Thanks for comments. I'll add code to check IDR7 and send out V2.
Thanks,
Peng.
>
>Thanks,
>Robin.
>
>>Signed-off-by: Peng Fan <van.freenix@gmail.com>
>>Cc: Will Deacon <will.deacon@arm.com>
>>Cc: Robin Murphy <robin.murphy@arm.com>
>>---
>>
>>Hi Will,
>>
>> Patch based on iommu/devel branch.
>>
>>
>> drivers/iommu/arm-smmu.c | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>>diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>>index acff332..d094a5a 100644
>>--- a/drivers/iommu/arm-smmu.c
>>+++ b/drivers/iommu/arm-smmu.c
>>@@ -98,6 +98,9 @@
>> #define sCR0_BSU_SHIFT 14
>> #define sCR0_BSU_MASK 0x3
>>
>>+/* Auxiliary Configuration register */
>>+#define ARM_SMMU_GR0_sACR 0x10
>>+
>> /* Identification registers */
>> #define ARM_SMMU_GR0_ID0 0x20
>> #define ARM_SMMU_GR0_ID1 0x24
>>@@ -235,6 +238,8 @@
>>
>> #define ARM_MMU500_ACTLR_CPRE (1 << 1)
>>
>>+#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
>>+
>> #define CB_PAR_F (1 << 0)
>>
>> #define ATSR_ACTIVE (1 << 0)
>>@@ -1506,6 +1511,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
>> writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
>> }
>>
>>+ /*
>>+ * Before clearing ARM_MMU500_ACTLR_CPRE, need to
>>+ * clear CACHE_LOCK bit of ACR first.
>>+ */
>>+ if (smmu->model == ARM_MMU500) {
>>+ reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
>>+ reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
>>+ writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
>>+ }
>>+
>> /* Make sure all context banks are disabled and clear CB_FSR */
>> for (i = 0; i < smmu->num_context_banks; ++i) {
>> cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
>>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-05-03 12:50 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-05-03 10:15 [PATCH] iommu/arm-smmu: clear cache lock bit of ACR Peng Fan
2016-05-03 10:15 ` Peng Fan
2016-05-03 10:15 ` Peng Fan
[not found] ` <1462270527-17074-1-git-send-email-van.freenix-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-05-03 11:15 ` Robin Murphy
2016-05-03 11:15 ` Robin Murphy
2016-05-03 11:15 ` Robin Murphy
[not found] ` <57288868.9020908-5wv7dgnIgG8@public.gmane.org>
2016-05-03 12:50 ` Peng Fan
2016-05-03 12:50 ` Peng Fan
2016-05-03 12:50 ` Peng Fan
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