Re: [PATCH 1/1] ARM: dts: sunxi: Add a olinuxino-lime2-emmc

[Olliver Schinagl <oliver-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org>]

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Hey Christo,

On 04-05-16 21:40, Christo Radev wrote:
> Hi Oliver,
>
> I start performance tests for eMMC, SD/MMC, USB, SATA SSD devices and 
> will post the result when ready.
>
> As a beginning I can say that eMMC is accessed via 4-bit bus without 
> matter of the patch used.
> There you are the content of /sys/kernel/debug/mmcX/ios (where X is 
> number of eMMC or SD/MMC device).
> |
> BootedfromSD card with8-bit patched kernel
> root@egpr:~# dmesg | grep mmc
> [3.599625]sunxi-mmc 1c0f000.mmc:GotCD GPIO
> [3.631883]sunxi-mmc 1c0f000.mmc:base:0xf08da000irq:26
> [3.669058]mmc0:host does notsupport reading read-only switch,assuming 
> write-enable
> [3.671674]sunxi-mmc 1c11000.mmc:base:0xf08de000irq:27
> [3.672064]mmc0:newhigh speed SDHC card at address 0007
> [3.673068]mmcblk0:mmc0:0007SD04G 3.71GiB
> [3.674785] mmcblk0:p1
> [3.682261]sunxi-mmc 1c11000.mmc:smc 1err,cmd 8,RTO !!
> [3.689280]sunxi-mmc 1c11000.mmc:smc 1err,cmd 55,RTO !!
> [3.690146]sunxi-mmc 1c11000.mmc:smc 1err,cmd 55,RTO !!
> [3.690977]sunxi-mmc 1c11000.mmc:smc 1err,cmd 55,RTO !!
> [3.691808]sunxi-mmc 1c11000.mmc:smc 1err,cmd 55,RTO !!
> [3.745505]mmc1:MAN_BKOPS_EN bit isnotset
> [3.749187]sunxi-mmc 1c11000.mmc:smc 1err,cmd 8,RD EBE !!
> [3.749229]sunxi-mmc 1c11000.mmc:data error,sending stop command
> [3.749247]sunxi-mmc 1c11000.mmc:send stop command failed
> [3.749268]mmc1:switchto bus width 2failed
> [3.753586]mmc1:newhigh speed MMC card at address 0001
> [3.754479]mmcblk1:mmc1:0001P1XXXX 3.60GiB
> [3.754961]mmcblk1boot0:mmc1:0001P1XXXX partition 116.0MiB
> [3.755604]mmcblk1boot1:mmc1:0001P1XXXX partition 216.0MiB
> [3.757045] mmcblk1:p1
> [4.216879]EXT4-fs (mmcblk0p1):mounted filesystem withwriteback data 
> mode.Opts:(null)
> [7.907002]EXT4-fs (mmcblk0p1):re-mounted.Opts:commit=600,errors=remount-ro
>
> root@egpr:~# cat /sys/kernel/debug/mmc0/ios
> clock:50000000Hz
> vdd:21(3.3~3.4V)
> bus mode:2(push-pull)
> chip select:0(don't care)
> power mode:     2 (on)
> bus width:      2 (4 bits)
> timing spec:    2 (sd high-speed)
> signal voltage: 0 (3.30 V)
> driver type:    0 (driver type B)
> root@egpr:~# cat /sys/kernel/debug/mmc1/ios
> clock:          50000000 Hz
> vdd:            21 (3.3 ~ 3.4 V)
> bus mode:       2 (push-pull)
> chip select:    0 (don't care)
> power mode:2(on)
> bus width:2(4bits)
> timing spec:1(mmc high-speed)
> signal voltage:0(3.30V)
> driver type:0(driver type B)
>
> BootedfromSATA SSD with4-bit patched kernel
> [3.598868]sunxi-mmc 1c0f000.mmc:GotCD GPIO
> [3.631154]sunxi-mmc 1c0f000.mmc:base:0xf08da000irq:26
> [3.668313]mmc0:host does notsupport reading read-only switch,assuming 
> write-enable
> [3.670908]sunxi-mmc 1c11000.mmc:base:0xf08de000irq:27
> [3.671324]mmc0:newhigh speed SDHC card at address 0007
> [3.672302]mmcblk0:mmc0:0007SD04G 3.71GiB
> [3.674067] mmcblk0:p1
> [3.681882]sunxi-mmc 1c11000.mmc:smc 1err,cmd 8,RTO !!
> [3.686129]sunxi-mmc 1c11000.mmc:smc 1err,cmd 55,RTO !!
> [3.686996]sunxi-mmc 1c11000.mmc:smc 1err,cmd 55,RTO !!
> [3.687843]sunxi-mmc 1c11000.mmc:smc 1err,cmd 55,RTO !!
> [3.688672]sunxi-mmc 1c11000.mmc:smc 1err,cmd 55,RTO !!
> [3.724762]mmc1:MAN_BKOPS_EN bit isnotset
> [3.731196]mmc1:newhigh speed MMC card at address 0001
> [3.732141]mmcblk1:mmc1:0001P1XXXX 3.60GiB
> [3.732553]mmcblk1boot0:mmc1:0001P1XXXX partition 116.0MiB
> [3.732960]mmcblk1boot1:mmc1:0001P1XXXX partition 216.0MiB
> [3.734186] mmcblk1:p1
>
> root@egpr:~# cat /sys/kernel/debug/mmc0/ios
> clock:50000000Hz
> vdd:21(3.3~3.4V)
> bus mode:2(push-pull)
> chip select:0(don't care)
> power mode:     2 (on)
> bus width:      2 (4 bits)
> timing spec:    2 (sd high-speed)
> signal voltage: 0 (3.30 V)
> driver type:    0 (driver type B)
> root@egpr:~# cat /sys/kernel/debug/mmc1/ios
> clock:          50000000 Hz
> vdd:            21 (3.3 ~ 3.4 V)
> bus mode:       2 (push-pull)
> chip select:    0 (don't care)
> power mode:2(on)
> bus width:2(4bits)
> timing spec:1(mmc high-speed)
> signal voltage:0(3.30V)
> driver type:0(driver type B)
> |
>
> The brief performance test using dd shows the similar results to both 
> 4- and 8-bit patches
> |
> eMMC 8-bit patch R/W test withdd
> root@egpr:/mnt# dd if=/dev/zero of=1GBfilebs=1Mcount=1K
> 1024+0records in
> 1024+0records out
> 1073741824bytes (1.1GB)copied,79.9305s,13.4MB/s
> root@egpr:/mnt# dd of=/dev/nullif=1GBfile
> 2097152+0records in
> 2097152+0records out
> 1073741824bytes (1.1GB)copied,49.5899s,21.7MB/s
>
> eMMC 4-bit patch R/W test withdd
> root@egpr:/mnt# dd if=/dev/zero of=1GBfilebs=1Mcount=1K
> 1024+0records in
> 1024+0records out
> 1073741824bytes (1.1GB)copied,78.7925s,13.6MB/s
> root@egpr:/mnt# dd of=/dev/nullif=1GBfile
> 2097152+0records in
> 2097152+0records out
> 1073741824bytes (1.1GB)copied,53.8002s,20.0MB/s
> |
>
> In my opinion 8-bit access to eMMC is broken in Allwinned A20 or in 
> the mmc driver.
Nah, it's not broken. But Allwinner 'forgot' to map the mmc controller 
pins to the mux and thus the additional 4 bits are not on the actual 
pins. It is sad and wasn't necessary, I'm sure it's just a small over 
sight, which is costing us performance now. But we get a big improvement 
by using the latest 4.6-rc1+ kernel by using HS-DDR mode. In my early 
tests I saw 40 MB/s read and 17 MB/s write speeds. It would be nice to 
imagine what the additional 8 bits would have brought us, but alas.

As I said however, the Lime2 PCB brings out all 8 bits and if we ever 
get a pin-compatible A40, there is a chance it will have 8 bit emmc. The 
Lime2 does not have 1.8 3.3 switcher on the vqmmc lines however, but I 
am not sure if we need this at all for higher speeds.

If 8 bit would give us double the bandwith, it could be we'd get 80 
MB/s/40 MB/s in theory, but I think that's already beyond the current 
chip anyway.

Comparing it to the current NAND chips, which top ou at 4MB/s read if 
memory serves me, eMMC makes the boards quite capable :)

olliver
>
> Best regards
> Chris
>

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