* [PATCH 01/19] drm: Restore double clflush on the last partial cacheline
@ 2016-05-05 9:15 Chris Wilson
2016-05-05 9:15 ` [PATCH 02/19] drm/i915/execlists: Refactor common engine setup Chris Wilson
` (17 more replies)
0 siblings, 18 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx
Cc: Chris Wilson, dri-devel, Akash Goel, Imre Deak, Daniel Vetter,
Jason Ekstrand, stable
This effectively reverts
commit afcd950cafea6e27b739fe7772cbbeed37d05b8b
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Jun 10 15:58:01 2015 +0100
drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()
as we have observed issues with serialisation of the clflush operations
on Baytrail+ Atoms with partial updates. Applying the double flush on the
last cacheline forces that clflush to be ordered with respect to the
previous clflush, and the mfence then protects against prefetches crossing
the clflush boundary.
The same issue can be demonstrated in userspace with igt/gem_exec_flush.
Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...)
Testcase: igt/gem_concurrent_blit
Testcase: igt/gem_partial_pread_pwrite
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: dri-devel@lists.freedesktop.org
Cc: Akash Goel <akash.goel@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/drm_cache.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 6743ff7dccfa..7f4a6c550319 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsigned long length)
mb();
for (; addr < end; addr += size)
clflushopt(addr);
+ clflushopt(end - 1); /* force serialisation */
mb();
return;
}
--
2.8.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 02/19] drm/i915/execlists: Refactor common engine setup
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
@ 2016-05-05 9:15 ` Chris Wilson
2016-05-05 10:18 ` Tvrtko Ursulin
2016-05-05 9:15 ` [PATCH 03/19] drm/i915: Store a i915 backpointer from engine, and use it Chris Wilson
` (16 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx
Move all of the constant assignments up front and into a common
function. This is primarily to ensure the backpointers are set as early
as possible for later use during initialisation.
v2: Use a constant struct so that all the similar values are set
together.
v3: Sanitize the engine's IMR to disable any potential interrupt before
we are ready (enabled in init_hw).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 180 +++++++++++++++++++++------------------
1 file changed, 97 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d8763524319d..8106316ce56f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1918,8 +1918,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
}
static void
-logical_ring_default_vfuncs(struct drm_device *dev,
- struct intel_engine_cs *engine)
+logical_ring_default_vfuncs(struct intel_engine_cs *engine)
{
/* Default vfuncs which can be overriden by each engine. */
engine->init_hw = gen8_init_common_ring;
@@ -1930,7 +1929,7 @@ logical_ring_default_vfuncs(struct drm_device *dev,
engine->emit_bb_start = gen8_emit_bb_start;
engine->get_seqno = gen8_get_seqno;
engine->set_seqno = gen8_set_seqno;
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(engine->dev, 0, BXT_REVID_A1)) {
engine->irq_seqno_barrier = bxt_a_seqno_barrier;
engine->set_seqno = bxt_a_set_seqno;
}
@@ -1941,6 +1940,7 @@ logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
{
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
+ init_waitqueue_head(&engine->irq_queue);
}
static int
@@ -1961,31 +1961,72 @@ lrc_setup_hws(struct intel_engine_cs *engine,
return 0;
}
-static int
-logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
+static const struct logical_ring_info {
+ const char *name;
+ unsigned exec_id;
+ unsigned guc_id;
+ u32 mmio_base;
+ unsigned irq_shift;
+} logical_rings[] = {
+ [RCS] = {
+ .name = "render ring",
+ .exec_id = I915_EXEC_RENDER,
+ .guc_id = GUC_RENDER_ENGINE,
+ .mmio_base = RENDER_RING_BASE,
+ .irq_shift = GEN8_RCS_IRQ_SHIFT,
+ },
+ [BCS] = {
+ .name = "blitter ring",
+ .exec_id = I915_EXEC_BLT,
+ .guc_id = GUC_BLITTER_ENGINE,
+ .mmio_base = BLT_RING_BASE,
+ .irq_shift = GEN8_BCS_IRQ_SHIFT,
+ },
+ [VCS] = {
+ .name = "bsd ring",
+ .exec_id = I915_EXEC_BSD,
+ .guc_id = GUC_VIDEO_ENGINE,
+ .mmio_base = GEN6_BSD_RING_BASE,
+ .irq_shift = GEN8_VCS1_IRQ_SHIFT,
+ },
+ [VCS2] = {
+ .name = "bsd2 ring",
+ .exec_id = I915_EXEC_BSD,
+ .guc_id = GUC_VIDEO_ENGINE2,
+ .mmio_base = GEN8_BSD2_RING_BASE,
+ .irq_shift = GEN8_VCS2_IRQ_SHIFT,
+ },
+ [VECS] = {
+ .name = "video enhancement ring",
+ .exec_id = I915_EXEC_VEBOX,
+ .guc_id = GUC_VIDEOENHANCE_ENGINE,
+ .mmio_base = VEBOX_RING_BASE,
+ .irq_shift = GEN8_VECS_IRQ_SHIFT,
+ },
+};
+
+static struct intel_engine_cs *
+logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
{
+ const struct logical_ring_info *info = &logical_rings[id];
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_context *dctx = dev_priv->kernel_context;
+ struct intel_engine_cs *engine = &dev_priv->engine[id];
enum forcewake_domains fw_domains;
- int ret;
- /* Intentionally left blank. */
- engine->buffer = NULL;
+ engine->id = id;
+ engine->name = info->name;
+ engine->exec_id = info->exec_id;
+ engine->guc_id = info->guc_id;
+ engine->mmio_base = info->mmio_base;
- engine->dev = dev;
- INIT_LIST_HEAD(&engine->active_list);
- INIT_LIST_HEAD(&engine->request_list);
- i915_gem_batch_pool_init(dev, &engine->batch_pool);
- init_waitqueue_head(&engine->irq_queue);
+ /* disable interrupts to this engine before we install ourselves */
+ I915_WRITE_IMR(engine, ~0);
+ POSTING_READ(RING_IMR(engine->mmio_base));
- INIT_LIST_HEAD(&engine->buffers);
- INIT_LIST_HEAD(&engine->execlist_queue);
- spin_lock_init(&engine->execlist_lock);
-
- tasklet_init(&engine->irq_tasklet,
- intel_lrc_irq_handler, (unsigned long)engine);
+ engine->dev = dev;
- logical_ring_init_platform_invariants(engine);
+ /* Intentionally left blank. */
+ engine->buffer = NULL;
fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
RING_ELSP(engine),
@@ -2001,6 +2042,31 @@ logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
engine->fw_domains = fw_domains;
+ INIT_LIST_HEAD(&engine->active_list);
+ INIT_LIST_HEAD(&engine->request_list);
+ INIT_LIST_HEAD(&engine->buffers);
+ INIT_LIST_HEAD(&engine->execlist_queue);
+ spin_lock_init(&engine->execlist_lock);
+
+ tasklet_init(&engine->irq_tasklet,
+ intel_lrc_irq_handler, (unsigned long)engine);
+
+ logical_ring_init_platform_invariants(engine);
+ logical_ring_default_vfuncs(engine);
+ logical_ring_default_irqs(engine, info->irq_shift);
+
+ intel_engine_init_hangcheck(engine);
+ i915_gem_batch_pool_init(engine->dev, &engine->batch_pool);
+
+ return engine;
+}
+
+static int
+logical_ring_init(struct intel_engine_cs *engine)
+{
+ struct intel_context *dctx = to_i915(engine->dev)->kernel_context;
+ int ret;
+
ret = i915_cmd_parser_init_ring(engine);
if (ret)
goto error;
@@ -2033,22 +2099,12 @@ error:
static int logical_render_ring_init(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_engine_cs *engine = &dev_priv->engine[RCS];
+ struct intel_engine_cs *engine = logical_ring_setup(dev, RCS);
int ret;
- engine->name = "render ring";
- engine->id = RCS;
- engine->exec_id = I915_EXEC_RENDER;
- engine->guc_id = GUC_RENDER_ENGINE;
- engine->mmio_base = RENDER_RING_BASE;
-
- logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT);
if (HAS_L3_DPF(dev))
engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
- logical_ring_default_vfuncs(dev, engine);
-
/* Override some for render ring. */
if (INTEL_INFO(dev)->gen >= 9)
engine->init_hw = gen9_init_render_ring;
@@ -2059,8 +2115,6 @@ static int logical_render_ring_init(struct drm_device *dev)
engine->emit_flush = gen8_emit_flush_render;
engine->emit_request = gen8_emit_request_render;
- engine->dev = dev;
-
ret = intel_init_pipe_control(engine);
if (ret)
return ret;
@@ -2076,7 +2130,7 @@ static int logical_render_ring_init(struct drm_device *dev)
ret);
}
- ret = logical_ring_init(dev, engine);
+ ret = logical_ring_init(engine);
if (ret) {
lrc_destroy_wa_ctx_obj(engine);
}
@@ -2086,70 +2140,30 @@ static int logical_render_ring_init(struct drm_device *dev)
static int logical_bsd_ring_init(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_engine_cs *engine = &dev_priv->engine[VCS];
-
- engine->name = "bsd ring";
- engine->id = VCS;
- engine->exec_id = I915_EXEC_BSD;
- engine->guc_id = GUC_VIDEO_ENGINE;
- engine->mmio_base = GEN6_BSD_RING_BASE;
+ struct intel_engine_cs *engine = logical_ring_setup(dev, VCS);
- logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT);
- logical_ring_default_vfuncs(dev, engine);
-
- return logical_ring_init(dev, engine);
+ return logical_ring_init(engine);
}
static int logical_bsd2_ring_init(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
-
- engine->name = "bsd2 ring";
- engine->id = VCS2;
- engine->exec_id = I915_EXEC_BSD;
- engine->guc_id = GUC_VIDEO_ENGINE2;
- engine->mmio_base = GEN8_BSD2_RING_BASE;
+ struct intel_engine_cs *engine = logical_ring_setup(dev, VCS2);
- logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT);
- logical_ring_default_vfuncs(dev, engine);
-
- return logical_ring_init(dev, engine);
+ return logical_ring_init(engine);
}
static int logical_blt_ring_init(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_engine_cs *engine = &dev_priv->engine[BCS];
-
- engine->name = "blitter ring";
- engine->id = BCS;
- engine->exec_id = I915_EXEC_BLT;
- engine->guc_id = GUC_BLITTER_ENGINE;
- engine->mmio_base = BLT_RING_BASE;
-
- logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT);
- logical_ring_default_vfuncs(dev, engine);
+ struct intel_engine_cs *engine = logical_ring_setup(dev, BCS);
- return logical_ring_init(dev, engine);
+ return logical_ring_init(engine);
}
static int logical_vebox_ring_init(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_engine_cs *engine = &dev_priv->engine[VECS];
-
- engine->name = "video enhancement ring";
- engine->id = VECS;
- engine->exec_id = I915_EXEC_VEBOX;
- engine->guc_id = GUC_VIDEOENHANCE_ENGINE;
- engine->mmio_base = VEBOX_RING_BASE;
-
- logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT);
- logical_ring_default_vfuncs(dev, engine);
+ struct intel_engine_cs *engine = logical_ring_setup(dev, VECS);
- return logical_ring_init(dev, engine);
+ return logical_ring_init(engine);
}
/**
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 03/19] drm/i915: Store a i915 backpointer from engine, and use it
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
2016-05-05 9:15 ` [PATCH 02/19] drm/i915/execlists: Refactor common engine setup Chris Wilson
@ 2016-05-05 9:15 ` Chris Wilson
2016-05-05 11:15 ` Tvrtko Ursulin
2016-05-05 9:15 ` [PATCH 04/19] drm/i915/shrinker: Flush active on objects before counting Chris Wilson
` (15 subsequent siblings)
17 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx
text data bss dec hex filename
6309351 3578714 696320 10584385 a18141 vmlinux
6308391 3578714 696320 10583425 a17d81 vmlinux
Almost 1KiB of code reduction.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 12 +-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/i915_dma.c | 9 +-
drivers/gpu/drm/i915/i915_drv.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 35 ++--
drivers/gpu/drm/i915/i915_gem.c | 47 ++---
drivers/gpu/drm/i915/i915_gem_context.c | 48 ++---
drivers/gpu/drm/i915/i915_gem_evict.c | 4 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +--
drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +-
drivers/gpu/drm/i915/i915_gem_shrinker.c | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 79 ++++----
drivers/gpu/drm/i915/i915_irq.c | 80 ++++----
drivers/gpu/drm/i915/i915_trace.h | 36 ++--
drivers/gpu/drm/i915/intel_display.c | 49 +++--
drivers/gpu/drm/i915/intel_drv.h | 4 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 138 ++++++-------
drivers/gpu/drm/i915/intel_lrc.h | 3 +-
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_overlay.c | 3 +-
drivers/gpu/drm/i915/intel_pm.c | 5 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 290 ++++++++++++---------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 8 +-
drivers/gpu/drm/i915/intel_uncore.c | 14 +-
26 files changed, 442 insertions(+), 499 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 69a1ba8ebdfb..35224ea30201 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -750,12 +750,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
int cmd_table_count;
int ret;
- if (!IS_GEN7(engine->dev))
+ if (!IS_GEN7(engine->i915))
return 0;
switch (engine->id) {
case RCS:
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine->i915)) {
cmd_tables = hsw_render_ring_cmds;
cmd_table_count =
ARRAY_SIZE(hsw_render_ring_cmds);
@@ -764,7 +764,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
}
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine->i915)) {
engine->reg_tables = hsw_render_reg_tables;
engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
} else {
@@ -780,7 +780,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
break;
case BCS:
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine->i915)) {
cmd_tables = hsw_blt_ring_cmds;
cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
} else {
@@ -788,7 +788,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
}
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine->i915)) {
engine->reg_tables = hsw_blt_reg_tables;
engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
} else {
@@ -1035,7 +1035,7 @@ bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
if (!engine->needs_cmd_parser)
return false;
- if (!USES_PPGTT(engine->dev))
+ if (!USES_PPGTT(engine->i915))
return false;
return (i915.enable_cmd_parser == 1);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6ad008c196b5..6698957ede3f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1383,7 +1383,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
seqno[id] = engine->get_seqno(engine);
}
- i915_get_extra_instdone(dev, instdone);
+ i915_get_extra_instdone(dev_priv, instdone);
intel_runtime_pm_put(dev_priv);
@@ -3165,7 +3165,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused)
enum intel_engine_id id;
int j, ret;
- if (!i915_semaphore_is_enabled(dev)) {
+ if (!i915_semaphore_is_enabled(dev_priv)) {
seq_puts(m, "Semaphores are disabled\n");
return 0;
}
@@ -4766,7 +4766,7 @@ i915_wedged_set(void *data, u64 val)
intel_runtime_pm_get(dev_priv);
- i915_handle_error(dev, val,
+ i915_handle_error(dev_priv, val,
"Manually setting wedged to %llu", val);
intel_runtime_pm_put(dev_priv);
@@ -4916,7 +4916,7 @@ i915_drop_caches_set(void *data, u64 val)
}
if (val & (DROP_RETIRE | DROP_ACTIVE))
- i915_gem_retire_requests(dev);
+ i915_gem_retire_requests(dev_priv);
if (val & DROP_BOUND)
i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ad7abe517700..46ac1da64a09 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -186,7 +186,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = 1;
break;
case I915_PARAM_HAS_SEMAPHORES:
- value = i915_semaphore_is_enabled(dev);
+ value = i915_semaphore_is_enabled(dev_priv);
break;
case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
value = 1;
@@ -970,7 +970,8 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
info->has_eu_pg ? "y" : "n");
i915.enable_execlists =
- intel_sanitize_enable_execlists(dev, i915.enable_execlists);
+ intel_sanitize_enable_execlists(dev_priv,
+ i915.enable_execlists);
/*
* i915.enable_ppgtt is read-only, so do an early pass to validate the
@@ -979,7 +980,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
* than every time we check intel_enable_ppgtt().
*/
i915.enable_ppgtt =
- intel_sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
+ intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
}
@@ -1345,7 +1346,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
* Notify a valid surface after modesetting,
* when running inside a VM.
*/
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
i915_setup_sysfs(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9fd221c97275..17aef1e92770 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -530,9 +530,9 @@ void intel_detect_pch(struct drm_device *dev)
pci_dev_put(pch);
}
-bool i915_semaphore_is_enabled(struct drm_device *dev)
+bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
{
- if (INTEL_INFO(dev)->gen < 6)
+ if (INTEL_GEN(dev_priv) < 6)
return false;
if (i915.semaphores >= 0)
@@ -544,7 +544,7 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
#ifdef CONFIG_INTEL_IOMMU
/* Enable semaphores on SNB when IO remapping is off */
- if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
+ if (INTEL_GEN(dev_priv) == 6 && intel_iommu_gfx_mapped)
return false;
#endif
@@ -914,9 +914,9 @@ int i915_resume_switcheroo(struct drm_device *dev)
* - re-init interrupt state
* - re-init display
*/
-int i915_reset(struct drm_device *dev)
+int i915_reset(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_device *dev = dev_priv->dev;
struct i915_gpu_error *error = &dev_priv->gpu_error;
unsigned reset_counter;
int ret;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5496aba1cd5..c162b825273f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2754,7 +2754,8 @@ extern int i915_max_ioctl;
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
-int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt);
+int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
+ int enable_ppgtt);
/* i915_dma.c */
void __printf(3, 4)
@@ -2778,7 +2779,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
#endif
extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_device *dev);
-extern int i915_reset(struct drm_device *dev);
+extern int i915_reset(struct drm_i915_private *dev_priv);
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
@@ -2795,9 +2796,10 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
/* i915_irq.c */
-void i915_queue_hangcheck(struct drm_device *dev);
+void i915_queue_hangcheck(struct drm_i915_private *dev_priv);
__printf(3, 4)
-void i915_handle_error(struct drm_device *dev, u32 engine_mask,
+void i915_handle_error(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
const char *fmt, ...);
extern void intel_irq_init(struct drm_i915_private *dev_priv);
@@ -2827,9 +2829,9 @@ void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
-static inline bool intel_vgpu_active(struct drm_device *dev)
+static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
{
- return to_i915(dev)->vgpu.active;
+ return dev_priv->vgpu.active;
}
void
@@ -3097,13 +3099,13 @@ static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
req->seqno);
}
-int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
+int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno);
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
struct drm_i915_gem_request *
i915_gem_find_active_request(struct intel_engine_cs *engine);
-bool i915_gem_retire_requests(struct drm_device *dev);
+bool i915_gem_retire_requests(struct drm_i915_private *dev_priv);
void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
static inline u32 i915_reset_counter(struct i915_gpu_error *error)
@@ -3350,9 +3352,9 @@ int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
/* belongs in i915_gem_gtt.h */
-static inline void i915_gem_chipset_flush(struct drm_device *dev)
+static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
{
- if (INTEL_INFO(dev)->gen < 6)
+ if (INTEL_INFO(dev_priv)->gen < 6)
intel_gtt_chipset_flush();
}
@@ -3431,14 +3433,15 @@ static inline void i915_error_state_buf_release(
{
kfree(eb->buf);
}
-void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
+void i915_capture_error_state(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
const char *error_msg);
void i915_error_state_get(struct drm_device *dev,
struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);
-void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
+void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
/* i915_cmd_parser.c */
@@ -3546,18 +3549,20 @@ extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_enable_rc6(const struct drm_device *dev);
-extern bool i915_semaphore_is_enabled(struct drm_device *dev);
+extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
/* overlay */
-extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
+extern struct intel_overlay_error_state *
+intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
struct intel_overlay_error_state *error);
-extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
+extern struct intel_display_error_state *
+intel_display_capture_error_state(struct drm_i915_private *dev_priv);
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
struct drm_device *dev,
struct intel_display_error_state *error);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a88e6c9e9516..c99d1b2c65d4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -177,7 +177,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
vaddr += PAGE_SIZE;
}
- i915_gem_chipset_flush(obj->base.dev);
+ i915_gem_chipset_flush(to_i915(obj->base.dev));
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (st == NULL)
@@ -347,7 +347,7 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
}
drm_clflush_virt_range(vaddr, args->size);
- i915_gem_chipset_flush(dev);
+ i915_gem_chipset_flush(to_i915(dev));
out:
intel_fb_obj_flush(obj, false, ORIGIN_CPU);
@@ -1006,7 +1006,7 @@ out:
}
if (needs_clflush_after)
- i915_gem_chipset_flush(dev);
+ i915_gem_chipset_flush(to_i915(dev));
else
obj->cache_dirty = true;
@@ -1230,8 +1230,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
struct intel_rps_client *rps)
{
struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = req->i915;
const bool irq_test_in_progress =
ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
@@ -1429,7 +1428,7 @@ __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
struct drm_i915_gem_request *tmp;
- lockdep_assert_held(&engine->dev->struct_mutex);
+ lockdep_assert_held(&engine->i915->dev->struct_mutex);
if (list_empty(&req->list))
return;
@@ -2502,9 +2501,8 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
}
static int
-i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
+i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *engine;
int ret;
@@ -2514,7 +2512,7 @@ i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
if (ret)
return ret;
}
- i915_gem_retire_requests(dev);
+ i915_gem_retire_requests(dev_priv);
/* Finally reset hw state */
for_each_engine(engine, dev_priv)
@@ -2534,7 +2532,7 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
/* HWS page needs to be set less than what we
* will inject to ring
*/
- ret = i915_gem_init_seqno(dev, seqno - 1);
+ ret = i915_gem_init_seqno(dev_priv, seqno - 1);
if (ret)
return ret;
@@ -2550,13 +2548,11 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
}
int
-i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
+i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
/* reserve 0 for non-seqno */
if (dev_priv->next_seqno == 0) {
- int ret = i915_gem_init_seqno(dev, 0);
+ int ret = i915_gem_init_seqno(dev_priv, 0);
if (ret)
return ret;
@@ -2654,7 +2650,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
/* Not allowed to fail! */
WARN(ret, "emit|add_request failed: %d!\n", ret);
- i915_queue_hangcheck(engine->dev);
+ i915_queue_hangcheck(engine->i915);
queue_delayed_work(dev_priv->wq,
&dev_priv->mm.retire_work,
@@ -2728,7 +2724,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
struct intel_context *ctx,
struct drm_i915_gem_request **req_out)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
struct drm_i915_gem_request *req;
int ret;
@@ -2750,7 +2746,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
if (req == NULL)
return -ENOMEM;
- ret = i915_gem_get_seqno(engine->dev, &req->seqno);
+ ret = i915_gem_get_seqno(engine->i915, &req->seqno);
if (ret)
goto err;
@@ -2807,7 +2803,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
int err;
if (ctx == NULL)
- ctx = to_i915(engine->dev)->kernel_context;
+ ctx = engine->i915->kernel_context;
err = __i915_gem_request_alloc(engine, ctx, &req);
return err ? ERR_PTR(err) : req;
}
@@ -2982,9 +2978,8 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
}
bool
-i915_gem_retire_requests(struct drm_device *dev)
+i915_gem_retire_requests(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *engine;
bool idle = true;
@@ -3017,7 +3012,7 @@ i915_gem_retire_work_handler(struct work_struct *work)
/* Come back later if the device is busy... */
idle = false;
if (mutex_trylock(&dev->struct_mutex)) {
- idle = i915_gem_retire_requests(dev);
+ idle = i915_gem_retire_requests(dev_priv);
mutex_unlock(&dev->struct_mutex);
}
if (!idle)
@@ -3186,7 +3181,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (i915_gem_request_completed(from_req, true))
return 0;
- if (!i915_semaphore_is_enabled(obj->base.dev)) {
+ if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
ret = __i915_wait_request(from_req,
i915->mm.interruptible,
@@ -3719,7 +3714,7 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
return;
if (i915_gem_clflush_object(obj, obj->pin_display))
- i915_gem_chipset_flush(obj->base.dev);
+ i915_gem_chipset_flush(to_i915(obj->base.dev));
old_write_domain = obj->base.write_domain;
obj->base.write_domain = 0;
@@ -3917,7 +3912,7 @@ out:
obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
cpu_write_needs_clflush(obj)) {
if (i915_gem_clflush_object(obj, true))
- i915_gem_chipset_flush(obj->base.dev);
+ i915_gem_chipset_flush(to_i915(obj->base.dev));
}
return 0;
@@ -4695,7 +4690,7 @@ i915_gem_suspend(struct drm_device *dev)
if (ret)
goto err;
- i915_gem_retire_requests(dev);
+ i915_gem_retire_requests(dev_priv);
i915_gem_stop_engines(dev);
i915_gem_context_lost(dev_priv);
@@ -4986,7 +4981,7 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
else
dev_priv->num_fence_regs = 8;
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
dev_priv->num_fence_regs =
I915_READ(vgtif_reg(avail_rs.fence_num));
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b1b704c2c001..2dcf18cfc809 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -99,28 +99,27 @@
#define GEN6_CONTEXT_ALIGN (64<<10)
#define GEN7_CONTEXT_ALIGN 4096
-static size_t get_context_alignment(struct drm_device *dev)
+static size_t get_context_alignment(struct drm_i915_private *dev_priv)
{
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
return GEN6_CONTEXT_ALIGN;
return GEN7_CONTEXT_ALIGN;
}
-static int get_context_size(struct drm_device *dev)
+static int get_context_size(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
u32 reg;
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev_priv)->gen) {
case 6:
reg = I915_READ(CXT_SIZE);
ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
break;
case 7:
reg = I915_READ(GEN7_CXT_SIZE);
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev_priv))
ret = HSW_CXT_TOTAL_SIZE;
else
ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
@@ -224,7 +223,7 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
* Flush any pending retires to hopefully release some
* stale contexts and try again.
*/
- i915_gem_retire_requests(dev_priv->dev);
+ i915_gem_retire_requests(dev_priv);
ret = ida_simple_get(&dev_priv->context_hw_ida,
0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
if (ret < 0)
@@ -320,7 +319,7 @@ i915_gem_create_context(struct drm_device *dev,
* context.
*/
ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
- get_context_alignment(dev), 0);
+ get_context_alignment(to_i915(dev)), 0);
if (ret) {
DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
goto err_destroy;
@@ -389,7 +388,8 @@ int i915_gem_context_init(struct drm_device *dev)
if (WARN_ON(dev_priv->kernel_context))
return 0;
- if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
+ if (intel_vgpu_active(dev_priv) &&
+ HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
if (!i915.enable_execlists) {
DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
return -EINVAL;
@@ -404,8 +404,9 @@ int i915_gem_context_init(struct drm_device *dev)
/* NB: intentionally left blank. We will allocate our own
* backing objects as we need them, thank you very much */
dev_priv->hw_context_size = 0;
- } else if (HAS_HW_CONTEXTS(dev)) {
- dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
+ } else if (HAS_HW_CONTEXTS(dev_priv)) {
+ dev_priv->hw_context_size =
+ round_up(get_context_size(dev_priv), 4096);
if (dev_priv->hw_context_size > (1<<20)) {
DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
dev_priv->hw_context_size);
@@ -509,12 +510,13 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
+ struct drm_i915_private *dev_priv = req->i915;
struct intel_engine_cs *engine = req->engine;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
/* Use an extended w/a on ivb+ if signalling from other rings */
- i915_semaphore_is_enabled(engine->dev) ?
- hweight32(INTEL_INFO(engine->dev)->ring_mask) - 1 :
+ i915_semaphore_is_enabled(dev_priv) ?
+ hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 :
0;
int len, ret;
@@ -523,21 +525,21 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
* explicitly, so we rely on the value at ring init, stored in
* itlb_before_ctx_switch.
*/
- if (IS_GEN6(engine->dev)) {
+ if (IS_GEN6(dev_priv)) {
ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
if (ret)
return ret;
}
/* These flags are for resource streamer on HSW+ */
- if (IS_HASWELL(engine->dev) || INTEL_INFO(engine->dev)->gen >= 8)
+ if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
- else if (INTEL_INFO(engine->dev)->gen < 8)
+ else if (INTEL_GEN(dev_priv) < 8)
flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
len = 4;
- if (INTEL_INFO(engine->dev)->gen >= 7)
+ if (INTEL_GEN(dev_priv) >= 7)
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
ret = intel_ring_begin(req, len);
@@ -545,14 +547,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
return ret;
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
- if (INTEL_INFO(engine->dev)->gen >= 7) {
+ if (INTEL_GEN(dev_priv) >= 7) {
intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
if (num_rings) {
struct intel_engine_cs *signaller;
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_engine(signaller, to_i915(engine->dev)) {
+ for_each_engine(signaller, dev_priv) {
if (signaller == engine)
continue;
@@ -575,14 +577,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
*/
intel_ring_emit(engine, MI_NOOP);
- if (INTEL_INFO(engine->dev)->gen >= 7) {
+ if (INTEL_GEN(dev_priv) >= 7) {
if (num_rings) {
struct intel_engine_cs *signaller;
i915_reg_t last_reg = {}; /* keep gcc quiet */
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_engine(signaller, to_i915(engine->dev)) {
+ for_each_engine(signaller, dev_priv) {
if (signaller == engine)
continue;
@@ -673,7 +675,7 @@ needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
if (engine->id != RCS)
return true;
- if (INTEL_INFO(engine->dev)->gen < 8)
+ if (INTEL_GEN(engine->i915) < 8)
return true;
return false;
@@ -710,7 +712,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
/* Trying to pin first makes error handling easier. */
ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
- get_context_alignment(engine->dev),
+ get_context_alignment(engine->i915),
0);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index ea1f8d1bd228..b144c3f5c650 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -154,7 +154,7 @@ none:
if (ret)
return ret;
- i915_gem_retire_requests(dev);
+ i915_gem_retire_requests(to_i915(dev));
goto search_again;
}
@@ -265,7 +265,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle)
if (ret)
return ret;
- i915_gem_retire_requests(vm->dev);
+ i915_gem_retire_requests(to_i915(vm->dev));
WARN_ON(!list_empty(&vm->active_list));
}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index e0ee5d1ac372..a54a243ccaac 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -724,7 +724,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
struct i915_address_space *vm;
struct list_head ordered_vmas;
struct list_head pinned_vmas;
- bool has_fenced_gpu_access = INTEL_INFO(engine->dev)->gen < 4;
+ bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
int retry;
i915_gem_retire_requests_ring(engine);
@@ -965,7 +965,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
}
if (flush_chipset)
- i915_gem_chipset_flush(req->engine->dev);
+ i915_gem_chipset_flush(req->engine->i915);
if (flush_domains & I915_GEM_DOMAIN_GTT)
wmb();
@@ -1119,7 +1119,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
i915_gem_request_assign(&obj->last_fenced_req, req);
if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
&dev_priv->mm.fence_list);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 364cf8236021..4e344707cebc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -110,17 +110,19 @@ const struct i915_ggtt_view i915_ggtt_view_rotated = {
.type = I915_GGTT_VIEW_ROTATED,
};
-int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
+int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
+ int enable_ppgtt)
{
bool has_aliasing_ppgtt;
bool has_full_ppgtt;
bool has_full_48bit_ppgtt;
- has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
- has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
- has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
+ has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6;
+ has_full_ppgtt = INTEL_GEN(dev_priv) >= 7;
+ has_full_48bit_ppgtt =
+ IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
has_full_ppgtt = false; /* emulation is too hard */
if (!has_aliasing_ppgtt)
@@ -130,7 +132,7 @@ int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
* We don't allow disabling PPGTT for gen9+ as it's a requirement for
* execlists, the sole mechanism available to submit work.
*/
- if (enable_ppgtt == 0 && INTEL_INFO(dev)->gen < 9)
+ if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
return 0;
if (enable_ppgtt == 1)
@@ -144,19 +146,19 @@ int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
#ifdef CONFIG_INTEL_IOMMU
/* Disable ppgtt on SNB if VT-d is on. */
- if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
+ if (INTEL_GEN(dev_priv) == 6 && intel_iommu_gfx_mapped) {
DRM_INFO("Disabling PPGTT because VT-d is on\n");
return 0;
}
#endif
/* Early VLV doesn't have this */
- if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
+ if (IS_VALLEYVIEW(dev_priv) && dev_priv->dev->pdev->revision < 0xb) {
DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
return 0;
}
- if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
+ if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists)
return has_full_48bit_ppgtt ? 3 : 2;
else
return has_aliasing_ppgtt ? 1 : 0;
@@ -994,7 +996,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
- if (intel_vgpu_active(vm->dev))
+ if (intel_vgpu_active(to_i915(vm->dev)))
gen8_ppgtt_notify_vgt(ppgtt, false);
if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
@@ -1545,14 +1547,14 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
0, 0,
GEN8_PML4E_SHIFT);
- if (intel_vgpu_active(ppgtt->base.dev)) {
+ if (intel_vgpu_active(to_i915(ppgtt->base.dev))) {
ret = gen8_preallocate_top_level_pdps(ppgtt);
if (ret)
goto free_scratch;
}
}
- if (intel_vgpu_active(ppgtt->base.dev))
+ if (intel_vgpu_active(to_i915(ppgtt->base.dev)))
gen8_ppgtt_notify_vgt(ppgtt, true);
return 0;
@@ -2080,7 +2082,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
} else
BUG();
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
ppgtt->switch_mm = vgpu_mm_switch;
ret = gen6_ppgtt_alloc(ppgtt);
@@ -2729,7 +2731,7 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
i915_address_space_init(&ggtt->base, dev_priv);
ggtt->base.total += PAGE_SIZE;
- if (intel_vgpu_active(dev)) {
+ if (intel_vgpu_active(dev_priv)) {
ret = intel_vgt_balloon(dev);
if (ret)
return ret;
@@ -2833,7 +2835,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
i915_gem_cleanup_stolen(dev);
if (drm_mm_initialized(&ggtt->base.mm)) {
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
intel_vgt_deballoon();
drm_mm_takedown(&ggtt->base.mm);
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 423cf5144bcb..7c93327b70fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -29,7 +29,7 @@
#include "intel_renderstate.h"
static const struct intel_renderstate_rodata *
-render_state_get_rodata(struct drm_device *dev, const int gen)
+render_state_get_rodata(const int gen)
{
switch (gen) {
case 6:
@@ -45,19 +45,20 @@ render_state_get_rodata(struct drm_device *dev, const int gen)
return NULL;
}
-static int render_state_init(struct render_state *so, struct drm_device *dev)
+static int render_state_init(struct render_state *so,
+ struct drm_i915_private *dev_priv)
{
int ret;
- so->gen = INTEL_INFO(dev)->gen;
- so->rodata = render_state_get_rodata(dev, so->gen);
+ so->gen = INTEL_GEN(dev_priv);
+ so->rodata = render_state_get_rodata(so->gen);
if (so->rodata == NULL)
return 0;
if (so->rodata->batch_items * 4 > 4096)
return -EINVAL;
- so->obj = i915_gem_object_create(dev, 4096);
+ so->obj = i915_gem_object_create(dev_priv->dev, 4096);
if (IS_ERR(so->obj))
return PTR_ERR(so->obj);
@@ -177,7 +178,7 @@ int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
if (WARN_ON(engine->id != RCS))
return -ENOENT;
- ret = render_state_init(so, engine->dev);
+ ret = render_state_init(so, engine->i915);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 79004f356174..538c30499848 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -131,7 +131,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
unsigned long count = 0;
trace_i915_gem_shrink(dev_priv, target, flags);
- i915_gem_retire_requests(dev_priv->dev);
+ i915_gem_retire_requests(dev_priv);
/*
* Unbinding of objects will require HW access; Let us not wake the
@@ -209,7 +209,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
if (flags & I915_SHRINK_BOUND)
intel_runtime_pm_put(dev_priv);
- i915_gem_retire_requests(dev_priv->dev);
+ i915_gem_retire_requests(dev_priv);
return count;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 89725c9efc25..22d926839b68 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -824,19 +824,18 @@ static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
return error_code;
}
-static void i915_gem_record_fences(struct drm_device *dev,
+static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
int i;
- if (IS_GEN3(dev) || IS_GEN2(dev)) {
+ if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
for (i = 0; i < dev_priv->num_fence_regs; i++)
error->fence[i] = I915_READ(FENCE_REG(i));
- } else if (IS_GEN5(dev) || IS_GEN4(dev)) {
+ } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
for (i = 0; i < dev_priv->num_fence_regs; i++)
error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
- } else if (INTEL_INFO(dev)->gen >= 6) {
+ } else if (INTEL_GEN(dev_priv) >= 6) {
for (i = 0; i < dev_priv->num_fence_regs; i++)
error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
}
@@ -851,7 +850,7 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
struct intel_engine_cs *to;
enum intel_engine_id id;
- if (!i915_semaphore_is_enabled(dev_priv->dev))
+ if (!i915_semaphore_is_enabled(dev_priv))
return;
if (!error->semaphore_obj)
@@ -893,31 +892,29 @@ static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
}
}
-static void i915_record_ring_state(struct drm_device *dev,
+static void i915_record_ring_state(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error,
struct intel_engine_cs *engine,
struct drm_i915_error_ring *ering)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- if (INTEL_INFO(dev)->gen >= 6) {
+ if (INTEL_GEN(dev_priv) >= 6) {
ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
- if (INTEL_INFO(dev)->gen >= 8)
+ if (INTEL_GEN(dev_priv) >= 8)
gen8_record_semaphore_state(dev_priv, error, engine,
ering);
else
gen6_record_semaphore_state(dev_priv, engine, ering);
}
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_GEN(dev_priv) >= 4) {
ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
}
@@ -939,10 +936,10 @@ static void i915_record_ring_state(struct drm_device *dev,
ering->tail = I915_READ_TAIL(engine);
ering->ctl = I915_READ_CTL(engine);
- if (I915_NEED_GFX_HWS(dev)) {
+ if (I915_NEED_GFX_HWS(dev_priv)) {
i915_reg_t mmio;
- if (IS_GEN7(dev)) {
+ if (IS_GEN7(dev_priv)) {
switch (engine->id) {
default:
case RCS:
@@ -958,7 +955,7 @@ static void i915_record_ring_state(struct drm_device *dev,
mmio = VEBOX_HWS_PGA_GEN7;
break;
}
- } else if (IS_GEN6(engine->dev)) {
+ } else if (IS_GEN6(engine->i915)) {
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
} else {
/* XXX: gen8 returns to sanity */
@@ -971,18 +968,18 @@ static void i915_record_ring_state(struct drm_device *dev,
ering->hangcheck_score = engine->hangcheck.score;
ering->hangcheck_action = engine->hangcheck.action;
- if (USES_PPGTT(dev)) {
+ if (USES_PPGTT(dev_priv)) {
int i;
ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
ering->vm_info.pp_dir_base =
I915_READ(RING_PP_DIR_BASE_READ(engine));
- else if (IS_GEN7(dev))
+ else if (IS_GEN7(dev_priv))
ering->vm_info.pp_dir_base =
I915_READ(RING_PP_DIR_BASE(engine));
- else if (INTEL_INFO(dev)->gen >= 8)
+ else if (INTEL_GEN(dev_priv) >= 8)
for (i = 0; i < 4; i++) {
ering->vm_info.pdp[i] =
I915_READ(GEN8_RING_PDP_UDW(engine, i));
@@ -998,7 +995,7 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
struct drm_i915_error_state *error,
struct drm_i915_error_ring *ering)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct drm_i915_gem_object *obj;
/* Currently render ring is the only HW context user */
@@ -1016,10 +1013,9 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
}
}
-static void i915_gem_record_rings(struct drm_device *dev,
+static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_ggtt *ggtt = &dev_priv->ggtt;
struct drm_i915_gem_request *request;
int i, count;
@@ -1030,12 +1026,12 @@ static void i915_gem_record_rings(struct drm_device *dev,
error->ring[i].pid = -1;
- if (engine->dev == NULL)
+ if (engine->i915 == NULL)
continue;
error->ring[i].valid = true;
- i915_record_ring_state(dev, error, engine, &error->ring[i]);
+ i915_record_ring_state(dev_priv, error, engine, &error->ring[i]);
request = i915_gem_find_active_request(engine);
if (request) {
@@ -1301,15 +1297,14 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
error->eir = I915_READ(EIR);
error->pgtbl_er = I915_READ(PGTBL_ER);
- i915_get_extra_instdone(dev, error->extra_instdone);
+ i915_get_extra_instdone(dev_priv, error->extra_instdone);
}
-static void i915_error_capture_msg(struct drm_device *dev,
+static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error,
u32 engine_mask,
const char *error_msg)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
u32 ecode;
int ring_id = -1, len;
@@ -1317,7 +1312,7 @@ static void i915_error_capture_msg(struct drm_device *dev,
len = scnprintf(error->error_msg, sizeof(error->error_msg),
"GPU HANG: ecode %d:%d:0x%08x",
- INTEL_INFO(dev)->gen, ring_id, ecode);
+ INTEL_INFO(dev_priv)->gen, ring_id, ecode);
if (ring_id != -1 && error->ring[ring_id].pid != -1)
len += scnprintf(error->error_msg + len,
@@ -1352,11 +1347,11 @@ static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
* out a structure which becomes available in debugfs for user level tools
* to pick up.
*/
-void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
+void i915_capture_error_state(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
const char *error_msg)
{
static bool warned;
- struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_error_state *error;
unsigned long flags;
@@ -1372,15 +1367,15 @@ void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
i915_capture_gen_state(dev_priv, error);
i915_capture_reg_state(dev_priv, error);
i915_gem_capture_buffers(dev_priv, error);
- i915_gem_record_fences(dev, error);
- i915_gem_record_rings(dev, error);
+ i915_gem_record_fences(dev_priv, error);
+ i915_gem_record_rings(dev_priv, error);
do_gettimeofday(&error->time);
- error->overlay = intel_overlay_capture_error_state(dev);
- error->display = intel_display_capture_error_state(dev);
+ error->overlay = intel_overlay_capture_error_state(dev_priv);
+ error->display = intel_display_capture_error_state(dev_priv);
- i915_error_capture_msg(dev, error, engine_mask, error_msg);
+ i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
DRM_INFO("%s\n", error->error_msg);
spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
@@ -1400,7 +1395,7 @@ void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
- DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
+ DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev_priv->dev->primary->index);
warned = true;
}
}
@@ -1450,17 +1445,17 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
}
/* NB: please notice the memset */
-void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
+void i915_get_extra_instdone(struct drm_i915_private *dev_priv,
+ uint32_t *instdone)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
- if (IS_GEN2(dev) || IS_GEN3(dev))
+ if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
instdone[0] = I915_READ(GEN2_INSTDONE);
- else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
+ else if (IS_GEN4(dev_priv) || IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) {
instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
instdone[1] = I915_READ(GEN4_INSTDONE1);
- } else if (INTEL_INFO(dev)->gen >= 7) {
+ } else if (INTEL_INFO(dev_priv)->gen >= 7) {
instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
instdone[1] = I915_READ(GEN7_SC_INSTDONE);
instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2f6fd33c07ba..8864ee19154f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2555,15 +2555,15 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
* Fire an error uevent so userspace can see that a hang or error
* was detected.
*/
-static void i915_reset_and_wakeup(struct drm_device *dev)
+static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
int ret;
- kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
+ kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
/*
* Note that there's only one work item which does gpu resets, so we
@@ -2577,8 +2577,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
*/
if (i915_reset_in_progress(&dev_priv->gpu_error)) {
DRM_DEBUG_DRIVER("resetting chip\n");
- kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
- reset_event);
+ kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
/*
* In most cases it's guaranteed that we get here with an RPM
@@ -2589,7 +2588,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
*/
intel_runtime_pm_get(dev_priv);
- intel_prepare_reset(dev);
+ intel_prepare_reset(dev_priv);
/*
* All state reset _must_ be completed before we update the
@@ -2597,14 +2596,14 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
* pending state and not properly drop locks, resulting in
* deadlocks with the reset work.
*/
- ret = i915_reset(dev);
+ ret = i915_reset(dev_priv);
- intel_finish_reset(dev);
+ intel_finish_reset(dev_priv);
intel_runtime_pm_put(dev_priv);
if (ret == 0)
- kobject_uevent_env(&dev->primary->kdev->kobj,
+ kobject_uevent_env(kobj,
KOBJ_CHANGE, reset_done_event);
/*
@@ -2615,9 +2614,8 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
}
}
-static void i915_report_and_clear_eir(struct drm_device *dev)
+static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t instdone[I915_NUM_INSTDONE_REG];
u32 eir = I915_READ(EIR);
int pipe, i;
@@ -2627,9 +2625,9 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
pr_err("render error detected, EIR: 0x%08x\n", eir);
- i915_get_extra_instdone(dev, instdone);
+ i915_get_extra_instdone(dev_priv, instdone);
- if (IS_G4X(dev)) {
+ if (IS_G4X(dev_priv)) {
if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
u32 ipeir = I915_READ(IPEIR_I965);
@@ -2651,7 +2649,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
}
}
- if (!IS_GEN2(dev)) {
+ if (!IS_GEN2(dev_priv)) {
if (eir & I915_ERROR_PAGE_TABLE) {
u32 pgtbl_err = I915_READ(PGTBL_ER);
pr_err("page table error\n");
@@ -2673,7 +2671,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
for (i = 0; i < ARRAY_SIZE(instdone); i++)
pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
- if (INTEL_INFO(dev)->gen < 4) {
+ if (INTEL_GEN(dev_priv) < 4) {
u32 ipeir = I915_READ(IPEIR);
pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
@@ -2717,10 +2715,10 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
* so userspace knows something bad happened (should trigger collection
* of a ring dump etc.).
*/
-void i915_handle_error(struct drm_device *dev, u32 engine_mask,
+void i915_handle_error(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
const char *fmt, ...)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
va_list args;
char error_msg[80];
@@ -2728,8 +2726,8 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
vscnprintf(error_msg, sizeof(error_msg), fmt, args);
va_end(args);
- i915_capture_error_state(dev, engine_mask, error_msg);
- i915_report_and_clear_eir(dev);
+ i915_capture_error_state(dev_priv, engine_mask, error_msg);
+ i915_report_and_clear_eir(dev_priv);
if (engine_mask) {
atomic_or(I915_RESET_IN_PROGRESS_FLAG,
@@ -2751,7 +2749,7 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
i915_error_wake_up(dev_priv, false);
}
- i915_reset_and_wakeup(dev);
+ i915_reset_and_wakeup(dev_priv);
}
/* Called from drm generic code, passed 'crtc' which
@@ -2869,9 +2867,9 @@ ring_idle(struct intel_engine_cs *engine, u32 seqno)
}
static bool
-ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
+ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr)
{
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
return (ipehr >> 23) == 0x1c;
} else {
ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
@@ -2884,10 +2882,10 @@ static struct intel_engine_cs *
semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
u64 offset)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct intel_engine_cs *signaller;
- if (INTEL_INFO(dev_priv)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
for_each_engine(signaller, dev_priv) {
if (engine == signaller)
continue;
@@ -2916,7 +2914,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
static struct intel_engine_cs *
semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u32 cmd, ipehr, head;
u64 offset = 0;
int i, backwards;
@@ -2942,7 +2940,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
return NULL;
ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
- if (!ipehr_is_semaphore_wait(engine->dev, ipehr))
+ if (!ipehr_is_semaphore_wait(engine->i915, ipehr))
return NULL;
/*
@@ -2954,7 +2952,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
* ringbuffer itself.
*/
head = I915_READ_HEAD(engine) & HEAD_ADDR;
- backwards = (INTEL_INFO(engine->dev)->gen >= 8) ? 5 : 4;
+ backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
for (i = backwards; i; --i) {
/*
@@ -2976,7 +2974,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
return NULL;
*seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
- if (INTEL_INFO(engine->dev)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
offset = ioread32(engine->buffer->virtual_start + head + 12);
offset <<= 32;
offset = ioread32(engine->buffer->virtual_start + head + 8);
@@ -2986,7 +2984,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
static int semaphore_passed(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct intel_engine_cs *signaller;
u32 seqno;
@@ -3028,7 +3026,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
if (engine->id != RCS)
return true;
- i915_get_extra_instdone(engine->dev, instdone);
+ i915_get_extra_instdone(engine->i915, instdone);
/* There might be unstable subunit states even when
* actual head is not moving. Filter out the unstable ones by
@@ -3069,8 +3067,7 @@ head_stuck(struct intel_engine_cs *engine, u64 acthd)
static enum intel_ring_hangcheck_action
ring_stuck(struct intel_engine_cs *engine, u64 acthd)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
enum intel_ring_hangcheck_action ha;
u32 tmp;
@@ -3078,7 +3075,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
if (ha != HANGCHECK_HUNG)
return ha;
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
return HANGCHECK_HUNG;
/* Is the chip hanging on a WAIT_FOR_EVENT?
@@ -3088,19 +3085,19 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
*/
tmp = I915_READ_CTL(engine);
if (tmp & RING_WAIT) {
- i915_handle_error(dev, 0,
+ i915_handle_error(dev_priv, 0,
"Kicking stuck wait on %s",
engine->name);
I915_WRITE_CTL(engine, tmp);
return HANGCHECK_KICK;
}
- if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
+ if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
switch (semaphore_passed(engine)) {
default:
return HANGCHECK_HUNG;
case 1:
- i915_handle_error(dev, 0,
+ i915_handle_error(dev_priv, 0,
"Kicking stuck semaphore on %s",
engine->name);
I915_WRITE_CTL(engine, tmp);
@@ -3115,7 +3112,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
static unsigned kick_waiters(struct intel_engine_cs *engine)
{
- struct drm_i915_private *i915 = to_i915(engine->dev);
+ struct drm_i915_private *i915 = engine->i915;
unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
if (engine->hangcheck.user_interrupts == user_interrupts &&
@@ -3144,7 +3141,6 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv),
gpu_error.hangcheck_work.work);
- struct drm_device *dev = dev_priv->dev;
struct intel_engine_cs *engine;
enum intel_engine_id id;
int busy_count = 0, rings_hung = 0;
@@ -3272,22 +3268,22 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
}
if (rings_hung) {
- i915_handle_error(dev, rings_hung, "Engine(s) hung");
+ i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
goto out;
}
if (busy_count)
/* Reset timer case chip hangs without another request
* being added */
- i915_queue_hangcheck(dev);
+ i915_queue_hangcheck(dev_priv);
out:
ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
}
-void i915_queue_hangcheck(struct drm_device *dev)
+void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
- struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
+ struct i915_gpu_error *e = &dev_priv->gpu_error;
if (!i915.enable_hangcheck)
return;
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index dc0def210097..20b2e4039792 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -462,7 +462,7 @@ TRACE_EVENT(i915_gem_ring_sync_to,
),
TP_fast_assign(
- __entry->dev = from->dev->primary->index;
+ __entry->dev = from->i915->dev->primary->index;
__entry->sync_from = from->id;
__entry->sync_to = to_req->engine->id;
__entry->seqno = i915_gem_request_get_seqno(req);
@@ -486,13 +486,11 @@ TRACE_EVENT(i915_gem_ring_dispatch,
),
TP_fast_assign(
- struct intel_engine_cs *engine =
- i915_gem_request_get_engine(req);
- __entry->dev = engine->dev->primary->index;
- __entry->ring = engine->id;
- __entry->seqno = i915_gem_request_get_seqno(req);
+ __entry->dev = req->i915->dev->primary->index;
+ __entry->ring = req->engine->id;
+ __entry->seqno = req->seqno;
__entry->flags = flags;
- i915_trace_irq_get(engine, req);
+ i915_trace_irq_get(req->engine, req);
),
TP_printk("dev=%u, ring=%u, seqno=%u, flags=%x",
@@ -511,7 +509,7 @@ TRACE_EVENT(i915_gem_ring_flush,
),
TP_fast_assign(
- __entry->dev = req->engine->dev->primary->index;
+ __entry->dev = req->i915->dev->primary->index;
__entry->ring = req->engine->id;
__entry->invalidate = invalidate;
__entry->flush = flush;
@@ -533,11 +531,9 @@ DECLARE_EVENT_CLASS(i915_gem_request,
),
TP_fast_assign(
- struct intel_engine_cs *engine =
- i915_gem_request_get_engine(req);
- __entry->dev = engine->dev->primary->index;
- __entry->ring = engine->id;
- __entry->seqno = i915_gem_request_get_seqno(req);
+ __entry->dev = req->i915->dev->primary->index;
+ __entry->ring = req->engine->id;
+ __entry->seqno = req->seqno;
),
TP_printk("dev=%u, ring=%u, seqno=%u",
@@ -560,7 +556,7 @@ TRACE_EVENT(i915_gem_request_notify,
),
TP_fast_assign(
- __entry->dev = engine->dev->primary->index;
+ __entry->dev = engine->i915->dev->primary->index;
__entry->ring = engine->id;
__entry->seqno = engine->get_seqno(engine);
),
@@ -597,13 +593,11 @@ TRACE_EVENT(i915_gem_request_wait_begin,
* less desirable.
*/
TP_fast_assign(
- struct intel_engine_cs *engine =
- i915_gem_request_get_engine(req);
- __entry->dev = engine->dev->primary->index;
- __entry->ring = engine->id;
- __entry->seqno = i915_gem_request_get_seqno(req);
+ __entry->dev = req->i915->dev->primary->index;
+ __entry->ring = req->engine->id;
+ __entry->seqno = req->seqno;
__entry->blocking =
- mutex_is_locked(&engine->dev->struct_mutex);
+ mutex_is_locked(&req->i915->dev->struct_mutex);
),
TP_printk("dev=%u, ring=%u, seqno=%u, blocking=%s",
@@ -792,7 +786,7 @@ TRACE_EVENT(switch_mm,
__entry->ring = engine->id;
__entry->to = to;
__entry->vm = to->ppgtt? &to->ppgtt->base : NULL;
- __entry->dev = engine->dev->primary->index;
+ __entry->dev = engine->i915->dev->primary->index;
),
TP_printk("dev=%u, ring=%u, ctx=%p, ctx_vm=%p",
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 45c218db86be..6e2e2b98d323 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3144,41 +3144,39 @@ static void intel_update_primary_planes(struct drm_device *dev)
}
}
-void intel_prepare_reset(struct drm_device *dev)
+void intel_prepare_reset(struct drm_i915_private *dev_priv)
{
/* no reset support for gen2 */
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
return;
/* reset doesn't touch the display */
- if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+ if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
return;
- drm_modeset_lock_all(dev);
+ drm_modeset_lock_all(dev_priv->dev);
/*
* Disabling the crtcs gracefully seems nicer. Also the
* g33 docs say we should at least disable all the planes.
*/
- intel_display_suspend(dev);
+ intel_display_suspend(dev_priv->dev);
}
-void intel_finish_reset(struct drm_device *dev)
+void intel_finish_reset(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
/*
* Flips in the rings will be nuked by the reset,
* so complete all pending flips so that user space
* will get its events and not get stuck.
*/
- intel_complete_page_flips(dev);
+ intel_complete_page_flips(dev_priv->dev);
/* no reset support for gen2 */
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
return;
/* reset doesn't touch the display */
- if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
+ if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
/*
* Flips in the rings have been nuked by the reset,
* so update the base address of all primary
@@ -3188,7 +3186,7 @@ void intel_finish_reset(struct drm_device *dev)
* FIXME: Atomic will make this obsolete since we won't schedule
* CS-based flips (which might get lost in gpu resets) any more.
*/
- intel_update_primary_planes(dev);
+ intel_update_primary_planes(dev_priv->dev);
return;
}
@@ -3199,18 +3197,18 @@ void intel_finish_reset(struct drm_device *dev)
intel_runtime_pm_disable_interrupts(dev_priv);
intel_runtime_pm_enable_interrupts(dev_priv);
- intel_modeset_init_hw(dev);
+ intel_modeset_init_hw(dev_priv->dev);
spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display.hpd_irq_setup)
- dev_priv->display.hpd_irq_setup(dev);
+ dev_priv->display.hpd_irq_setup(dev_priv->dev);
spin_unlock_irq(&dev_priv->irq_lock);
- intel_display_resume(dev);
+ intel_display_resume(dev_priv->dev);
intel_hpd_init(dev_priv);
- drm_modeset_unlock_all(dev);
+ drm_modeset_unlock_all(dev_priv->dev);
}
static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
@@ -11256,7 +11254,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
if (engine == NULL)
return true;
- if (INTEL_INFO(engine->dev)->gen < 5)
+ if (INTEL_GEN(engine->i915) < 5)
return false;
if (i915.use_mmio_flip < 0)
@@ -16185,9 +16183,8 @@ struct intel_display_error_state {
};
struct intel_display_error_state *
-intel_display_capture_error_state(struct drm_device *dev)
+intel_display_capture_error_state(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_display_error_state *error;
int transcoders[] = {
TRANSCODER_A,
@@ -16197,14 +16194,14 @@ intel_display_capture_error_state(struct drm_device *dev)
};
int i;
- if (INTEL_INFO(dev)->num_pipes == 0)
+ if (INTEL_INFO(dev_priv)->num_pipes == 0)
return NULL;
error = kzalloc(sizeof(*error), GFP_ATOMIC);
if (error == NULL)
return NULL;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
for_each_pipe(dev_priv, i) {
@@ -16220,25 +16217,25 @@ intel_display_capture_error_state(struct drm_device *dev)
error->plane[i].control = I915_READ(DSPCNTR(i));
error->plane[i].stride = I915_READ(DSPSTRIDE(i));
- if (INTEL_INFO(dev)->gen <= 3) {
+ if (INTEL_GEN(dev_priv) <= 3) {
error->plane[i].size = I915_READ(DSPSIZE(i));
error->plane[i].pos = I915_READ(DSPPOS(i));
}
- if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
+ if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
error->plane[i].addr = I915_READ(DSPADDR(i));
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_GEN(dev_priv) >= 4) {
error->plane[i].surface = I915_READ(DSPSURF(i));
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
}
error->pipe[i].source = I915_READ(PIPESRC(i));
- if (HAS_GMCH_DISPLAY(dev))
+ if (HAS_GMCH_DISPLAY(dev_priv))
error->pipe[i].stat = I915_READ(PIPESTAT(i));
}
/* Note: this does not include DSI transcoders. */
- error->num_transcoders = INTEL_INFO(dev)->num_pipes;
+ error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
if (HAS_DDI(dev_priv))
error->num_transcoders++; /* Account for eDP. */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 51058522741a..66de61669884 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1226,8 +1226,8 @@ u32 intel_compute_tile_offset(int *x, int *y,
const struct drm_framebuffer *fb, int plane,
unsigned int pitch,
unsigned int rotation);
-void intel_prepare_reset(struct drm_device *dev);
-void intel_finish_reset(struct drm_device *dev);
+void intel_prepare_reset(struct drm_i915_private *dev_priv);
+void intel_finish_reset(struct drm_i915_private *dev_priv);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void broxton_init_cdclk(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index d5a7cfec589b..4a527d3cf026 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -827,7 +827,7 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc)
bool enable_by_default = IS_HASWELL(dev_priv) ||
IS_BROADWELL(dev_priv);
- if (intel_vgpu_active(dev_priv->dev)) {
+ if (intel_vgpu_active(dev_priv)) {
fbc->no_fbc_reason = "VGPU is active";
return false;
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8106316ce56f..e76280d5cdff 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -246,21 +246,22 @@ static int intel_lr_context_pin(struct intel_context *ctx,
*
* Return: 1 if Execlists is supported and has to be enabled.
*/
-int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
+int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
{
/* On platforms with execlist available, vGPU will only
* support execlist mode, no ring buffer mode.
*/
- if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
+ if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
return 1;
- if (INTEL_INFO(dev)->gen >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
return 1;
if (enable_execlists == 0)
return 0;
- if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
+ if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
+ USES_PPGTT(dev_priv) &&
i915.use_mmio_flip >= 0)
return 1;
@@ -270,19 +271,19 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists
static void
logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
+ struct drm_i915_private *dev_priv = engine->i915;
- if (IS_GEN8(dev) || IS_GEN9(dev))
+ if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
engine->idle_lite_restore_wa = ~0;
- engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
+ engine->disable_lite_restore_wa = (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
(engine->id == VCS || engine->id == VCS2);
engine->ctx_desc_template = GEN8_CTX_VALID;
- engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
+ engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
GEN8_CTX_ADDRESSING_MODE_SHIFT;
- if (IS_GEN8(dev))
+ if (IS_GEN8(dev_priv))
engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
@@ -342,8 +343,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
{
struct intel_engine_cs *engine = rq0->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = rq0->i915;
uint64_t desc[2];
if (rq1) {
@@ -425,7 +425,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
* If irqs are not active generate a warning as batches that finish
* without the irqs may get lost and a GPU Hang may occur.
*/
- WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
+ WARN_ON(!intel_irqs_enabled(engine->i915));
/* Try to read in pairs */
list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
@@ -497,7 +497,7 @@ static u32
get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
u32 *context_id)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u32 status;
read_pointer %= GEN8_CSB_ENTRIES;
@@ -523,7 +523,7 @@ get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
static void intel_lrc_irq_handler(unsigned long data)
{
struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u32 status_pointer;
unsigned int read_pointer, write_pointer;
u32 csb[GEN8_CSB_ENTRIES][2];
@@ -884,7 +884,7 @@ void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
struct drm_i915_gem_request *req, *tmp;
LIST_HEAD(cancel_list);
- WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
+ WARN_ON(!mutex_is_locked(&engine->i915->dev->struct_mutex));
spin_lock_bh(&engine->execlist_lock);
list_replace_init(&engine->execlist_queue, &cancel_list);
@@ -898,7 +898,7 @@ void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
void intel_logical_ring_stop(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
if (!intel_engine_initialized(engine))
@@ -964,7 +964,7 @@ static int intel_lr_context_pin(struct intel_context *ctx,
lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
ringbuf = ctx->engine[engine->id].ringbuf;
- ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
+ ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
if (ret)
goto unpin_map;
@@ -1019,9 +1019,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
int ret, i;
struct intel_engine_cs *engine = req->engine;
struct intel_ringbuffer *ringbuf = req->ringbuf;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct i915_workarounds *w = &dev_priv->workarounds;
+ struct i915_workarounds *w = &req->i915->workarounds;
if (w->count == 0)
return 0;
@@ -1092,7 +1090,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
* this batch updates GEN8_L3SQCREG4 with default value we need to
* set this bit here to retain the WA during flush.
*/
- if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
+ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0))
l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
@@ -1181,7 +1179,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
- if (IS_BROADWELL(engine->dev)) {
+ if (IS_BROADWELL(engine->i915)) {
int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
if (rc < 0)
return rc;
@@ -1253,12 +1251,11 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
uint32_t *offset)
{
int ret;
- struct drm_device *dev = engine->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
/* WaDisableCtxRestoreArbitration:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
+ IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
@@ -1279,12 +1276,11 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
uint32_t *const batch,
uint32_t *offset)
{
- struct drm_device *dev = engine->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
wa_ctx_emit(batch, index,
@@ -1293,7 +1289,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
}
/* WaClearTdlStateAckDirtyBits:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
+ if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
@@ -1312,8 +1308,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
}
/* WaDisableCtxRestoreArbitration:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
+ IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
@@ -1325,7 +1321,7 @@ static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
{
int ret;
- engine->wa_ctx.obj = i915_gem_object_create(engine->dev,
+ engine->wa_ctx.obj = i915_gem_object_create(engine->i915->dev,
PAGE_ALIGN(size));
if (IS_ERR(engine->wa_ctx.obj)) {
DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
@@ -1365,9 +1361,9 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
WARN_ON(engine->id != RCS);
/* update this when WA for higher Gen are added */
- if (INTEL_INFO(engine->dev)->gen > 9) {
+ if (INTEL_GEN(engine->i915) > 9) {
DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
- INTEL_INFO(engine->dev)->gen);
+ INTEL_GEN(engine->i915));
return 0;
}
@@ -1387,7 +1383,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
batch = kmap_atomic(page);
offset = 0;
- if (INTEL_INFO(engine->dev)->gen == 8) {
+ if (INTEL_GEN(engine->i915) == 8) {
ret = gen8_init_indirectctx_bb(engine,
&wa_ctx->indirect_ctx,
batch,
@@ -1401,7 +1397,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
&offset);
if (ret)
goto out;
- } else if (INTEL_INFO(engine->dev)->gen == 9) {
+ } else if (INTEL_GEN(engine->i915) == 9) {
ret = gen9_init_indirectctx_bb(engine,
&wa_ctx->indirect_ctx,
batch,
@@ -1427,7 +1423,7 @@ out:
static void lrc_init_hws(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
(u32)engine->status_page.gfx_addr);
@@ -1436,8 +1432,7 @@ static void lrc_init_hws(struct intel_engine_cs *engine)
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned int next_context_status_buffer_hw;
lrc_init_hws(engine);
@@ -1484,8 +1479,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
static int gen8_init_render_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
ret = gen8_init_common_ring(engine);
@@ -1562,7 +1556,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
if (req->ctx->ppgtt &&
(intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
if (!USES_FULL_48BIT_PPGTT(req->i915) &&
- !intel_vgpu_active(req->i915->dev)) {
+ !intel_vgpu_active(req->i915)) {
ret = intel_logical_ring_emit_pdps(req);
if (ret)
return ret;
@@ -1590,8 +1584,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1610,8 +1603,7 @@ static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1628,8 +1620,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
{
struct intel_ringbuffer *ringbuf = request->ringbuf;
struct intel_engine_cs *engine = ringbuf->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = request->i915;
uint32_t cmd;
int ret;
@@ -1697,7 +1688,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
* On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
* pipe control.
*/
- if (IS_GEN9(engine->dev))
+ if (IS_GEN9(request->i915))
vf_flush_wa = true;
}
@@ -1890,7 +1881,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
tasklet_kill(&engine->irq_tasklet);
- dev_priv = engine->dev->dev_private;
+ dev_priv = engine->i915;
if (engine->buffer) {
intel_logical_ring_stop(engine);
@@ -1914,7 +1905,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
engine->ctx_desc_template = 0;
lrc_destroy_wa_ctx_obj(engine);
- engine->dev = NULL;
+ engine->i915 = NULL;
}
static void
@@ -1929,7 +1920,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_bb_start = gen8_emit_bb_start;
engine->get_seqno = gen8_get_seqno;
engine->set_seqno = gen8_set_seqno;
- if (IS_BXT_REVID(engine->dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
engine->irq_seqno_barrier = bxt_a_seqno_barrier;
engine->set_seqno = bxt_a_set_seqno;
}
@@ -2023,7 +2014,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
I915_WRITE_IMR(engine, ~0);
POSTING_READ(RING_IMR(engine->mmio_base));
- engine->dev = dev;
+ engine->i915 = dev_priv;
/* Intentionally left blank. */
engine->buffer = NULL;
@@ -2056,7 +2047,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
logical_ring_default_irqs(engine, info->irq_shift);
intel_engine_init_hangcheck(engine);
- i915_gem_batch_pool_init(engine->dev, &engine->batch_pool);
+ i915_gem_batch_pool_init(dev, &engine->batch_pool);
return engine;
}
@@ -2064,7 +2055,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
static int
logical_ring_init(struct intel_engine_cs *engine)
{
- struct intel_context *dctx = to_i915(engine->dev)->kernel_context;
+ struct intel_context *dctx = engine->i915->kernel_context;
int ret;
ret = i915_cmd_parser_init_ring(engine);
@@ -2224,7 +2215,7 @@ cleanup_render_ring:
}
static u32
-make_rpcs(struct drm_device *dev)
+make_rpcs(struct drm_i915_private *dev_priv)
{
u32 rpcs = 0;
@@ -2232,7 +2223,7 @@ make_rpcs(struct drm_device *dev)
* No explicit RPCS request is needed to ensure full
* slice/subslice/EU enablement prior to Gen9.
*/
- if (INTEL_INFO(dev)->gen < 9)
+ if (INTEL_GEN(dev_priv) < 9)
return 0;
/*
@@ -2241,24 +2232,24 @@ make_rpcs(struct drm_device *dev)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (INTEL_INFO(dev)->has_slice_pg) {
+ if (INTEL_INFO(dev_priv)->has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
- rpcs |= INTEL_INFO(dev)->slice_total <<
+ rpcs |= INTEL_INFO(dev_priv)->slice_total <<
GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev)->has_subslice_pg) {
+ if (INTEL_INFO(dev_priv)->has_subslice_pg) {
rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
- rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
+ rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice <<
GEN8_RPCS_SS_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev)->has_eu_pg) {
- rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
+ if (INTEL_INFO(dev_priv)->has_eu_pg) {
+ rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
GEN8_RPCS_EU_MIN_SHIFT;
- rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
+ rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
GEN8_RPCS_EU_MAX_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
@@ -2270,9 +2261,9 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
{
u32 indirect_ctx_offset;
- switch (INTEL_INFO(engine->dev)->gen) {
+ switch (INTEL_GEN(engine->i915)) {
default:
- MISSING_CASE(INTEL_INFO(engine->dev)->gen);
+ MISSING_CASE(INTEL_GEN(engine->i915));
/* fall through */
case 9:
indirect_ctx_offset =
@@ -2293,8 +2284,7 @@ populate_lr_context(struct intel_context *ctx,
struct intel_engine_cs *engine,
struct intel_ringbuffer *ringbuf)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = ctx->i915;
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
void *vaddr;
u32 *reg_state;
@@ -2332,7 +2322,7 @@ populate_lr_context(struct intel_context *ctx,
RING_CONTEXT_CONTROL(engine),
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
- (HAS_RESOURCE_STREAMER(dev) ?
+ (HAS_RESOURCE_STREAMER(dev_priv) ?
CTX_CTRL_RS_CTX_ENABLE : 0)));
ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
0);
@@ -2421,7 +2411,7 @@ populate_lr_context(struct intel_context *ctx,
if (engine->id == RCS) {
reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
- make_rpcs(dev));
+ make_rpcs(dev_priv));
}
i915_gem_object_unpin_map(ctx_obj);
@@ -2472,11 +2462,11 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
{
int ret = 0;
- WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
+ WARN_ON(INTEL_GEN(engine->i915) < 8);
switch (engine->id) {
case RCS:
- if (INTEL_INFO(engine->dev)->gen >= 9)
+ if (INTEL_GEN(engine->i915) >= 9)
ret = GEN9_LR_CONTEXT_RENDER_SIZE;
else
ret = GEN8_LR_CONTEXT_RENDER_SIZE;
@@ -2508,7 +2498,7 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
static int execlists_context_deferred_alloc(struct intel_context *ctx,
struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
+ struct drm_device *dev = engine->i915->dev;
struct drm_i915_gem_object *ctx_obj;
uint32_t context_size;
struct intel_ringbuffer *ringbuf;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 229b8a974262..1afba0331dc6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -112,7 +112,8 @@ uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
struct intel_engine_cs *engine);
/* Execlists */
-int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
+int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
+ int enable_execlists);
struct i915_execbuffer_params;
int intel_execlists_submission(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 6ba4bf7f2a89..b765c75f3fcd 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -189,7 +189,7 @@ static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
*/
int intel_mocs_init_engine(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
struct drm_i915_mocs_table table;
unsigned int index;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 8570c60c6fc0..4a1e774ba8cc 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1508,9 +1508,8 @@ static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
struct intel_overlay_error_state *
-intel_overlay_capture_error_state(struct drm_device *dev)
+intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_overlay *overlay = dev_priv->overlay;
struct intel_overlay_error_state *error;
struct overlay_registers __iomem *regs;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 017c431f9363..ba097f2dd561 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6349,7 +6349,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
/* Powersaving is controlled by the host when inside a VM */
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
return;
if (IS_IRONLAKE_M(dev)) {
@@ -7405,8 +7405,7 @@ static void __intel_rps_boost_work(struct work_struct *work)
struct drm_i915_gem_request *req = boost->req;
if (!i915_gem_request_completed(req, true))
- gen6_rps_boost(to_i915(req->engine->dev), NULL,
- req->emitted_jiffies);
+ gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
i915_gem_request_unreference(req);
kfree(boost);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8f3eb3033da0..e8a28b0ccab9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -60,7 +60,7 @@ void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
bool intel_engine_stopped(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
}
@@ -106,7 +106,6 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
u32 flush_domains)
{
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
u32 cmd;
int ret;
@@ -145,7 +144,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
cmd |= MI_EXE_FLUSH;
if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
- (IS_G4X(dev) || IS_GEN5(dev)))
+ (IS_G4X(req->i915) || IS_GEN5(req->i915)))
cmd |= MI_INVALIDATE_ISP;
ret = intel_ring_begin(req, 2);
@@ -431,19 +430,19 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
static void ring_write_tail(struct intel_engine_cs *engine,
u32 value)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
I915_WRITE_TAIL(engine, value);
}
u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u64 acthd;
- if (INTEL_INFO(engine->dev)->gen >= 8)
+ if (INTEL_GEN(dev_priv) >= 8)
acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
RING_ACTHD_UDW(engine->mmio_base));
- else if (INTEL_INFO(engine->dev)->gen >= 4)
+ else if (INTEL_GEN(dev_priv) >= 4)
acthd = I915_READ(RING_ACTHD(engine->mmio_base));
else
acthd = I915_READ(ACTHD);
@@ -453,25 +452,24 @@ u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u32 addr;
addr = dev_priv->status_page_dmah->busaddr;
- if (INTEL_INFO(engine->dev)->gen >= 4)
+ if (INTEL_GEN(dev_priv) >= 4)
addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
I915_WRITE(HWS_PGA, addr);
}
static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
i915_reg_t mmio;
/* The ring status page addresses are no longer next to the rest of
* the ring registers as of gen7.
*/
- if (IS_GEN7(dev)) {
+ if (IS_GEN7(dev_priv)) {
switch (engine->id) {
case RCS:
mmio = RENDER_HWS_PGA_GEN7;
@@ -491,7 +489,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
mmio = VEBOX_HWS_PGA_GEN7;
break;
}
- } else if (IS_GEN6(engine->dev)) {
+ } else if (IS_GEN6(dev_priv)) {
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
} else {
/* XXX: gen8 returns to sanity */
@@ -508,7 +506,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
* arises: do we still need this and if so how should we go about
* invalidating the TLB?
*/
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8) {
i915_reg_t reg = RING_INSTPM(engine->mmio_base);
/* ring should be idle before issuing a sync flush*/
@@ -526,9 +524,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
static bool stop_ring(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
- if (!IS_GEN2(engine->dev)) {
+ if (!IS_GEN2(dev_priv)) {
I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
DRM_ERROR("%s : timed out trying to stop ring\n",
@@ -546,7 +544,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
I915_WRITE_HEAD(engine, 0);
engine->write_tail(engine, 0);
- if (!IS_GEN2(engine->dev)) {
+ if (!IS_GEN2(dev_priv)) {
(void)I915_READ_CTL(engine);
I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
}
@@ -561,8 +559,7 @@ void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
static int init_ring_common(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct intel_ringbuffer *ringbuf = engine->buffer;
struct drm_i915_gem_object *obj = ringbuf->obj;
int ret = 0;
@@ -592,7 +589,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
}
}
- if (I915_NEED_GFX_HWS(dev))
+ if (I915_NEED_GFX_HWS(dev_priv))
intel_ring_setup_status_page(engine);
else
ring_setup_phys_status_page(engine);
@@ -649,12 +646,10 @@ out:
void
intel_fini_pipe_control(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
-
if (engine->scratch.obj == NULL)
return;
- if (INTEL_INFO(dev)->gen >= 5) {
+ if (INTEL_GEN(engine->i915) >= 5) {
kunmap(sg_page(engine->scratch.obj->pages->sgl));
i915_gem_object_ggtt_unpin(engine->scratch.obj);
}
@@ -670,7 +665,7 @@ intel_init_pipe_control(struct intel_engine_cs *engine)
WARN_ON(engine->scratch.obj);
- engine->scratch.obj = i915_gem_object_create(engine->dev, 4096);
+ engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
if (IS_ERR(engine->scratch.obj)) {
DRM_ERROR("Failed to allocate seqno page\n");
ret = PTR_ERR(engine->scratch.obj);
@@ -708,11 +703,9 @@ err:
static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
- int ret, i;
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct i915_workarounds *w = &dev_priv->workarounds;
+ struct i915_workarounds *w = &req->i915->workarounds;
+ int ret, i;
if (w->count == 0)
return 0;
@@ -801,7 +794,7 @@ static int wa_add(struct drm_i915_private *dev_priv,
static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
i915_reg_t reg)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct i915_workarounds *wa = &dev_priv->workarounds;
const uint32_t index = wa->hw_whitelist_count[engine->id];
@@ -817,8 +810,7 @@ static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
static int gen8_init_workarounds(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
@@ -869,9 +861,8 @@ static int gen8_init_workarounds(struct intel_engine_cs *engine)
static int bdw_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen8_init_workarounds(engine);
if (ret)
@@ -891,16 +882,15 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
/* WaForceContextSaveRestoreNonCoherent:bdw */
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
- (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
+ (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
return 0;
}
static int chv_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen8_init_workarounds(engine);
if (ret)
@@ -917,8 +907,7 @@ static int chv_init_workarounds(struct intel_engine_cs *engine)
static int gen9_init_workarounds(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
uint32_t tmp;
int ret;
@@ -941,14 +930,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_DG_MIRROR_FIX_ENABLE);
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
GEN9_RHWO_OPTIMIZATION_DISABLE);
/*
@@ -974,20 +963,20 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
GEN9_CCS_TLB_PREFETCH_ENABLE);
/* WaDisableMaskBasedCammingInRCC:skl,bxt */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE);
/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
- if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
- IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_F0, REVID_FOREVER) ||
+ IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
- if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
+ if (IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
@@ -1013,8 +1002,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u8 vals[3] = { 0, 0, 0 };
unsigned int i;
@@ -1055,9 +1043,8 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
static int skl_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen9_init_workarounds(engine);
if (ret)
@@ -1068,12 +1055,12 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
* until D0 which is the default case so this is equivalent to
* !WaDisablePerCtxtPreemptionGranularityControl:skl
*/
- if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
- if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
I915_WRITE(FF_SLICE_CS_CHICKEN2,
_MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
@@ -1082,24 +1069,24 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
* involving this register should also be added to WA batch as required.
*/
- if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
/* WaDisableLSQCROPERFforOCL:skl */
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_RO_PERF_DIS);
/* WaEnableGapsTsvCreditFix:skl */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN9_GAPS_TSV_CREDIT_DISABLE));
}
/* WaDisablePowerCompilerClockGating:skl */
- if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
WA_SET_BIT_MASKED(HIZ_CHICKEN,
BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
/* This is tied to WaForceContextSaveRestoreNonCoherent */
- if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
+ if (IS_SKL_REVID(dev_priv, 0, REVID_FOREVER)) {
/*
*Use Force Non-Coherent whenever executing a 3D context. This
* is a workaround for a possible hang in the unlikely event
@@ -1115,13 +1102,13 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
}
/* WaBarrierPerformanceFixDisable:skl */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
WA_SET_BIT_MASKED(HDC_CHICKEN0,
HDC_FENCE_DEST_SLM_DISABLE |
HDC_BARRIER_PERFORMANCE_DISABLE);
/* WaDisableSbeCacheDispatchPortSharing:skl */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
WA_SET_BIT_MASKED(
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
@@ -1136,9 +1123,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
static int bxt_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen9_init_workarounds(engine);
if (ret)
@@ -1146,11 +1132,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaStoreMultiplePTEenable:bxt */
/* This is a requirement according to Hardware specification */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
/* WaSetClckGatingDisableMedia:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
}
@@ -1160,7 +1146,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
STALL_DOP_GATING_DISABLE);
/* WaDisableSbeCacheDispatchPortSharing:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
WA_SET_BIT_MASKED(
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
@@ -1170,7 +1156,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
/* WaDisableObjectLevelPreemtionForInstanceId:bxt */
/* WaDisableLSQCROPERFforOCL:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
if (ret)
return ret;
@@ -1181,7 +1167,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
}
/* WaProgramL3SqcReg1DefaultForPerf:bxt */
- if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
+ if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
L3_HIGH_PRIO_CREDITS(2));
@@ -1190,24 +1176,23 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
int init_workarounds_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
WARN_ON(engine->id != RCS);
dev_priv->workarounds.count = 0;
dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
- if (IS_BROADWELL(dev))
+ if (IS_BROADWELL(dev_priv))
return bdw_init_workarounds(engine);
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
return chv_init_workarounds(engine);
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(dev_priv))
return skl_init_workarounds(engine);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
return bxt_init_workarounds(engine);
return 0;
@@ -1215,14 +1200,13 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
static int init_render_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
int ret = init_ring_common(engine);
if (ret)
return ret;
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
- if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
+ if (INTEL_GEN(dev_priv) >= 4 && INTEL_GEN(dev_priv) < 7)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
/* We need to disable the AsyncFlip performance optimisations in order
@@ -1231,22 +1215,22 @@ static int init_render_ring(struct intel_engine_cs *engine)
*
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
*/
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
+ if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
/* Required for the hardware to program scanline values for waiting */
/* WaEnableFlushTlbInvalidationMode:snb */
- if (INTEL_INFO(dev)->gen == 6)
+ if (INTEL_GEN(dev_priv) == 6)
I915_WRITE(GFX_MODE,
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
- if (IS_GEN7(dev))
+ if (IS_GEN7(dev_priv))
I915_WRITE(GFX_MODE_GEN7,
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(dev_priv)) {
/* From the Sandybridge PRM, volume 1 part 3, page 24:
* "If this bit is set, STCunit will have LRA as replacement
* policy. [...] This bit must be reset. LRA replacement
@@ -1256,19 +1240,18 @@ static int init_render_ring(struct intel_engine_cs *engine)
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
}
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
+ if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
- if (HAS_L3_DPF(dev))
- I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
+ if (HAS_L3_DPF(dev_priv))
+ I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
return init_workarounds_ring(engine);
}
static void render_ring_cleanup(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
if (dev_priv->semaphore_obj) {
i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
@@ -1284,13 +1267,12 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
{
#define MBOX_UPDATE_DWORDS 8
struct intel_engine_cs *signaller = signaller_req->engine;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
#undef MBOX_UPDATE_DWORDS
@@ -1326,13 +1308,12 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
{
#define MBOX_UPDATE_DWORDS 6
struct intel_engine_cs *signaller = signaller_req->engine;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
#undef MBOX_UPDATE_DWORDS
@@ -1365,14 +1346,13 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
struct intel_engine_cs *signaller = signaller_req->engine;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *useless;
enum intel_engine_id id;
int ret, num_rings;
#define MBOX_UPDATE_DWORDS 3
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
#undef MBOX_UPDATE_DWORDS
@@ -1460,10 +1440,9 @@ gen8_render_add_request(struct drm_i915_gem_request *req)
return 0;
}
-static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
+static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
u32 seqno)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
return dev_priv->last_seqno < seqno;
}
@@ -1481,7 +1460,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
u32 seqno)
{
struct intel_engine_cs *waiter = waiter_req->engine;
- struct drm_i915_private *dev_priv = waiter->dev->dev_private;
+ struct drm_i915_private *dev_priv = waiter_req->i915;
struct i915_hw_ppgtt *ppgtt;
int ret;
@@ -1535,7 +1514,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
return ret;
/* If seqno wrap happened, omit the wait with no-ops */
- if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
+ if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
intel_ring_emit(waiter, dw1 | wait_mbox);
intel_ring_emit(waiter, seqno);
intel_ring_emit(waiter, 0);
@@ -1616,7 +1595,7 @@ pc_render_add_request(struct drm_i915_gem_request *req)
static void
gen6_seqno_barrier(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
/* Workaround to force correct ordering between irq and seqno writes on
* ivb (and maybe also on snb) by reading from a CS register (like
@@ -1665,8 +1644,7 @@ pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
static bool
gen5_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1683,8 +1661,7 @@ gen5_ring_get_irq(struct intel_engine_cs *engine)
static void
gen5_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1696,8 +1673,7 @@ gen5_ring_put_irq(struct intel_engine_cs *engine)
static bool
i9xx_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (!intel_irqs_enabled(dev_priv))
@@ -1717,8 +1693,7 @@ i9xx_ring_get_irq(struct intel_engine_cs *engine)
static void
i9xx_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1733,8 +1708,7 @@ i9xx_ring_put_irq(struct intel_engine_cs *engine)
static bool
i8xx_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (!intel_irqs_enabled(dev_priv))
@@ -1754,8 +1728,7 @@ i8xx_ring_get_irq(struct intel_engine_cs *engine)
static void
i8xx_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1808,8 +1781,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
static bool
gen6_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1817,10 +1789,10 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (engine->irq_refcount++ == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS)
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
I915_WRITE_IMR(engine,
~(engine->irq_enable_mask |
- GT_PARITY_ERROR(dev)));
+ GT_PARITY_ERROR(dev_priv)));
else
I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
@@ -1833,14 +1805,13 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
static void
gen6_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--engine->irq_refcount == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS)
- I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
+ I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
else
I915_WRITE_IMR(engine, ~0);
gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
@@ -1851,8 +1822,7 @@ gen6_ring_put_irq(struct intel_engine_cs *engine)
static bool
hsw_vebox_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1871,8 +1841,7 @@ hsw_vebox_get_irq(struct intel_engine_cs *engine)
static void
hsw_vebox_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1886,8 +1855,7 @@ hsw_vebox_put_irq(struct intel_engine_cs *engine)
static bool
gen8_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1895,7 +1863,7 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (engine->irq_refcount++ == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS) {
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
I915_WRITE_IMR(engine,
~(engine->irq_enable_mask |
GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
@@ -1912,13 +1880,12 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
static void
gen8_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--engine->irq_refcount == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS) {
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
I915_WRITE_IMR(engine,
~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
} else {
@@ -2040,12 +2007,12 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
static void cleanup_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
if (!dev_priv->status_page_dmah)
return;
- drm_pci_free(engine->dev, dev_priv->status_page_dmah);
+ drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
engine->status_page.page_addr = NULL;
}
@@ -2071,7 +2038,7 @@ static int init_status_page(struct intel_engine_cs *engine)
unsigned flags;
int ret;
- obj = i915_gem_object_create(engine->dev, 4096);
+ obj = i915_gem_object_create(engine->i915->dev, 4096);
if (IS_ERR(obj)) {
DRM_ERROR("Failed to allocate status page\n");
return PTR_ERR(obj);
@@ -2082,7 +2049,7 @@ static int init_status_page(struct intel_engine_cs *engine)
goto err_unref;
flags = 0;
- if (!HAS_LLC(engine->dev))
+ if (!HAS_LLC(engine->i915))
/* On g33, we cannot place HWS above 256MiB, so
* restrict its pinning to the low mappable arena.
* Though this restriction is not documented for
@@ -2116,11 +2083,11 @@ err_unref:
static int init_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
if (!dev_priv->status_page_dmah) {
dev_priv->status_page_dmah =
- drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
+ drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
if (!dev_priv->status_page_dmah)
return -ENOMEM;
}
@@ -2146,10 +2113,9 @@ void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
ringbuf->vma = NULL;
}
-int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
+int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
struct intel_ringbuffer *ringbuf)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_object *obj = ringbuf->obj;
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
unsigned flags = PIN_OFFSET_BIAS | 4096;
@@ -2248,13 +2214,13 @@ intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
* of the buffer.
*/
ring->effective_size = size;
- if (IS_I830(engine->dev) || IS_845G(engine->dev))
+ if (IS_I830(engine->i915) || IS_845G(engine->i915))
ring->effective_size -= 2 * CACHELINE_BYTES;
ring->last_retired_head = -1;
intel_ring_update_space(ring);
- ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
+ ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
if (ret) {
DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
engine->name, ret);
@@ -2277,12 +2243,13 @@ intel_ringbuffer_free(struct intel_ringbuffer *ring)
static int intel_init_ring_buffer(struct drm_device *dev,
struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_ringbuffer *ringbuf;
int ret;
WARN_ON(engine->buffer);
- engine->dev = dev;
+ engine->i915 = dev_priv;
INIT_LIST_HEAD(&engine->active_list);
INIT_LIST_HEAD(&engine->request_list);
INIT_LIST_HEAD(&engine->execlist_queue);
@@ -2300,7 +2267,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
}
engine->buffer = ringbuf;
- if (I915_NEED_GFX_HWS(dev)) {
+ if (I915_NEED_GFX_HWS(dev_priv)) {
ret = init_status_page(engine);
if (ret)
goto error;
@@ -2311,7 +2278,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
goto error;
}
- ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
+ ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
if (ret) {
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
engine->name, ret);
@@ -2337,11 +2304,11 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
if (!intel_engine_initialized(engine))
return;
- dev_priv = to_i915(engine->dev);
+ dev_priv = engine->i915;
if (engine->buffer) {
intel_stop_engine(engine);
- WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
+ WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
intel_unpin_ringbuffer_obj(engine->buffer);
intel_ringbuffer_free(engine->buffer);
@@ -2351,7 +2318,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
if (engine->cleanup)
engine->cleanup(engine);
- if (I915_NEED_GFX_HWS(engine->dev)) {
+ if (I915_NEED_GFX_HWS(dev_priv)) {
cleanup_status_page(engine);
} else {
WARN_ON(engine->id != RCS);
@@ -2360,7 +2327,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
i915_cmd_parser_fini_ring(engine);
i915_gem_batch_pool_fini(&engine->batch_pool);
- engine->dev = NULL;
+ engine->i915 = NULL;
}
int intel_engine_idle(struct intel_engine_cs *engine)
@@ -2526,7 +2493,7 @@ int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
/* Our semaphore implementation is strictly monotonic (i.e. we proceed
* so long as the semaphore value in the register/page is greater
@@ -2562,7 +2529,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
u32 value)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
/* Every tail move must follow the sequence below */
@@ -2604,7 +2571,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
return ret;
cmd = MI_FLUSH_DW;
- if (INTEL_INFO(engine->dev)->gen >= 8)
+ if (INTEL_GEN(req->i915) >= 8)
cmd += 1;
/* We always require a command barrier so that subsequent
@@ -2626,7 +2593,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
intel_ring_emit(engine, cmd);
intel_ring_emit(engine,
I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (INTEL_INFO(engine->dev)->gen >= 8) {
+ if (INTEL_GEN(req->i915) >= 8) {
intel_ring_emit(engine, 0); /* upper addr */
intel_ring_emit(engine, 0); /* value */
} else {
@@ -2717,7 +2684,6 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
uint32_t cmd;
int ret;
@@ -2726,7 +2692,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
return ret;
cmd = MI_FLUSH_DW;
- if (INTEL_INFO(dev)->gen >= 8)
+ if (INTEL_GEN(req->i915) >= 8)
cmd += 1;
/* We always require a command barrier so that subsequent
@@ -2747,7 +2713,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
intel_ring_emit(engine, cmd);
intel_ring_emit(engine,
I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(req->i915) >= 8) {
intel_ring_emit(engine, 0); /* upper addr */
intel_ring_emit(engine, 0); /* value */
} else {
@@ -2773,7 +2739,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->mmio_base = RENDER_RING_BASE;
if (INTEL_INFO(dev)->gen >= 8) {
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
obj = i915_gem_object_create(dev, 4096);
if (IS_ERR(obj)) {
DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
@@ -2798,7 +2764,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
WARN_ON(!dev_priv->semaphore_obj);
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_rcs_signal;
@@ -2816,7 +2782,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
/*
@@ -2940,7 +2906,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
@@ -2951,7 +2917,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->irq_put = gen6_ring_put_irq;
engine->dispatch_execbuffer =
gen6_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
@@ -3014,7 +2980,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
@@ -3047,7 +3013,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
engine->irq_get = gen8_ring_get_irq;
engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
@@ -3057,7 +3023,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
engine->irq_get = gen6_ring_get_irq;
engine->irq_put = gen6_ring_put_irq;
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.signal = gen6_signal;
engine->semaphore.sync_to = gen6_ring_sync;
/*
@@ -3108,7 +3074,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
engine->irq_get = gen8_ring_get_irq;
engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
@@ -3118,7 +3084,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
engine->irq_get = hsw_vebox_get_irq;
engine->irq_put = hsw_vebox_put_irq;
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 723ff6160fbb..929e7b4af2a4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -141,7 +141,8 @@ struct i915_ctx_workarounds {
struct drm_i915_gem_object *obj;
};
-struct intel_engine_cs {
+struct intel_engine_cs {
+ struct drm_i915_private *i915;
const char *name;
enum intel_engine_id {
RCS = 0,
@@ -156,7 +157,6 @@ struct intel_engine_cs {
unsigned int hw_id;
unsigned int guc_id; /* XXX same as hw_id? */
u32 mmio_base;
- struct drm_device *dev;
struct intel_ringbuffer *buffer;
struct list_head buffers;
@@ -350,7 +350,7 @@ struct intel_engine_cs {
static inline bool
intel_engine_initialized(struct intel_engine_cs *engine)
{
- return engine->dev != NULL;
+ return engine->i915 != NULL;
}
static inline unsigned
@@ -425,7 +425,7 @@ intel_write_status_page(struct intel_engine_cs *engine,
struct intel_ringbuffer *
intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
-int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
+int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
struct intel_ringbuffer *ringbuf);
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
void intel_ringbuffer_free(struct intel_ringbuffer *ring);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 4f1dfe616856..4ea2bf2c2a4a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1381,7 +1381,7 @@ void intel_uncore_init(struct drm_device *dev)
break;
}
- if (intel_vgpu_active(dev)) {
+ if (intel_vgpu_active(dev_priv)) {
ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
ASSIGN_READ_MMIO_VFUNCS(vgpu);
}
@@ -1663,8 +1663,8 @@ static int wait_for_register_fw(struct drm_i915_private *dev_priv,
static int gen8_request_engine_reset(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
@@ -1682,7 +1682,7 @@ static int gen8_request_engine_reset(struct intel_engine_cs *engine)
static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
@@ -1802,10 +1802,10 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
{
enum forcewake_domains fw_domains;
- if (intel_vgpu_active(dev_priv->dev))
+ if (intel_vgpu_active(dev_priv))
return 0;
- switch (INTEL_INFO(dev_priv)->gen) {
+ switch (INTEL_GEN(dev_priv)) {
case 9:
fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg));
break;
@@ -1842,10 +1842,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
{
enum forcewake_domains fw_domains;
- if (intel_vgpu_active(dev_priv->dev))
+ if (intel_vgpu_active(dev_priv))
return 0;
- switch (INTEL_INFO(dev_priv)->gen) {
+ switch (INTEL_GEN(dev_priv)) {
case 9:
fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
break;
--
2.8.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 04/19] drm/i915/shrinker: Flush active on objects before counting
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
2016-05-05 9:15 ` [PATCH 02/19] drm/i915/execlists: Refactor common engine setup Chris Wilson
2016-05-05 9:15 ` [PATCH 03/19] drm/i915: Store a i915 backpointer from engine, and use it Chris Wilson
@ 2016-05-05 9:15 ` Chris Wilson
2016-05-05 9:15 ` [PATCH 05/19] drm/i915: Delay queuing hangcheck to wait-request Chris Wilson
` (14 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx
As we inspect obj->active to decide how many objects we can shrink (we
only shrink idle objects), it helps to flush the active lists first
in order to have a more accurate count of available objects.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 538c30499848..d893014d28fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -265,6 +265,8 @@ i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
if (!i915_gem_shrinker_lock(dev, &unlock))
return 0;
+ i915_gem_retire_requests(dev_priv);
+
count = 0;
list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
if (can_release_pages(obj))
--
2.8.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 05/19] drm/i915: Delay queuing hangcheck to wait-request
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (2 preceding siblings ...)
2016-05-05 9:15 ` [PATCH 04/19] drm/i915/shrinker: Flush active on objects before counting Chris Wilson
@ 2016-05-05 9:15 ` Chris Wilson
2016-05-05 9:15 ` [PATCH 06/19] drm/i915: Remove the dedicated hangcheck workqueue Chris Wilson
` (13 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx
We can forgo queuing the hangcheck from the start of every request to
until we wait upon a request. This reduces the overhead of every
request, but may increase the latency of detecting a hang. Howeever, if
nothing every waits upon a hang, did it ever hang? It also improves the
robustness of the wait-request by ensuring that the hangchecker is
indeed running before we sleep indefinitely (and thereby ensuring that
we never actually sleep forever waiting for a dead GPU).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 9 +++++----
drivers/gpu/drm/i915/i915_irq.c | 10 ++++------
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c99d1b2c65d4..4de6eafaec28 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1310,6 +1310,9 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
break;
}
+ /* Ensure that even if the GPU hangs, we get woken up. */
+ i915_queue_hangcheck(dev_priv);
+
timer.function = NULL;
if (timeout || missed_irq(dev_priv, engine)) {
unsigned long expire;
@@ -2650,8 +2653,6 @@ void __i915_add_request(struct drm_i915_gem_request *request,
/* Not allowed to fail! */
WARN(ret, "emit|add_request failed: %d!\n", ret);
- i915_queue_hangcheck(engine->i915);
-
queue_delayed_work(dev_priv->wq,
&dev_priv->mm.retire_work,
round_jiffies_up_relative(HZ));
@@ -2995,8 +2996,8 @@ i915_gem_retire_requests(struct drm_i915_private *dev_priv)
if (idle)
mod_delayed_work(dev_priv->wq,
- &dev_priv->mm.idle_work,
- msecs_to_jiffies(100));
+ &dev_priv->mm.idle_work,
+ msecs_to_jiffies(100));
return idle;
}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8864ee19154f..1544a5677ac8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3167,10 +3167,10 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
for_each_engine_id(engine, dev_priv, id) {
+ bool busy = waitqueue_active(&engine->irq_queue);
u64 acthd;
u32 seqno;
unsigned user_interrupts;
- bool busy = true;
semaphore_clear_deadlocks(dev_priv);
@@ -3193,12 +3193,11 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
if (engine->hangcheck.seqno == seqno) {
if (ring_idle(engine, seqno)) {
engine->hangcheck.action = HANGCHECK_IDLE;
- if (waitqueue_active(&engine->irq_queue)) {
+ if (busy) {
/* Safeguard against driver failure */
user_interrupts = kick_waiters(engine);
engine->hangcheck.score += BUSY;
- } else
- busy = false;
+ }
} else {
/* We always increment the hangcheck score
* if the ring is busy and still processing
@@ -3272,9 +3271,8 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
goto out;
}
+ /* Reset timer in case GPU hangs without another request being added */
if (busy_count)
- /* Reset timer case chip hangs without another request
- * being added */
i915_queue_hangcheck(dev_priv);
out:
--
2.8.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 06/19] drm/i915: Remove the dedicated hangcheck workqueue
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (3 preceding siblings ...)
2016-05-05 9:15 ` [PATCH 05/19] drm/i915: Delay queuing hangcheck to wait-request Chris Wilson
@ 2016-05-05 9:15 ` Chris Wilson
2016-05-05 9:15 ` [PATCH 07/19] drm/i915: Make queueing the hangcheck work inline Chris Wilson
` (12 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx
The queue only ever contains at most one item and has no special flags.
It is just a very simple wrapper around the system-wq - a complication
with no benefits.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_dma.c | 8 --------
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
3 files changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 46ac1da64a09..26dc679b427f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1023,15 +1023,8 @@ static int i915_workqueues_init(struct drm_i915_private *dev_priv)
if (dev_priv->hotplug.dp_wq == NULL)
goto out_free_wq;
- dev_priv->gpu_error.hangcheck_wq =
- alloc_ordered_workqueue("i915-hangcheck", 0);
- if (dev_priv->gpu_error.hangcheck_wq == NULL)
- goto out_free_dp_wq;
-
return 0;
-out_free_dp_wq:
- destroy_workqueue(dev_priv->hotplug.dp_wq);
out_free_wq:
destroy_workqueue(dev_priv->wq);
out_err:
@@ -1042,7 +1035,6 @@ out_err:
static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
{
- destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
destroy_workqueue(dev_priv->hotplug.dp_wq);
destroy_workqueue(dev_priv->wq);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c162b825273f..83c0f3594c79 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1353,7 +1353,6 @@ struct i915_gpu_error {
/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
- struct workqueue_struct *hangcheck_wq;
struct delayed_work hangcheck_work;
/* For reset and error_state handling. */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1544a5677ac8..ab6fb1483309 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3281,7 +3281,7 @@ out:
void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
- struct i915_gpu_error *e = &dev_priv->gpu_error;
+ unsigned long delay;
if (!i915.enable_hangcheck)
return;
@@ -3291,8 +3291,8 @@ void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
* we will ignore a hung ring if a second ring is kept busy.
*/
- queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
- round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
+ delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
+ schedule_delayed_work(&dev_priv->gpu_error.hangcheck_work, delay);
}
static void ibx_irq_reset(struct drm_device *dev)
--
2.8.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 07/19] drm/i915: Make queueing the hangcheck work inline
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (4 preceding siblings ...)
2016-05-05 9:15 ` [PATCH 06/19] drm/i915: Remove the dedicated hangcheck workqueue Chris Wilson
@ 2016-05-05 9:15 ` Chris Wilson
2016-05-05 9:15 ` [PATCH 08/19] drm/i915: Slaughter the thundering i915_wait_request herd Chris Wilson
` (11 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx
Since the function is a small wrapper around schedule_delayed_work(),
move it inline to remove the function call overhead for the principle
caller.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 17 ++++++++++++++++-
drivers/gpu/drm/i915/i915_irq.c | 16 ----------------
2 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 83c0f3594c79..c2f66ceb84e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2795,7 +2795,22 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
/* i915_irq.c */
-void i915_queue_hangcheck(struct drm_i915_private *dev_priv);
+static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
+{
+ unsigned long delay;
+
+ if (unlikely(!i915.enable_hangcheck))
+ return;
+
+ /* Don't continually defer the hangcheck so that it is always run at
+ * least once after work has been scheduled on any ring. Otherwise,
+ * we will ignore a hung ring if a second ring is kept busy.
+ */
+
+ delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
+ schedule_delayed_work(&dev_priv->gpu_error.hangcheck_work, delay);
+}
+
__printf(3, 4)
void i915_handle_error(struct drm_i915_private *dev_priv,
u32 engine_mask,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ab6fb1483309..ce5915d43cdc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3279,22 +3279,6 @@ out:
ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
}
-void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
-{
- unsigned long delay;
-
- if (!i915.enable_hangcheck)
- return;
-
- /* Don't continually defer the hangcheck so that it is always run at
- * least once after work has been scheduled on any ring. Otherwise,
- * we will ignore a hung ring if a second ring is kept busy.
- */
-
- delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
- schedule_delayed_work(&dev_priv->gpu_error.hangcheck_work, delay);
-}
-
static void ibx_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
--
2.8.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 08/19] drm/i915: Slaughter the thundering i915_wait_request herd
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (5 preceding siblings ...)
2016-05-05 9:15 ` [PATCH 07/19] drm/i915: Make queueing the hangcheck work inline Chris Wilson
@ 2016-05-05 9:15 ` Chris Wilson
2016-05-05 9:15 ` [PATCH 09/19] drm/i915: Remove the lazy_coherency parameter from request-completed? Chris Wilson
` (10 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Goel, Akash
One particularly stressful scenario consists of many independent tasks
all competing for GPU time and waiting upon the results (e.g. realtime
transcoding of many, many streams). One bottleneck in particular is that
each client waits on its own results, but every client is woken up after
every batchbuffer - hence the thunder of hooves as then every client must
do its heavyweight dance to read a coherent seqno to see if it is the
lucky one.
Ideally, we only want one client to wake up after the interrupt and
check its request for completion. Since the requests must retire in
order, we can select the first client on the oldest request to be woken.
Once that client has completed his wait, we can then wake up the
next client and so on. However, all clients then incur latency as every
process in the chain may be delayed for scheduling - this may also then
cause some priority inversion. To reduce the latency, when a client
is added or removed from the list, we scan the tree for completed
seqno and wake up all the completed waiters in parallel.
Using igt/benchmarks/gem_latency, we can demonstrate this effect. The
benchmark measures the number of GPU cycles between completion of a
batch and the client waking up from a call to wait-ioctl. With many
concurrent waiters, with each on a different request, we observe that
the wakeup latency before the patch scales nearly linearly with the
number of waiters (before external factors kick in making the scaling much
worse). After applying the patch, we can see that only the single waiter
for the request is being woken up, providing a constant wakeup latency
for every operation. However, the situation is not quite as rosy for
many waiters on the same request, though to the best of my knowledge this
is much less likely in practice. Here, we can observe that the
concurrent waiters incur extra latency from being woken up by the
solitary bottom-half, rather than directly by the interrupt. This
appears to be scheduler induced (having discounted adverse effects from
having a rbtree walk/erase in the wakeup path), each additional
wake_up_process() costs approximately 1us on big core. Another effect of
performing the secondary wakeups from the first bottom-half is the
incurred delay this imposes on high priority threads - rather than
immediately returning to userspace and leaving the interrupt handler to
wake the others.
To offset the delay incurred with additional waiters on a request, we
could use a hybrid scheme that did a quick read in the interrupt handler
and dequeued all the completed waiters (incurring the overhead in the
interrupt handler, not the best plan either as we then incur GPU
submission latency) but we would still have to wake up the bottom-half
every time to do the heavyweight slow read. Or we could only kick the
waiters on the seqno with the same priority as the current task (i.e. in
the realtime waiter scenario, only it is woken up immediately by the
interrupt and simply queues the next waiter before returning to userspace,
minimising its delay at the expense of the chain, and also reducing
contention on its scheduler runqueue). This is effective at avoid long
pauses in the interrupt handler and at avoiding the extra latency in
realtime/high-priority waiters.
v2: Convert from a kworker per engine into a dedicated kthread for the
bottom-half.
v3: Rename request members and tweak comments.
v4: Use a per-engine spinlock in the breadcrumbs bottom-half.
v5: Fix race in locklessly checking waiter status and kicking the task on
adding a new waiter.
v6: Fix deciding when to force the timer to hide missing interrupts.
v7: Move the bottom-half from the kthread to the first client process.
v8: Reword a few comments
v9: Break the busy loop when the interrupt is unmasked or has fired.
v10: Comments, unnecessary churn, better debugging from Tvrtko
v11: Wake all completed waiters on removing the current bottom-half to
reduce the latency of waking up a herd of clients all waiting on the
same request.
v12: Rearrange missed-interrupt fault injection so that it works with
igt/drv_missed_irq_hang
v13: Rename intel_breadcrumb and friends to intel_wait in preparation
for signal handling.
v14: RCU commentary, assert_spin_locked
v15: Hide BUG_ON behind the compiler; report on gem_latency findings.
v16: Sort seqno-groups by priority so that first-waiter has the highest
task priority (and so avoid priority inversion).
Testcase: igt/gem_concurrent_blit
Testcase: igt/benchmarks/gem_latency
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Rogozhkin, Dmitry V" <dmitry.v.rogozhkin@intel.com>
Cc: "Gong, Zhipeng" <zhipeng.gong@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: "Goel, Akash" <akash.goel@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 15 +-
drivers/gpu/drm/i915/i915_drv.h | 32 ++-
drivers/gpu/drm/i915/i915_gem.c | 130 ++++--------
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 27 +--
drivers/gpu/drm/i915/intel_breadcrumbs.c | 333 +++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 67 ++++++-
10 files changed, 504 insertions(+), 110 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_breadcrumbs.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 63c4d2b7c5b0..3a00f5a05604 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -37,6 +37,7 @@ i915-y += i915_cmd_parser.o \
i915_gem_userptr.o \
i915_gpu_error.o \
i915_trace_points.o \
+ intel_breadcrumbs.o \
intel_lrc.o \
intel_mocs.o \
intel_ringbuffer.o \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6698957ede3f..bb1f3e2e85e5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -761,10 +761,21 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
static void i915_ring_seqno_info(struct seq_file *m,
struct intel_engine_cs *engine)
{
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+ struct rb_node *rb;
+
seq_printf(m, "Current sequence (%s): %x\n",
engine->name, engine->get_seqno(engine));
seq_printf(m, "Current user interrupts (%s): %x\n",
engine->name, READ_ONCE(engine->user_interrupts));
+
+ spin_lock(&b->lock);
+ for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb)) {
+ struct intel_wait *w = container_of(rb, typeof(*w), node);
+ seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
+ engine->name, w->task->comm, w->task->pid, w->seqno);
+ }
+ spin_unlock(&b->lock);
}
static int i915_gem_seqno_info(struct seq_file *m, void *data)
@@ -1400,6 +1411,8 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
engine->hangcheck.seqno,
seqno[id],
engine->last_submitted_seqno);
+ seq_printf(m, "\twaiters? %d\n",
+ intel_engine_has_waiter(engine));
seq_printf(m, "\tuser interrupts = %x [current %x]\n",
engine->hangcheck.user_interrupts,
READ_ONCE(engine->user_interrupts));
@@ -2384,7 +2397,7 @@ static int count_irq_waiters(struct drm_i915_private *i915)
int count = 0;
for_each_engine(engine, i915)
- count += engine->irq_refcount;
+ count += intel_engine_has_waiter(engine);
return count;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c2f66ceb84e9..f4a9a4568a21 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1402,7 +1402,7 @@ struct i915_gpu_error {
#define I915_STOP_RING_ALLOW_WARN (1 << 30)
/* For missed irq/seqno simulation. */
- unsigned int test_irq_rings;
+ unsigned long test_irq_rings;
};
enum modeset_restore {
@@ -2902,7 +2902,6 @@ ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
ibx_display_interrupt_update(dev_priv, bits, 0);
}
-
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
@@ -3772,4 +3771,33 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
i915_gem_request_assign(&engine->trace_irq_req, req);
}
+static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
+{
+ /* Ensure our read of the seqno is coherent so that we
+ * do not "miss an interrupt" (i.e. if this is the last
+ * request and the seqno write from the GPU is not visible
+ * by the time the interrupt fires, we will see that the
+ * request is incomplete and go back to sleep awaiting
+ * another interrupt that will never come.)
+ *
+ * Strictly, we only need to do this once after an interrupt,
+ * but it is easier and safer to do it every time the waiter
+ * is woken.
+ */
+ if (i915_gem_request_completed(req, false))
+ return true;
+
+ /* We need to check whether any gpu reset happened in between
+ * the request being submitted and now. If a reset has occurred,
+ * the request is effectively complete (we either are in the
+ * process of or have discarded the rendering and completely
+ * reset the GPU. The results of the request are lost and we
+ * are free to continue on with the original operation.
+ */
+ if (req->reset_counter != i915_reset_counter(&req->i915->gpu_error))
+ return true;
+
+ return false;
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4de6eafaec28..23d89859cbb9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1123,17 +1123,6 @@ i915_gem_check_wedge(unsigned reset_counter, bool interruptible)
return 0;
}
-static void fake_irq(unsigned long data)
-{
- wake_up_process((struct task_struct *)data);
-}
-
-static bool missed_irq(struct drm_i915_private *dev_priv,
- struct intel_engine_cs *engine)
-{
- return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings);
-}
-
static unsigned long local_clock_us(unsigned *cpu)
{
unsigned long t;
@@ -1166,7 +1155,7 @@ static bool busywait_stop(unsigned long timeout, unsigned cpu)
return this_cpu != cpu;
}
-static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
+static bool __i915_spin_request(struct drm_i915_gem_request *req, int state)
{
unsigned long timeout;
unsigned cpu;
@@ -1181,17 +1170,14 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
* takes to sleep on a request, on the order of a microsecond.
*/
- if (req->engine->irq_refcount)
- return -EBUSY;
-
/* Only spin if we know the GPU is processing this request */
if (!i915_gem_request_started(req, true))
- return -EAGAIN;
+ return false;
timeout = local_clock_us(&cpu) + 5;
- while (!need_resched()) {
+ do {
if (i915_gem_request_completed(req, true))
- return 0;
+ return true;
if (signal_pending_state(state, current))
break;
@@ -1200,12 +1186,9 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
break;
cpu_relax_lowlatency();
- }
-
- if (i915_gem_request_completed(req, false))
- return 0;
+ } while (!need_resched());
- return -EAGAIN;
+ return false;
}
/**
@@ -1229,17 +1212,13 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
s64 *timeout,
struct intel_rps_client *rps)
{
- struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
- struct drm_i915_private *dev_priv = req->i915;
- const bool irq_test_in_progress =
- ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
- DEFINE_WAIT(wait);
- unsigned long timeout_expire;
+ struct intel_wait wait;
+ unsigned long timeout_remain;
s64 before = 0; /* Only to silence a compiler warning. */
- int ret;
+ int ret = 0;
- WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
+ might_sleep();
if (list_empty(&req->list))
return 0;
@@ -1247,7 +1226,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
if (i915_gem_request_completed(req, true))
return 0;
- timeout_expire = 0;
+ timeout_remain = MAX_SCHEDULE_TIMEOUT;
if (timeout) {
if (WARN_ON(*timeout < 0))
return -EINVAL;
@@ -1255,7 +1234,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
if (*timeout == 0)
return -ETIME;
- timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);
+ timeout_remain = nsecs_to_jiffies_timeout(*timeout);
/*
* Record current time in case interrupted by signal, or wedged.
@@ -1263,78 +1242,57 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
before = ktime_get_raw_ns();
}
- if (INTEL_INFO(dev_priv)->gen >= 6)
- gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
-
trace_i915_gem_request_wait_begin(req);
- /* Optimistic spin for the next jiffie before touching IRQs */
- ret = __i915_spin_request(req, state);
- if (ret == 0)
- goto out;
+ if (INTEL_INFO(req->i915)->gen >= 6)
+ gen6_rps_boost(req->i915, rps, req->emitted_jiffies);
- if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) {
- ret = -ENODEV;
- goto out;
- }
-
- for (;;) {
- struct timer_list timer;
+ /* Optimistic spin for the next ~jiffie before touching IRQs */
+ if (__i915_spin_request(req, state))
+ goto complete;
- prepare_to_wait(&engine->irq_queue, &wait, state);
-
- /* We need to check whether any gpu reset happened in between
- * the request being submitted and now. If a reset has occurred,
- * the request is effectively complete (we either are in the
- * process of or have discarded the rendering and completely
- * reset the GPU. The results of the request are lost and we
- * are free to continue on with the original operation.
+ intel_wait_init(&wait, req->seqno);
+ set_current_state(state);
+ if (intel_engine_add_wait(req->engine, &wait))
+ /* In order to check that we haven't missed the interrupt
+ * as we enabled it, we need to kick ourselves to do a
+ * coherent check on the seqno before we sleep.
*/
- if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
- ret = 0;
- break;
- }
-
- if (i915_gem_request_completed(req, false)) {
- ret = 0;
- break;
- }
+ goto wakeup;
+ for (;;) {
if (signal_pending_state(state, current)) {
ret = -ERESTARTSYS;
break;
}
- if (timeout && time_after_eq(jiffies, timeout_expire)) {
+ /* Ensure that even if the GPU hangs, we get woken up. */
+ i915_queue_hangcheck(req->i915);
+
+ timeout_remain = io_schedule_timeout(timeout_remain);
+ if (timeout_remain == 0) {
ret = -ETIME;
break;
}
- /* Ensure that even if the GPU hangs, we get woken up. */
- i915_queue_hangcheck(dev_priv);
-
- timer.function = NULL;
- if (timeout || missed_irq(dev_priv, engine)) {
- unsigned long expire;
-
- setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
- expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire;
- mod_timer(&timer, expire);
- }
+ if (intel_wait_complete(&wait))
+ break;
- io_schedule();
+wakeup:
+ set_current_state(state);
- if (timer.function) {
- del_singleshot_timer_sync(&timer);
- destroy_timer_on_stack(&timer);
- }
+ /* Carefully check if the request is complete, giving time
+ * for the seqno to be visible following the interrupt.
+ * We also have to check in case we are kicked by the GPU
+ * reset in order to drop the struct_mutex.
+ */
+ if (__i915_request_irq_complete(req))
+ break;
}
- if (!irq_test_in_progress)
- engine->irq_put(engine);
- finish_wait(&engine->irq_queue, &wait);
-
-out:
+ intel_engine_remove_wait(req->engine, &wait);
+ __set_current_state(TASK_RUNNING);
+complete:
trace_i915_gem_request_wait_end(req);
if (timeout) {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 22d926839b68..34e5ba3f7c7a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -926,7 +926,7 @@ static void i915_record_ring_state(struct drm_i915_private *dev_priv,
ering->instdone = I915_READ(GEN2_INSTDONE);
}
- ering->waiting = waitqueue_active(&engine->irq_queue);
+ ering->waiting = intel_engine_has_waiter(engine);
ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
ering->acthd = intel_ring_get_active_head(engine);
ering->seqno = engine->get_seqno(engine);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ce5915d43cdc..70bfa5af0ad1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -996,13 +996,10 @@ static void ironlake_rps_change_irq_handler(struct drm_device *dev)
static void notify_ring(struct intel_engine_cs *engine)
{
- if (!intel_engine_initialized(engine))
- return;
-
- trace_i915_gem_request_notify(engine);
- engine->user_interrupts++;
-
- wake_up_all(&engine->irq_queue);
+ if (intel_engine_wakeup(engine)) {
+ trace_i915_gem_request_notify(engine);
+ engine->user_interrupts++;
+ }
}
static void vlv_c0_read(struct drm_i915_private *dev_priv,
@@ -1083,7 +1080,7 @@ static bool any_waiters(struct drm_i915_private *dev_priv)
struct intel_engine_cs *engine;
for_each_engine(engine, dev_priv)
- if (engine->irq_refcount)
+ if (intel_engine_has_waiter(engine))
return true;
return false;
@@ -2524,8 +2521,6 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
bool reset_completed)
{
- struct intel_engine_cs *engine;
-
/*
* Notify all waiters for GPU completion events that reset state has
* been changed, and that they need to restart their wait after
@@ -2533,9 +2528,8 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
* a gpu reset pending so that i915_error_work_func can acquire them).
*/
- /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
- for_each_engine(engine, dev_priv)
- wake_up_all(&engine->irq_queue);
+ /* Wake up i915_wait_request, potentially holding dev->struct_mutex. */
+ intel_kick_waiters(dev_priv);
/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
wake_up_all(&dev_priv->pending_flip_queue);
@@ -3117,13 +3111,14 @@ static unsigned kick_waiters(struct intel_engine_cs *engine)
if (engine->hangcheck.user_interrupts == user_interrupts &&
!test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
- if (!(i915->gpu_error.test_irq_rings & intel_engine_flag(engine)))
+ if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
engine->name);
else
DRM_INFO("Fake missed irq on %s\n",
engine->name);
- wake_up_all(&engine->irq_queue);
+
+ intel_engine_enable_fake_irq(engine);
}
return user_interrupts;
@@ -3167,7 +3162,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
for_each_engine_id(engine, dev_priv, id) {
- bool busy = waitqueue_active(&engine->irq_queue);
+ bool busy = intel_engine_has_waiter(engine);
u64 acthd;
u32 seqno;
unsigned user_interrupts;
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
new file mode 100644
index 000000000000..c82ecbf7470a
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+
+static void intel_breadcrumbs_fake_irq(unsigned long data)
+{
+ struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
+
+ /*
+ * The timer persists in case we cannot enable interrupts,
+ * or if we have previously seen seqno/interrupt incoherency
+ * ("missed interrupt" syndrome). Here the worker will wake up
+ * every jiffie in order to kick the oldest waiter to do the
+ * coherent seqno check.
+ */
+ rcu_read_lock();
+ if (intel_engine_wakeup(engine))
+ mod_timer(&engine->breadcrumbs.fake_irq, jiffies + 1);
+ rcu_read_unlock();
+}
+
+static void irq_enable(struct intel_engine_cs *engine)
+{
+ WARN_ON(!engine->irq_get(engine));
+}
+
+static void irq_disable(struct intel_engine_cs *engine)
+{
+ engine->irq_put(engine);
+}
+
+static bool __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b)
+{
+ struct intel_engine_cs *engine =
+ container_of(b, struct intel_engine_cs, breadcrumbs);
+ struct drm_i915_private *i915 = engine->i915;
+ bool irq_posted = false;
+
+ assert_spin_locked(&b->lock);
+ if (b->rpm_wakelock)
+ return false;
+
+ /* Since we are waiting on a request, the GPU should be busy
+ * and should have its own rpm reference. For completeness,
+ * record an rpm reference for ourselves to cover the
+ * interrupt we unmask.
+ */
+ intel_runtime_pm_get_noresume(i915);
+ b->rpm_wakelock = true;
+
+ /* No interrupts? Kick the waiter every jiffie! */
+ if (intel_irqs_enabled(i915)) {
+ if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings)) {
+ irq_enable(engine);
+ irq_posted = true;
+ }
+ b->irq_enabled = true;
+ }
+
+ if (!b->irq_enabled ||
+ test_bit(engine->id, &i915->gpu_error.missed_irq_rings))
+ mod_timer(&b->fake_irq, jiffies + 1);
+
+ return irq_posted;
+}
+
+static void __intel_breadcrumbs_disable_irq(struct intel_breadcrumbs *b)
+{
+ struct intel_engine_cs *engine =
+ container_of(b, struct intel_engine_cs, breadcrumbs);
+
+ assert_spin_locked(&b->lock);
+ if (!b->rpm_wakelock)
+ return;
+
+ if (b->irq_enabled) {
+ irq_disable(engine);
+ b->irq_enabled = false;
+ }
+
+ intel_runtime_pm_put(engine->i915);
+ b->rpm_wakelock = false;
+}
+
+static inline struct intel_wait *to_wait(struct rb_node *node)
+{
+ return container_of(node, struct intel_wait, node);
+}
+
+static inline void __intel_breadcrumbs_finish(struct intel_breadcrumbs *b,
+ struct intel_wait *wait)
+{
+ assert_spin_locked(&b->lock);
+
+ /* This request is completed, so remove it from the tree, mark it as
+ * complete, and *then* wake up the associated task.
+ */
+ rb_erase(&wait->node, &b->waiters);
+ RB_CLEAR_NODE(&wait->node);
+
+ wake_up_process(wait->task); /* implicit smp_wmb() */
+}
+
+bool intel_engine_add_wait(struct intel_engine_cs *engine,
+ struct intel_wait *wait)
+{
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+ struct rb_node **p, *parent, *completed;
+ bool first;
+ u32 seqno;
+
+ spin_lock(&b->lock);
+
+ /* Insert the request into the retirement ordered list
+ * of waiters by walking the rbtree. If we are the oldest
+ * seqno in the tree (the first to be retired), then
+ * set ourselves as the bottom-half.
+ *
+ * As we descend the tree, prune completed branches since we hold the
+ * spinlock we know that the first_waiter must be delayed and can
+ * reduce some of the sequential wake up latency if we take action
+ * ourselves and wake up the completed tasks in parallel. Also, by
+ * removing stale elements in the tree, we may be able to reduce the
+ * ping-pong between the old bottom-half and ourselves as first-waiter.
+ */
+ first = true;
+ parent = NULL;
+ completed = NULL;
+ seqno = engine->get_seqno(engine);
+
+ p = &b->waiters.rb_node;
+ while (*p) {
+ parent = *p;
+ if (wait->seqno == to_wait(parent)->seqno) {
+ /* We have multiple waiters on the same seqno, select
+ * the highest priority task (that with the smallest
+ * task->prio) to serve as the bottom-half for this
+ * group.
+ */
+ if (wait->task->prio > to_wait(parent)->task->prio) {
+ p = &parent->rb_right;
+ first = false;
+ } else
+ p = &parent->rb_left;
+ } else if (i915_seqno_passed(wait->seqno,
+ to_wait(parent)->seqno)) {
+ p = &parent->rb_right;
+ if (i915_seqno_passed(seqno, to_wait(parent)->seqno))
+ completed = parent;
+ else
+ first = false;
+ } else
+ p = &parent->rb_left;
+ }
+ rb_link_node(&wait->node, parent, p);
+ rb_insert_color(&wait->node, &b->waiters);
+
+ if (completed != NULL) {
+ struct rb_node *next = rb_next(completed);
+
+ if (next && next != &wait->node) {
+ GEM_BUG_ON(first);
+ smp_store_mb(b->first_waiter, to_wait(next)->task);
+ /* As there is a delay between reading the current
+ * seqno, processing the completed tasks and selecting
+ * the next waiter, we may have missed the interrupt
+ * and so need for the next bottom-half to wakeup.
+ *
+ * Also as we enable the IRQ, we may miss the
+ * interrupt for that seqno, so we have to wake up
+ * the next bottom-half in order to do a coherent check
+ * in case the seqno passed.
+ */
+ __intel_breadcrumbs_enable_irq(b);
+ wake_up_process(to_wait(next)->task);
+ }
+
+ do {
+ struct intel_wait *crumb = to_wait(completed);
+ completed = rb_prev(completed);
+ __intel_breadcrumbs_finish(b, crumb);
+ } while (completed != NULL);
+ }
+
+ if (first) {
+ smp_store_mb(b->first_waiter, wait->task);
+ first =__intel_breadcrumbs_enable_irq(b);
+ }
+ GEM_BUG_ON(b->first_waiter == NULL);
+
+ spin_unlock(&b->lock);
+
+ return first;
+}
+
+void intel_engine_enable_fake_irq(struct intel_engine_cs *engine)
+{
+ mod_timer(&engine->breadcrumbs.fake_irq, jiffies + 1);
+}
+
+static inline bool chain_wakeup(struct rb_node *rb, int priority)
+{
+ return rb && to_wait(rb)->task->prio <= priority;
+}
+
+void intel_engine_remove_wait(struct intel_engine_cs *engine,
+ struct intel_wait *wait)
+{
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+
+ /* Quick check to see if this waiter was already decoupled from
+ * the tree by the bottom-half to avoid contention on the spinlock
+ * by the herd.
+ */
+ if (RB_EMPTY_NODE(&wait->node))
+ return;
+
+ spin_lock(&b->lock);
+
+ if (b->first_waiter == wait->task) {
+ struct rb_node *next;
+ struct task_struct *task;
+ const int priority = wait->task->prio;
+
+ /* We are the current bottom-half. Find the next candidate,
+ * the first waiter in the queue on the remaining oldest
+ * request. As multiple seqnos may complete in the time it
+ * takes us to wake up and find the next waiter, we have to
+ * wake up that waiter for it to perform its own coherent
+ * completion check.
+ */
+ next = rb_next(&wait->node);
+ if (chain_wakeup(next, priority)) {
+ /* If the next waiter is already complete,
+ * wake it up and continue onto the next waiter. So
+ * if have a small herd, they will wake up in parallel
+ * rather than sequentially, which should reduce
+ * the overall latency in waking all the completed
+ * clients.
+ *
+ * However, waking up a chain adds extra latency to
+ * the first_waiter. This is undesirable if that
+ * waiter is a high priority task.
+ */
+ u32 seqno = engine->get_seqno(engine);
+ while (i915_seqno_passed(seqno, to_wait(next)->seqno)) {
+ struct rb_node *n = rb_next(next);
+ __intel_breadcrumbs_finish(b, to_wait(next));
+ next = n;
+ if (!chain_wakeup(next, priority))
+ break;
+ }
+ }
+ task = next ? to_wait(next)->task : NULL;
+
+ smp_store_mb(b->first_waiter, task);
+ if (task) {
+ /* In our haste, we may have completed the first waiter
+ * before we enabled the interrupt. Do so now as we
+ * have a second waiter for a future seqno. Afterwards,
+ * we have to wake up that waiter in case we missed
+ * the interrupt, or if we have to handle an
+ * exception rather than a seqno completion.
+ */
+ if (to_wait(next)->seqno != wait->seqno)
+ __intel_breadcrumbs_enable_irq(b);
+ wake_up_process(task);
+ } else
+ __intel_breadcrumbs_disable_irq(b);
+ }
+
+ if (!RB_EMPTY_NODE(&wait->node))
+ rb_erase(&wait->node, &b->waiters);
+ spin_unlock(&b->lock);
+}
+
+void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine)
+{
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+
+ spin_lock_init(&b->lock);
+ setup_timer(&b->fake_irq,
+ intel_breadcrumbs_fake_irq,
+ (unsigned long)engine);
+}
+
+void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
+{
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+
+ del_timer_sync(&b->fake_irq);
+}
+
+unsigned intel_kick_waiters(struct drm_i915_private *i915)
+{
+ struct intel_engine_cs *engine;
+ unsigned mask = 0;
+
+ /* To avoid the task_struct disappearing beneath us as we wake up
+ * the process, we must first inspect the task_struct->state under the
+ * RCU lock, i.e. as we call wake_up_process() we must be holding the
+ * rcu_read_lock().
+ */
+ rcu_read_lock();
+ for_each_engine(engine, i915)
+ if (unlikely(intel_engine_wakeup(engine)))
+ mask |= intel_engine_flag(engine);
+ rcu_read_unlock();
+
+ return mask;
+}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e76280d5cdff..a29ccbd2ca91 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1894,6 +1894,8 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
i915_cmd_parser_fini_ring(engine);
i915_gem_batch_pool_fini(&engine->batch_pool);
+ intel_engine_fini_breadcrumbs(engine);
+
if (engine->status_page.obj) {
i915_gem_object_unpin_map(engine->status_page.obj);
engine->status_page.obj = NULL;
@@ -1931,7 +1933,7 @@ logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
{
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
- init_waitqueue_head(&engine->irq_queue);
+ intel_engine_init_breadcrumbs(engine);
}
static int
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e8a28b0ccab9..5fa582e2b93c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2258,7 +2258,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
memset(engine->semaphore.sync_seqno, 0,
sizeof(engine->semaphore.sync_seqno));
- init_waitqueue_head(&engine->irq_queue);
+ intel_engine_init_breadcrumbs(engine);
ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
if (IS_ERR(ringbuf)) {
@@ -2327,6 +2327,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
i915_cmd_parser_fini_ring(engine);
i915_gem_batch_pool_fini(&engine->batch_pool);
+ intel_engine_fini_breadcrumbs(engine);
engine->i915 = NULL;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 929e7b4af2a4..28597ea8fbf9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -160,6 +160,31 @@ struct intel_engine_cs {
struct intel_ringbuffer *buffer;
struct list_head buffers;
+ /* Rather than have every client wait upon all user interrupts,
+ * with the herd waking after every interrupt and each doing the
+ * heavyweight seqno dance, we delegate the task (of being the
+ * bottom-half of the user interrupt) to the first client. After
+ * every interrupt, we wake up one client, who does the heavyweight
+ * coherent seqno read and either goes back to sleep (if incomplete),
+ * or wakes up all the completed clients in parallel, before then
+ * transferring the bottom-half status to the next client in the queue.
+ *
+ * Compared to walking the entire list of waiters in a single dedicated
+ * bottom-half, we reduce the latency of the first waiter by avoiding
+ * a context switch, but incur additional coherent seqno reads when
+ * following the chain of request breadcrumbs. Since it is most likely
+ * that we have a single client waiting on each seqno, then reducing
+ * the overhead of waking that client is much preferred.
+ */
+ struct intel_breadcrumbs {
+ spinlock_t lock; /* protects the lists of requests */
+ struct rb_root waiters; /* sorted by retirement, priority */
+ struct task_struct *first_waiter; /* bh for user interrupts */
+ struct timer_list fake_irq; /* used after a missed interrupt */
+ bool irq_enabled;
+ bool rpm_wakelock;
+ } breadcrumbs;
+
/*
* A pool of objects to use as shadow copies of client batch buffers
* when the command parser is enabled. Prevents the client from
@@ -308,8 +333,6 @@ struct intel_engine_cs {
bool gpu_caches_dirty;
- wait_queue_head_t irq_queue;
-
struct intel_context *last_context;
struct intel_ring_hangcheck hangcheck;
@@ -495,4 +518,44 @@ static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
}
+/* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
+struct intel_wait {
+ struct rb_node node;
+ struct task_struct *task;
+ u32 seqno;
+};
+void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
+static inline void intel_wait_init(struct intel_wait *wait, u32 seqno)
+{
+ wait->task = current;
+ wait->seqno = seqno;
+}
+static inline bool intel_wait_complete(const struct intel_wait *wait)
+{
+ return RB_EMPTY_NODE(&wait->node);
+}
+bool intel_engine_add_wait(struct intel_engine_cs *engine,
+ struct intel_wait *wait);
+void intel_engine_remove_wait(struct intel_engine_cs *engine,
+ struct intel_wait *wait);
+static inline bool intel_engine_has_waiter(struct intel_engine_cs *engine)
+{
+ return READ_ONCE(engine->breadcrumbs.first_waiter);
+}
+static inline bool intel_engine_wakeup(struct intel_engine_cs *engine)
+{
+ bool wakeup = false;
+ struct task_struct *task = READ_ONCE(engine->breadcrumbs.first_waiter);
+ /* Note that for this not to dangerously chase a dangling pointer,
+ * the caller is responsible for ensure that the task remain valid for
+ * wake_up_process() i.e. that the RCU grace period cannot expire.
+ */
+ if (task)
+ wakeup = wake_up_process(task);
+ return wakeup;
+}
+void intel_engine_enable_fake_irq(struct intel_engine_cs *engine);
+void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
+unsigned intel_kick_waiters(struct drm_i915_private *i915);
+
#endif /* _INTEL_RINGBUFFER_H_ */
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 09/19] drm/i915: Remove the lazy_coherency parameter from request-completed?
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (6 preceding siblings ...)
2016-05-05 9:15 ` [PATCH 08/19] drm/i915: Slaughter the thundering i915_wait_request herd Chris Wilson
@ 2016-05-05 9:15 ` Chris Wilson
2016-05-05 9:15 ` [PATCH 10/19] drm/i915: Use HWS for seqno tracking everywhere Chris Wilson
` (9 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx
Now that we have split out the seqno-barrier from the
engine->get_seqno() callback itself, we can move the users of the
seqno-barrier to the required callsites simplifying the common code and
making the required workaround handling much more explicit.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 17 ++++++++---------
drivers/gpu/drm/i915/i915_gem.c | 24 ++++++++++++++++--------
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
5 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index bb1f3e2e85e5..fbe3bf92e838 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -632,7 +632,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
i915_gem_request_get_seqno(work->flip_queued_req),
dev_priv->next_seqno,
engine->get_seqno(engine),
- i915_gem_request_completed(work->flip_queued_req, true));
+ i915_gem_request_completed(work->flip_queued_req));
} else
seq_printf(m, "Flip not associated with any ring\n");
seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f4a9a4568a21..e4af53b00477 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3094,20 +3094,14 @@ i915_seqno_passed(uint32_t seq1, uint32_t seq2)
return (int32_t)(seq1 - seq2) >= 0;
}
-static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
- bool lazy_coherency)
+static inline bool i915_gem_request_started(struct drm_i915_gem_request *req)
{
- if (!lazy_coherency && req->engine->irq_seqno_barrier)
- req->engine->irq_seqno_barrier(req->engine);
return i915_seqno_passed(req->engine->get_seqno(req->engine),
req->previous_seqno);
}
-static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
- bool lazy_coherency)
+static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req)
{
- if (!lazy_coherency && req->engine->irq_seqno_barrier)
- req->engine->irq_seqno_barrier(req->engine);
return i915_seqno_passed(req->engine->get_seqno(req->engine),
req->seqno);
}
@@ -3773,6 +3767,8 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
{
+ struct intel_engine_cs *engine = req->engine;
+
/* Ensure our read of the seqno is coherent so that we
* do not "miss an interrupt" (i.e. if this is the last
* request and the seqno write from the GPU is not visible
@@ -3784,7 +3780,10 @@ static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
* but it is easier and safer to do it every time the waiter
* is woken.
*/
- if (i915_gem_request_completed(req, false))
+ if (engine->irq_seqno_barrier)
+ engine->irq_seqno_barrier(engine);
+
+ if (i915_gem_request_completed(req))
return true;
/* We need to check whether any gpu reset happened in between
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 23d89859cbb9..e3dbcf6178bc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1171,12 +1171,12 @@ static bool __i915_spin_request(struct drm_i915_gem_request *req, int state)
*/
/* Only spin if we know the GPU is processing this request */
- if (!i915_gem_request_started(req, true))
+ if (!i915_gem_request_started(req))
return false;
timeout = local_clock_us(&cpu) + 5;
do {
- if (i915_gem_request_completed(req, true))
+ if (i915_gem_request_completed(req))
return true;
if (signal_pending_state(state, current))
@@ -1223,7 +1223,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
if (list_empty(&req->list))
return 0;
- if (i915_gem_request_completed(req, true))
+ if (i915_gem_request_completed(req))
return 0;
timeout_remain = MAX_SCHEDULE_TIMEOUT;
@@ -2772,8 +2772,16 @@ i915_gem_find_active_request(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *request;
+ /* We are called by the error capture and reset at a random
+ * point in time. In particular, note that neither is crucially
+ * ordered with an interrupt. After a hang, the GPU is dead and we
+ * assume that no more writes can happen (we waited long enough for
+ * all writes that were in transaction to be flushed) - adding an
+ * extra delay for a recent interrupt is pointless. Hence, we do
+ * not need an engine->irq_seqno_barrier() before the seqno reads.
+ */
list_for_each_entry(request, &engine->request_list, list) {
- if (i915_gem_request_completed(request, false))
+ if (i915_gem_request_completed(request))
continue;
return request;
@@ -2904,7 +2912,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
struct drm_i915_gem_request,
list);
- if (!i915_gem_request_completed(request, true))
+ if (!i915_gem_request_completed(request))
break;
i915_gem_request_retire(request);
@@ -2928,7 +2936,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
}
if (unlikely(engine->trace_irq_req &&
- i915_gem_request_completed(engine->trace_irq_req, true))) {
+ i915_gem_request_completed(engine->trace_irq_req))) {
engine->irq_put(engine);
i915_gem_request_assign(&engine->trace_irq_req, NULL);
}
@@ -3028,7 +3036,7 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
if (list_empty(&req->list))
goto retire;
- if (i915_gem_request_completed(req, true)) {
+ if (i915_gem_request_completed(req)) {
__i915_gem_request_retire__upto(req);
retire:
i915_gem_object_retire__read(obj, i);
@@ -3137,7 +3145,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (to == from)
return 0;
- if (i915_gem_request_completed(from_req, true))
+ if (i915_gem_request_completed(from_req))
return 0;
if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6e2e2b98d323..fe45ce072327 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11451,7 +11451,7 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev,
if (work->flip_ready_vblank == 0) {
if (work->flip_queued_req &&
- !i915_gem_request_completed(work->flip_queued_req, true))
+ !i915_gem_request_completed(work->flip_queued_req))
return false;
work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ba097f2dd561..533007fe8573 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7404,7 +7404,7 @@ static void __intel_rps_boost_work(struct work_struct *work)
struct request_boost *boost = container_of(work, struct request_boost, work);
struct drm_i915_gem_request *req = boost->req;
- if (!i915_gem_request_completed(req, true))
+ if (!i915_gem_request_completed(req))
gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
i915_gem_request_unreference(req);
@@ -7419,7 +7419,7 @@ void intel_queue_rps_boost_for_request(struct drm_device *dev,
if (req == NULL || INTEL_INFO(dev)->gen < 6)
return;
- if (i915_gem_request_completed(req, true))
+ if (i915_gem_request_completed(req))
return;
boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 10/19] drm/i915: Use HWS for seqno tracking everywhere
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (7 preceding siblings ...)
2016-05-05 9:15 ` [PATCH 09/19] drm/i915: Remove the lazy_coherency parameter from request-completed? Chris Wilson
@ 2016-05-05 9:15 ` Chris Wilson
2016-05-05 9:16 ` [PATCH 11/19] drm/i915: Add a delay between interrupt and inspecting the final seqno (ilk) Chris Wilson
` (8 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:15 UTC (permalink / raw)
To: intel-gfx
By using the same address for storing the HWS on every platform, we can
remove the platform specific vfuncs and reduce the get-seqno routine to
a single read of a cached memory location.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_trace.h | 2 +-
drivers/gpu/drm/i915/intel_breadcrumbs.c | 4 +-
drivers/gpu/drm/i915/intel_lrc.c | 26 +---------
drivers/gpu/drm/i915/intel_ringbuffer.c | 83 ++++++++------------------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 +--
9 files changed, 36 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fbe3bf92e838..4b5b4231b498 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -631,7 +631,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
engine->name,
i915_gem_request_get_seqno(work->flip_queued_req),
dev_priv->next_seqno,
- engine->get_seqno(engine),
+ intel_engine_get_seqno(engine),
i915_gem_request_completed(work->flip_queued_req));
} else
seq_printf(m, "Flip not associated with any ring\n");
@@ -765,7 +765,7 @@ static void i915_ring_seqno_info(struct seq_file *m,
struct rb_node *rb;
seq_printf(m, "Current sequence (%s): %x\n",
- engine->name, engine->get_seqno(engine));
+ engine->name, intel_engine_get_seqno(engine));
seq_printf(m, "Current user interrupts (%s): %x\n",
engine->name, READ_ONCE(engine->user_interrupts));
@@ -1391,7 +1391,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
for_each_engine_id(engine, dev_priv, id) {
acthd[id] = intel_ring_get_active_head(engine);
- seqno[id] = engine->get_seqno(engine);
+ seqno[id] = intel_engine_get_seqno(engine);
}
i915_get_extra_instdone(dev_priv, instdone);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e4af53b00477..4c99edc06b94 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3096,13 +3096,13 @@ i915_seqno_passed(uint32_t seq1, uint32_t seq2)
static inline bool i915_gem_request_started(struct drm_i915_gem_request *req)
{
- return i915_seqno_passed(req->engine->get_seqno(req->engine),
+ return i915_seqno_passed(intel_engine_get_seqno(req->engine),
req->previous_seqno);
}
static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req)
{
- return i915_seqno_passed(req->engine->get_seqno(req->engine),
+ return i915_seqno_passed(intel_engine_get_seqno(req->engine),
req->seqno);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 34e5ba3f7c7a..b24450140cc8 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -929,7 +929,7 @@ static void i915_record_ring_state(struct drm_i915_private *dev_priv,
ering->waiting = intel_engine_has_waiter(engine);
ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
ering->acthd = intel_ring_get_active_head(engine);
- ering->seqno = engine->get_seqno(engine);
+ ering->seqno = intel_engine_get_seqno(engine);
ering->last_seqno = engine->last_submitted_seqno;
ering->start = I915_READ_START(engine);
ering->head = I915_READ_HEAD(engine);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 70bfa5af0ad1..d973606c2a32 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2992,7 +2992,7 @@ static int semaphore_passed(struct intel_engine_cs *engine)
if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
return -1;
- if (i915_seqno_passed(signaller->get_seqno(signaller), seqno))
+ if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
return 1;
/* cursory check for an unkickable deadlock */
@@ -3180,7 +3180,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
engine->irq_seqno_barrier(engine);
acthd = intel_ring_get_active_head(engine);
- seqno = engine->get_seqno(engine);
+ seqno = intel_engine_get_seqno(engine);
/* Reset stuck interrupts between batch advances */
user_interrupts = 0;
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 20b2e4039792..09bbb71e9ec5 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -558,7 +558,7 @@ TRACE_EVENT(i915_gem_request_notify,
TP_fast_assign(
__entry->dev = engine->i915->dev->primary->index;
__entry->ring = engine->id;
- __entry->seqno = engine->get_seqno(engine);
+ __entry->seqno = intel_engine_get_seqno(engine);
),
TP_printk("dev=%u, ring=%u, seqno=%u",
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index c82ecbf7470a..37f8fe19f122 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -148,7 +148,7 @@ bool intel_engine_add_wait(struct intel_engine_cs *engine,
first = true;
parent = NULL;
completed = NULL;
- seqno = engine->get_seqno(engine);
+ seqno = intel_engine_get_seqno(engine);
p = &b->waiters.rb_node;
while (*p) {
@@ -264,7 +264,7 @@ void intel_engine_remove_wait(struct intel_engine_cs *engine,
* the first_waiter. This is undesirable if that
* waiter is a high priority task.
*/
- u32 seqno = engine->get_seqno(engine);
+ u32 seqno = intel_engine_get_seqno(engine);
while (i915_seqno_passed(seqno, to_wait(next)->seqno)) {
struct rb_node *n = rb_next(next);
__intel_breadcrumbs_finish(b, to_wait(next));
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a29ccbd2ca91..8a4b3cd9623f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1716,16 +1716,6 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
return 0;
}
-static u32 gen8_get_seqno(struct intel_engine_cs *engine)
-{
- return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
-}
-
-static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno)
-{
- intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
-}
-
static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
{
/*
@@ -1741,14 +1731,6 @@ static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
}
-static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno)
-{
- intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
-
- /* See bxt_a_get_seqno() explaining the reason for the clflush. */
- intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
-}
-
/*
* Reserve space for 2 NOOPs at the end of each request to be
* used as a workaround for not being allowed to do lite
@@ -1774,7 +1756,7 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
intel_hws_seqno_address(request->engine) |
MI_FLUSH_DW_USE_GTT);
intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
+ intel_logical_ring_emit(ringbuf, request->seqno);
intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
intel_logical_ring_emit(ringbuf, MI_NOOP);
return intel_logical_ring_advance_and_submit(request);
@@ -1920,12 +1902,8 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->irq_get = gen8_logical_ring_get_irq;
engine->irq_put = gen8_logical_ring_put_irq;
engine->emit_bb_start = gen8_emit_bb_start;
- engine->get_seqno = gen8_get_seqno;
- engine->set_seqno = gen8_set_seqno;
- if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
engine->irq_seqno_barrier = bxt_a_seqno_barrier;
- engine->set_seqno = bxt_a_set_seqno;
- }
}
static inline void
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5fa582e2b93c..d3558505aac0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1281,19 +1281,17 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
return ret;
for_each_engine_id(waiter, dev_priv, id) {
- u32 seqno;
u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
- seqno = i915_gem_request_get_seqno(signaller_req);
intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_CS_STALL);
intel_ring_emit(signaller, lower_32_bits(gtt_offset));
intel_ring_emit(signaller, upper_32_bits(gtt_offset));
- intel_ring_emit(signaller, seqno);
+ intel_ring_emit(signaller, signaller_req->seqno);
intel_ring_emit(signaller, 0);
intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
MI_SEMAPHORE_TARGET(waiter->hw_id));
@@ -1322,18 +1320,16 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
return ret;
for_each_engine_id(waiter, dev_priv, id) {
- u32 seqno;
u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
- seqno = i915_gem_request_get_seqno(signaller_req);
intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
MI_FLUSH_DW_OP_STOREDW);
intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
MI_FLUSH_DW_USE_GTT);
intel_ring_emit(signaller, upper_32_bits(gtt_offset));
- intel_ring_emit(signaller, seqno);
+ intel_ring_emit(signaller, signaller_req->seqno);
intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
MI_SEMAPHORE_TARGET(waiter->hw_id));
intel_ring_emit(signaller, 0);
@@ -1364,11 +1360,9 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
if (i915_mmio_reg_valid(mbox_reg)) {
- u32 seqno = i915_gem_request_get_seqno(signaller_req);
-
intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
intel_ring_emit_reg(signaller, mbox_reg);
- intel_ring_emit(signaller, seqno);
+ intel_ring_emit(signaller, signaller_req->seqno);
}
}
@@ -1404,7 +1398,7 @@ gen6_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
intel_ring_emit(engine,
I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
- intel_ring_emit(engine, i915_gem_request_get_seqno(req));
+ intel_ring_emit(engine, req->seqno);
intel_ring_emit(engine, MI_USER_INTERRUPT);
__intel_ring_advance(engine);
@@ -1543,7 +1537,9 @@ static int
pc_render_add_request(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
- u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 addr = engine->status_page.gfx_addr +
+ (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
+ u32 scratch_addr = addr;
int ret;
/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
@@ -1559,12 +1555,12 @@ pc_render_add_request(struct drm_i915_gem_request *req)
return ret;
intel_ring_emit(engine,
- GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
+ GFX_OP_PIPE_CONTROL(4) |
+ PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
- intel_ring_emit(engine,
- engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
- intel_ring_emit(engine, i915_gem_request_get_seqno(req));
+ intel_ring_emit(engine, addr | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(engine, req->seqno);
intel_ring_emit(engine, 0);
PIPE_CONTROL_FLUSH(engine, scratch_addr);
scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
@@ -1579,13 +1575,12 @@ pc_render_add_request(struct drm_i915_gem_request *req)
PIPE_CONTROL_FLUSH(engine, scratch_addr);
intel_ring_emit(engine,
- GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
+ GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_NOTIFY);
- intel_ring_emit(engine,
- engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
- intel_ring_emit(engine, i915_gem_request_get_seqno(req));
+ intel_ring_emit(engine, addr | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(engine, req->seqno);
intel_ring_emit(engine, 0);
__intel_ring_advance(engine);
@@ -1617,30 +1612,6 @@ gen6_seqno_barrier(struct intel_engine_cs *engine)
spin_unlock_irq(&dev_priv->uncore.lock);
}
-static u32
-ring_get_seqno(struct intel_engine_cs *engine)
-{
- return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
-}
-
-static void
-ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
-{
- intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
-}
-
-static u32
-pc_render_get_seqno(struct intel_engine_cs *engine)
-{
- return engine->scratch.cpu_page[0];
-}
-
-static void
-pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
-{
- engine->scratch.cpu_page[0] = seqno;
-}
-
static bool
gen5_ring_get_irq(struct intel_engine_cs *engine)
{
@@ -1770,8 +1741,8 @@ i9xx_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
intel_ring_emit(engine,
- I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
- intel_ring_emit(engine, i915_gem_request_get_seqno(req));
+ I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
+ intel_ring_emit(engine, req->seqno);
intel_ring_emit(engine, MI_USER_INTERRUPT);
__intel_ring_advance(engine);
@@ -2521,7 +2492,9 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
memset(engine->semaphore.sync_seqno, 0,
sizeof(engine->semaphore.sync_seqno));
- engine->set_seqno(engine, seqno);
+ intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
+ if (engine->irq_seqno_barrier)
+ engine->irq_seqno_barrier(engine);
engine->last_submitted_seqno = seqno;
engine->hangcheck.seqno = seqno;
@@ -2763,8 +2736,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_get = gen8_ring_get_irq;
engine->irq_put = gen8_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (i915_semaphore_is_enabled(dev_priv)) {
WARN_ON(!dev_priv->semaphore_obj);
engine->semaphore.sync_to = gen8_ring_sync;
@@ -2781,8 +2752,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_put = gen6_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine->irq_seqno_barrier = gen6_seqno_barrier;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
@@ -2807,8 +2776,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
} else if (IS_GEN5(dev)) {
engine->add_request = pc_render_add_request;
engine->flush = gen4_render_ring_flush;
- engine->get_seqno = pc_render_get_seqno;
- engine->set_seqno = pc_render_set_seqno;
engine->irq_get = gen5_ring_get_irq;
engine->irq_put = gen5_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
@@ -2819,8 +2786,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen2_render_ring_flush;
else
engine->flush = gen4_render_ring_flush;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (IS_GEN2(dev)) {
engine->irq_get = i8xx_ring_get_irq;
engine->irq_put = i8xx_ring_put_irq;
@@ -2898,8 +2863,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->flush = gen6_bsd_ring_flush;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (INTEL_INFO(dev)->gen >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
@@ -2937,8 +2900,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->mmio_base = BSD_RING_BASE;
engine->flush = bsd_ring_flush;
engine->add_request = i9xx_add_request;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (IS_GEN5(dev)) {
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
engine->irq_get = gen5_ring_get_irq;
@@ -2973,8 +2934,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->flush = gen6_bsd_ring_flush;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
engine->irq_get = gen8_ring_get_irq;
@@ -3006,8 +2965,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
engine->flush = gen6_ring_flush;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (INTEL_INFO(dev)->gen >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
@@ -3066,8 +3023,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
engine->flush = gen6_ring_flush;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (INTEL_INFO(dev)->gen >= 8) {
engine->irq_enable_mask =
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 28597ea8fbf9..559be04b5456 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -218,9 +218,6 @@ struct intel_engine_cs {
* monotonic, even if not coherent.
*/
void (*irq_seqno_barrier)(struct intel_engine_cs *ring);
- u32 (*get_seqno)(struct intel_engine_cs *ring);
- void (*set_seqno)(struct intel_engine_cs *ring,
- u32 seqno);
int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
u64 offset, u32 length,
unsigned dispatch_flags);
@@ -496,6 +493,10 @@ int intel_init_blt_ring_buffer(struct drm_device *dev);
int intel_init_vebox_ring_buffer(struct drm_device *dev);
u64 intel_ring_get_active_head(struct intel_engine_cs *engine);
+static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
+{
+ return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
+}
int init_workarounds_ring(struct intel_engine_cs *engine);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 11/19] drm/i915: Add a delay between interrupt and inspecting the final seqno (ilk)
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (8 preceding siblings ...)
2016-05-05 9:15 ` [PATCH 10/19] drm/i915: Use HWS for seqno tracking everywhere Chris Wilson
@ 2016-05-05 9:16 ` Chris Wilson
2016-05-05 9:16 ` [PATCH 12/19] drm/i915: Check the CPU cached value of seqno after waking the waiter Chris Wilson
` (7 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:16 UTC (permalink / raw)
To: intel-gfx
On Ironlake, there is no command nor register to ensure that the write
from a MI_STORE command is completed (and coherent on the CPU) before the
command parser continues. This means that the ordering between the seqno
write and the subsequent user interrupt is undefined (like gen6+). So to
ensure that the seqno write is completed after the final user interrupt
we need to delay the read sufficiently to allow the write to complete.
This delay is undefined by the bspec, and empirically requires 75us even
though a register read combined with a clflush is less than 500ns. Hence,
the delay is due to an on-chip buffer rather than the latency of the write
to memory.
Note that the render ring controls this by filling the PIPE_CONTROL fifo
with stalling commands that force the earliest pipe-control with the
seqno to be completed before the command parser continues. Given that we
need a barrier operation for BSD, we may as well forgo the extra
per-batch latency by using a common per-interrupt barrier.
Studying the impact of adding the usleep shows that in both sequences of
and individual synchronous no-op batches is negligible for the media
engine (where the write now is unordered with the interrupt). Converting
the render engine over from the current glutton of pie-controls over to
the per-interrupt delays speeds up both the sequential and individual
synchronous no-ops by 20% and 60%, respectively. This speed up holds
even when looking at the throughput of small copies (4KiB->4MiB), both
serial and synchronous, by about 20%. This is because despite adding a
significant delay to the interrupt, in all likelihood we will see the
seqno write without having to apply the barrier (only in the rare corner
cases where the write is delayed on the last required is the delay
necessary).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94307
Testcase: igt/gem_sync #ilk
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_irq.c | 10 ++---
drivers/gpu/drm/i915/intel_ringbuffer.c | 80 ++++++++-------------------------
2 files changed, 21 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d973606c2a32..2fafa34386a3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1284,8 +1284,7 @@ static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv
static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
u32 gt_iir)
{
- if (gt_iir &
- (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
+ if (gt_iir & GT_RENDER_USER_INTERRUPT)
notify_ring(&dev_priv->engine[RCS]);
if (gt_iir & ILK_BSD_USER_INTERRUPT)
notify_ring(&dev_priv->engine[VCS]);
@@ -1294,9 +1293,7 @@ static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
u32 gt_iir)
{
-
- if (gt_iir &
- (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
+ if (gt_iir & GT_RENDER_USER_INTERRUPT)
notify_ring(&dev_priv->engine[RCS]);
if (gt_iir & GT_BSD_USER_INTERRUPT)
notify_ring(&dev_priv->engine[VCS]);
@@ -3646,8 +3643,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
gt_irqs |= GT_RENDER_USER_INTERRUPT;
if (IS_GEN5(dev)) {
- gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
- ILK_BSD_USER_INTERRUPT;
+ gt_irqs |= ILK_BSD_USER_INTERRUPT;
} else {
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d3558505aac0..2624cc7184dc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1524,67 +1524,22 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
return 0;
}
-#define PIPE_CONTROL_FLUSH(ring__, addr__) \
-do { \
- intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
- PIPE_CONTROL_DEPTH_STALL); \
- intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
- intel_ring_emit(ring__, 0); \
- intel_ring_emit(ring__, 0); \
-} while (0)
-
-static int
-pc_render_add_request(struct drm_i915_gem_request *req)
+static void
+gen5_seqno_barrier(struct intel_engine_cs *ring)
{
- struct intel_engine_cs *engine = req->engine;
- u32 addr = engine->status_page.gfx_addr +
- (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
- u32 scratch_addr = addr;
- int ret;
-
- /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
- * incoherent with writes to memory, i.e. completely fubar,
- * so we need to use PIPE_NOTIFY instead.
+ /* MI_STORE are internally buffered by the GPU and not flushed
+ * either by MI_FLUSH or SyncFlush or any other combination of
+ * MI commands.
*
- * However, we also need to workaround the qword write
- * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
- * memory before requesting an interrupt.
+ * "Only the submission of the store operation is guaranteed.
+ * The write result will be complete (coherent) some time later
+ * (this is practically a finite period but there is no guaranteed
+ * latency)."
+ *
+ * Empirically, we observe that we need a delay of at least 75us to
+ * be sure that the seqno write is visible by the CPU.
*/
- ret = intel_ring_begin(req, 32);
- if (ret)
- return ret;
-
- intel_ring_emit(engine,
- GFX_OP_PIPE_CONTROL(4) |
- PIPE_CONTROL_QW_WRITE |
- PIPE_CONTROL_WRITE_FLUSH |
- PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
- intel_ring_emit(engine, addr | PIPE_CONTROL_GLOBAL_GTT);
- intel_ring_emit(engine, req->seqno);
- intel_ring_emit(engine, 0);
- PIPE_CONTROL_FLUSH(engine, scratch_addr);
- scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
- PIPE_CONTROL_FLUSH(engine, scratch_addr);
- scratch_addr += 2 * CACHELINE_BYTES;
- PIPE_CONTROL_FLUSH(engine, scratch_addr);
- scratch_addr += 2 * CACHELINE_BYTES;
- PIPE_CONTROL_FLUSH(engine, scratch_addr);
- scratch_addr += 2 * CACHELINE_BYTES;
- PIPE_CONTROL_FLUSH(engine, scratch_addr);
- scratch_addr += 2 * CACHELINE_BYTES;
- PIPE_CONTROL_FLUSH(engine, scratch_addr);
-
- intel_ring_emit(engine,
- GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
- PIPE_CONTROL_WRITE_FLUSH |
- PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
- PIPE_CONTROL_NOTIFY);
- intel_ring_emit(engine, addr | PIPE_CONTROL_GLOBAL_GTT);
- intel_ring_emit(engine, req->seqno);
- intel_ring_emit(engine, 0);
- __intel_ring_advance(engine);
-
- return 0;
+ usleep_range(75, 250);
}
static void
@@ -2774,12 +2729,12 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
}
} else if (IS_GEN5(dev)) {
- engine->add_request = pc_render_add_request;
+ engine->add_request = i9xx_add_request;
engine->flush = gen4_render_ring_flush;
engine->irq_get = gen5_ring_get_irq;
engine->irq_put = gen5_ring_put_irq;
- engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
- GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
+ engine->irq_seqno_barrier = gen5_seqno_barrier;
+ engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
} else {
engine->add_request = i9xx_add_request;
if (INTEL_INFO(dev)->gen < 4)
@@ -2835,7 +2790,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
if (ret)
return ret;
- if (INTEL_INFO(dev)->gen >= 5) {
+ if (INTEL_INFO(dev)->gen >= 6) {
ret = intel_init_pipe_control(engine);
if (ret)
return ret;
@@ -2904,6 +2859,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
engine->irq_get = gen5_ring_get_irq;
engine->irq_put = gen5_ring_put_irq;
+ engine->irq_seqno_barrier = gen5_seqno_barrier;
} else {
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
engine->irq_get = i9xx_ring_get_irq;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 12/19] drm/i915: Check the CPU cached value of seqno after waking the waiter
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (9 preceding siblings ...)
2016-05-05 9:16 ` [PATCH 11/19] drm/i915: Add a delay between interrupt and inspecting the final seqno (ilk) Chris Wilson
@ 2016-05-05 9:16 ` Chris Wilson
2016-05-05 9:16 ` [PATCH 13/19] drm/i915: Only apply one barrier after a breadcrumb interrupt is posted Chris Wilson
` (6 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:16 UTC (permalink / raw)
To: intel-gfx
If we have multiple waiters, we may find that many complete on the same
wake up. If we first inspect the seqno from the CPU cache, we may reduce
the number of heavyweight coherent seqno reads we require.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4c99edc06b94..e3f014c8f1f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3769,6 +3769,12 @@ static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
+ /* Before we do the heavier coherent read of the seqno,
+ * check the value (hopefully) in the CPU cacheline.
+ */
+ if (i915_gem_request_completed(req))
+ return true;
+
/* Ensure our read of the seqno is coherent so that we
* do not "miss an interrupt" (i.e. if this is the last
* request and the seqno write from the GPU is not visible
@@ -3780,11 +3786,11 @@ static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
* but it is easier and safer to do it every time the waiter
* is woken.
*/
- if (engine->irq_seqno_barrier)
+ if (engine->irq_seqno_barrier) {
engine->irq_seqno_barrier(engine);
-
- if (i915_gem_request_completed(req))
- return true;
+ if (i915_gem_request_completed(req))
+ return true;
+ }
/* We need to check whether any gpu reset happened in between
* the request being submitted and now. If a reset has occurred,
--
2.8.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 13/19] drm/i915: Only apply one barrier after a breadcrumb interrupt is posted
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (10 preceding siblings ...)
2016-05-05 9:16 ` [PATCH 12/19] drm/i915: Check the CPU cached value of seqno after waking the waiter Chris Wilson
@ 2016-05-05 9:16 ` Chris Wilson
2016-05-05 9:16 ` [PATCH 14/19] drm/i915: Stop setting wraparound seqno on initialisation Chris Wilson
` (5 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:16 UTC (permalink / raw)
To: intel-gfx
If we flag the seqno as potentially stale upon receiving an interrupt,
we can use that information to reduce the frequency that we apply the
heavyweight coherent seqno read (i.e. if we wake up a chain of waiters).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 15 ++++++++++++++-
drivers/gpu/drm/i915/i915_irq.c | 1 +
drivers/gpu/drm/i915/intel_breadcrumbs.c | 11 ++++++++++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
4 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e3f014c8f1f0..08956485afc5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3786,7 +3786,20 @@ static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
* but it is easier and safer to do it every time the waiter
* is woken.
*/
- if (engine->irq_seqno_barrier) {
+ if (engine->irq_seqno_barrier && READ_ONCE(engine->irq_posted)) {
+ /* The ordering of irq_posted versus applying the barrier
+ * is crucial. The clearing of the current irq_posted must
+ * be visible before we perform the barrier operation,
+ * such that if a subsequent interrupt arrives, irq_posted
+ * is reasserted and our task rewoken (which causes us to
+ * do another __i915_request_irq_complete() immediately
+ * and reapply the barrier). Conversely, if the clear
+ * occurs after the barrier, then an interrupt that arrived
+ * whilst we waited on the barrier would not trigger a
+ * barrier on the next pass, and the read may not see the
+ * seqno update.
+ */
+ WRITE_ONCE(engine->irq_posted, false);
engine->irq_seqno_barrier(engine);
if (i915_gem_request_completed(req))
return true;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2fafa34386a3..bcce52507b33 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -996,6 +996,7 @@ static void ironlake_rps_change_irq_handler(struct drm_device *dev)
static void notify_ring(struct intel_engine_cs *engine)
{
+ smp_store_mb(engine->irq_posted, true);
if (intel_engine_wakeup(engine)) {
trace_i915_gem_request_notify(engine);
engine->user_interrupts++;
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 37f8fe19f122..578de43cb07e 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -43,12 +43,20 @@ static void intel_breadcrumbs_fake_irq(unsigned long data)
static void irq_enable(struct intel_engine_cs *engine)
{
+ /* Enabling the IRQ may miss the generation of the interrupt, but
+ * we still need to force the barrier before reading the seqno,
+ * just in case.
+ */
+ engine->irq_posted = true;
+
WARN_ON(!engine->irq_get(engine));
}
static void irq_disable(struct intel_engine_cs *engine)
{
engine->irq_put(engine);
+
+ engine->irq_posted = false;
}
static bool __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b)
@@ -194,7 +202,8 @@ bool intel_engine_add_wait(struct intel_engine_cs *engine,
* in case the seqno passed.
*/
__intel_breadcrumbs_enable_irq(b);
- wake_up_process(to_wait(next)->task);
+ if (READ_ONCE(engine->irq_posted))
+ wake_up_process(to_wait(next)->task);
}
do {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 559be04b5456..30fe1140b22a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -196,6 +196,7 @@ struct intel_engine_cs {
struct i915_ctx_workarounds wa_ctx;
unsigned irq_refcount; /* protected by dev_priv->irq_lock */
+ bool irq_posted;
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
struct drm_i915_gem_request *trace_irq_req;
bool __must_check (*irq_get)(struct intel_engine_cs *ring);
--
2.8.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 14/19] drm/i915: Stop setting wraparound seqno on initialisation
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (11 preceding siblings ...)
2016-05-05 9:16 ` [PATCH 13/19] drm/i915: Only apply one barrier after a breadcrumb interrupt is posted Chris Wilson
@ 2016-05-05 9:16 ` Chris Wilson
2016-05-05 9:16 ` [PATCH 15/19] drm/i915: Only query timestamp when measuring elapsed time Chris Wilson
` (4 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:16 UTC (permalink / raw)
To: intel-gfx
We have testcases to ensure that seqno wraparound works fine, so we can
forgo forcing everyone to encounter seqno wraparound during early
uptime. seqno wraparound incurs a full GPU stall so not forcing it
will eliminate one jitter from the early system. Using the testcases, we
have very deterministic testing which given how difficult it would be to
debug an issue (GPU hang) stemming from a wraparound using pure
postmortem analysis I see no value in forcing a wrap during boot.
Advancing the global next_seqno after a GPU reset is equally pointless.
References? https://bugs.freedesktop.org/show_bug.cgi?id=95023
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e3dbcf6178bc..8c8b44883657 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4847,12 +4847,6 @@ i915_gem_init_hw(struct drm_device *dev)
}
}
- /*
- * Increment the next seqno by 0x100 so we have a visible break
- * on re-initialisation
- */
- ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
-
out:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
return ret;
@@ -4997,14 +4991,6 @@ i915_gem_load_init(struct drm_device *dev)
dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
- /*
- * Set initial sequence number for requests.
- * Using this number allows the wraparound to happen early,
- * catching any obvious problems.
- */
- dev_priv->next_seqno = ((u32)~0 - 0x1100);
- dev_priv->last_seqno = ((u32)~0 - 0x1101);
-
INIT_LIST_HEAD(&dev_priv->mm.fence_list);
init_waitqueue_head(&dev_priv->pending_flip_queue);
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 15/19] drm/i915: Only query timestamp when measuring elapsed time
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (12 preceding siblings ...)
2016-05-05 9:16 ` [PATCH 14/19] drm/i915: Stop setting wraparound seqno on initialisation Chris Wilson
@ 2016-05-05 9:16 ` Chris Wilson
2016-05-05 9:16 ` [PATCH 16/19] drm/i915: Convert trace-irq to the breadcrumb waiter Chris Wilson
` (3 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:16 UTC (permalink / raw)
To: intel-gfx
Avoid the two calls to ktime_get_raw_ns() (at best it reads the TSC) as
we only need to compute the elapsed time for a timed wait.
v2: Eliminate the unused local variable reducing the function size by 64
bytes (using the storage space on the callers stack rather than adding
to our stack frame)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8c8b44883657..e29cac614df5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1215,7 +1215,6 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
struct intel_wait wait;
unsigned long timeout_remain;
- s64 before = 0; /* Only to silence a compiler warning. */
int ret = 0;
might_sleep();
@@ -1234,12 +1233,9 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
if (*timeout == 0)
return -ETIME;
+ /* Record current time in case interrupted, or wedged */
timeout_remain = nsecs_to_jiffies_timeout(*timeout);
-
- /*
- * Record current time in case interrupted by signal, or wedged.
- */
- before = ktime_get_raw_ns();
+ *timeout += ktime_get_raw_ns();
}
trace_i915_gem_request_wait_begin(req);
@@ -1296,9 +1292,9 @@ complete:
trace_i915_gem_request_wait_end(req);
if (timeout) {
- s64 tres = *timeout - (ktime_get_raw_ns() - before);
-
- *timeout = tres < 0 ? 0 : tres;
+ *timeout -= ktime_get_raw_ns();
+ if (*timeout < 0)
+ *timeout = 0;
/*
* Apparently ktime isn't accurate enough and occasionally has a
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 16/19] drm/i915: Convert trace-irq to the breadcrumb waiter
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (13 preceding siblings ...)
2016-05-05 9:16 ` [PATCH 15/19] drm/i915: Only query timestamp when measuring elapsed time Chris Wilson
@ 2016-05-05 9:16 ` Chris Wilson
2016-05-05 9:16 ` [PATCH 17/19] drm/i915: Move the get/put irq locking into the caller Chris Wilson
` (2 subsequent siblings)
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:16 UTC (permalink / raw)
To: intel-gfx
If we convert the tracing over from direct use of ring->irq_get() and
over to the breadcrumb infrastructure, we only have a single user of the
ring->irq_get and so we will be able to simplify the driver routines
(eliminating the redundant validation and irq refcounting).
v2: Move to a signaling framework based upon the waiter.
v3: Track the first-signal to avoid having to walk the rbtree everytime.
v4: Mark the signaler thread as RT priority to reduce latency in the
indirect wakeups.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 8 --
drivers/gpu/drm/i915/i915_gem.c | 6 --
drivers/gpu/drm/i915/i915_trace.h | 2 +-
drivers/gpu/drm/i915/intel_breadcrumbs.c | 176 +++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 +-
5 files changed, 183 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 08956485afc5..67f7f305e3b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3757,14 +3757,6 @@ wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
schedule_timeout_uninterruptible(remaining_jiffies);
}
}
-
-static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
- struct drm_i915_gem_request *req)
-{
- if (engine->trace_irq_req == NULL && engine->irq_get(engine))
- i915_gem_request_assign(&engine->trace_irq_req, req);
-}
-
static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e29cac614df5..02c00a6ebd67 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2931,12 +2931,6 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
i915_gem_object_retire__read(obj, engine->id);
}
- if (unlikely(engine->trace_irq_req &&
- i915_gem_request_completed(engine->trace_irq_req))) {
- engine->irq_put(engine);
- i915_gem_request_assign(&engine->trace_irq_req, NULL);
- }
-
WARN_ON(i915_verify_lists(engine->dev));
}
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 09bbb71e9ec5..f40ca977321c 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -490,7 +490,7 @@ TRACE_EVENT(i915_gem_ring_dispatch,
__entry->ring = req->engine->id;
__entry->seqno = req->seqno;
__entry->flags = flags;
- i915_trace_irq_get(req->engine, req);
+ intel_engine_enable_signaling(req);
),
TP_printk("dev=%u, ring=%u, seqno=%u, flags=%x",
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 578de43cb07e..14fb9fdcde3a 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -22,6 +22,8 @@
*
*/
+#include <linux/kthread.h>
+
#include "i915_drv.h"
static void intel_breadcrumbs_fake_irq(unsigned long data)
@@ -315,10 +317,184 @@ void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine)
(unsigned long)engine);
}
+struct signal {
+ struct rb_node node;
+ struct intel_wait wait;
+ struct drm_i915_gem_request *request;
+};
+
+static bool signal_complete(struct signal *signal)
+{
+ if (signal == NULL)
+ return false;
+
+ /* If another process served as the bottom-half it may have already
+ * signalled that this wait is already completed.
+ */
+ if (intel_wait_complete(&signal->wait))
+ return true;
+
+ /* Carefully check if the request is complete, giving time for the
+ * seqno to be visible or if the GPU hung.
+ */
+ if (__i915_request_irq_complete(signal->request))
+ return true;
+
+ return false;
+}
+
+static struct signal *to_signal(struct rb_node *rb)
+{
+ return container_of(rb, struct signal, node);
+}
+
+static void signaler_set_rtpriority(void)
+{
+ struct sched_param param = { .sched_priority = 1 };
+ sched_setscheduler_nocheck(current, SCHED_FIFO, ¶m);
+}
+
+static int intel_breadcrumbs_signaler(void *arg)
+{
+ struct intel_engine_cs *engine = arg;
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+ struct signal *signal;
+
+ /* Install ourselves with high priority to reduce signalling latency */
+ signaler_set_rtpriority();
+
+ do {
+ set_current_state(TASK_INTERRUPTIBLE);
+
+ /* We are either woken up by the interrupt bottom-half,
+ * or by a client adding a new signaller. In both cases,
+ * the GPU seqno may have advanced beyond our oldest signal.
+ * If it has, propagate the signal, remove the waiter and
+ * check again with the next oldest signal. Otherwise we
+ * need to wait for a new interrupt from the GPU or for
+ * a new client.
+ */
+ signal = READ_ONCE(b->first_signal);
+ if (signal_complete(signal)) {
+ /* Wake up all other completed waiters and select the
+ * next bottom-half for the next user interrupt.
+ */
+ intel_engine_remove_wait(engine, &signal->wait);
+
+ i915_gem_request_unreference(signal->request);
+
+ /* Find the next oldest signal. Note that as we have
+ * not been holding the lock, another client may
+ * have installed an even older signal than the one
+ * we just completed - so double check we are still
+ * the oldest before picking the next one.
+ */
+ spin_lock(&b->lock);
+ if (signal == b->first_signal)
+ b->first_signal = rb_next(&signal->node);
+ rb_erase(&signal->node, &b->signals);
+ spin_unlock(&b->lock);
+
+ kfree(signal);
+ } else {
+ if (kthread_should_stop())
+ break;
+
+ schedule();
+ }
+ } while (1);
+
+ return 0;
+}
+
+int intel_engine_enable_signaling(struct drm_i915_gem_request *request)
+{
+ struct intel_engine_cs *engine = request->engine;
+ struct intel_breadcrumbs *b = &engine->breadcrumbs;
+ struct rb_node *parent, **p;
+ struct task_struct *task;
+ struct signal *signal;
+ bool first;
+
+ signal = kmalloc(sizeof(*signal), GFP_ATOMIC);
+ if (unlikely(signal == NULL))
+ return -ENOMEM;
+
+ /* Spawn a thread to provide a common bottom-half for all signals.
+ * As this is an asynchronous interface we cannot steal the current
+ * task for handling the bottom-half to the user interrupt, therefore
+ * we create a thread to do the coherent seqno dance after the
+ * interrupt and then signal the waitqueue (via the dma-buf/fence).
+ */
+ task = READ_ONCE(b->signaler);
+ if (unlikely(task == NULL)) {
+ spin_lock(&b->lock);
+ task = b->signaler;
+ if (task == NULL) {
+ task = kthread_create(intel_breadcrumbs_signaler,
+ engine,
+ "irq/i915:%d",
+ engine->id);
+ if (!IS_ERR(task))
+ b->signaler = task;
+ }
+ spin_unlock(&b->lock);
+
+ if (IS_ERR(task)) {
+ kfree(signal);
+ return PTR_ERR(task);
+ }
+ }
+
+ signal->wait.task = task;
+ signal->wait.seqno = request->seqno;
+
+ signal->request = i915_gem_request_reference(request);
+
+ /* Insert ourselves into the retirement ordered list of signals
+ * on this engine. We track the oldest seqno as that will be the
+ * first signal to complete.
+ */
+ spin_lock(&b->lock);
+ parent = NULL;
+ first = true;
+ p = &b->signals.rb_node;
+ while (*p) {
+ parent = *p;
+ if (i915_seqno_passed(signal->wait.seqno,
+ to_signal(parent)->wait.seqno)) {
+ p = &parent->rb_right;
+ first = false;
+ } else
+ p = &parent->rb_left;
+ }
+ rb_link_node(&signal->node, parent, p);
+ rb_insert_color(&signal->node, &b->signals);
+ if (first)
+ smp_store_mb(b->first_signal, signal);
+ spin_unlock(&b->lock);
+
+ /* Now add ourselves into the list of waiters, but register our
+ * bottom-half as the signaller thread. As per usual, only the oldest
+ * waiter (not just signaller) is tasked as the bottom-half waking
+ * up all completed waiters after the user interrupt.
+ *
+ * If we are the oldest waiter, enable the irq (after which we
+ * must double check that the seqno did not complete).
+ */
+ if (intel_engine_add_wait(engine, &signal->wait))
+ wake_up_process(task);
+
+ return 0;
+}
+
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
{
struct intel_breadcrumbs *b = &engine->breadcrumbs;
+ if (b->signaler)
+ kthread_stop(b->signaler);
+
del_timer_sync(&b->fake_irq);
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 30fe1140b22a..8abc2b83a15e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -141,6 +141,8 @@ struct i915_ctx_workarounds {
struct drm_i915_gem_object *obj;
};
+struct drm_i915_gem_request;
+
struct intel_engine_cs {
struct drm_i915_private *i915;
const char *name;
@@ -179,7 +181,10 @@ struct intel_engine_cs {
struct intel_breadcrumbs {
spinlock_t lock; /* protects the lists of requests */
struct rb_root waiters; /* sorted by retirement, priority */
+ struct rb_root signals; /* sorted by retirement */
struct task_struct *first_waiter; /* bh for user interrupts */
+ struct task_struct *signaler; /* used for fence signalling */
+ void *first_signal;
struct timer_list fake_irq; /* used after a missed interrupt */
bool irq_enabled;
bool rpm_wakelock;
@@ -198,7 +203,6 @@ struct intel_engine_cs {
unsigned irq_refcount; /* protected by dev_priv->irq_lock */
bool irq_posted;
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
- struct drm_i915_gem_request *trace_irq_req;
bool __must_check (*irq_get)(struct intel_engine_cs *ring);
void (*irq_put)(struct intel_engine_cs *ring);
@@ -540,6 +544,7 @@ bool intel_engine_add_wait(struct intel_engine_cs *engine,
struct intel_wait *wait);
void intel_engine_remove_wait(struct intel_engine_cs *engine,
struct intel_wait *wait);
+int intel_engine_enable_signaling(struct drm_i915_gem_request *request);
static inline bool intel_engine_has_waiter(struct intel_engine_cs *engine)
{
return READ_ONCE(engine->breadcrumbs.first_waiter);
--
2.8.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 17/19] drm/i915: Move the get/put irq locking into the caller
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (14 preceding siblings ...)
2016-05-05 9:16 ` [PATCH 16/19] drm/i915: Convert trace-irq to the breadcrumb waiter Chris Wilson
@ 2016-05-05 9:16 ` Chris Wilson
2016-05-05 9:16 ` [PATCH 18/19] drm/i915: Simplify enabling user-interrupts with L3-remapping Chris Wilson
2016-05-05 9:16 ` [PATCH 19/19] drm/i915: Remove debug noise on detecting fault-injection of missed interrupts Chris Wilson
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:16 UTC (permalink / raw)
To: intel-gfx
With only a single callsite for intel_engine_cs->irq_get and ->irq_put,
we can reduce the code size by moving the common preamble into the
caller, and we can also eliminate the reference counting.
For completeness, as we are no longer doing reference counting on irq,
rename the get/put vfunctions to enable/disable respectively.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_irq.c | 8 +-
drivers/gpu/drm/i915/intel_breadcrumbs.c | 8 +-
drivers/gpu/drm/i915/intel_lrc.c | 34 +---
drivers/gpu/drm/i915/intel_ringbuffer.c | 269 ++++++++++---------------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +-
5 files changed, 106 insertions(+), 218 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bcce52507b33..09d5de154aee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -259,12 +259,12 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
dev_priv->gt_irq_mask &= ~interrupt_mask;
dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
- POSTING_READ(GTIMR);
}
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
ilk_update_gt_irq(dev_priv, mask, mask);
+ POSTING_READ_FW(GTIMR);
}
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
@@ -2859,9 +2859,9 @@ ring_idle(struct intel_engine_cs *engine, u32 seqno)
}
static bool
-ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr)
+ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
{
- if (INTEL_GEN(dev_priv) >= 8) {
+ if (INTEL_GEN(engine->i915) >= 8) {
return (ipehr >> 23) == 0x1c;
} else {
ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
@@ -2932,7 +2932,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
return NULL;
ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
- if (!ipehr_is_semaphore_wait(engine->i915, ipehr))
+ if (!ipehr_is_semaphore_wait(engine, ipehr))
return NULL;
/*
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 14fb9fdcde3a..475c454d11bf 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -51,12 +51,16 @@ static void irq_enable(struct intel_engine_cs *engine)
*/
engine->irq_posted = true;
- WARN_ON(!engine->irq_get(engine));
+ spin_lock_irq(&engine->i915->irq_lock);
+ engine->irq_enable(engine);
+ spin_unlock_irq(&engine->i915->irq_lock);
}
static void irq_disable(struct intel_engine_cs *engine)
{
- engine->irq_put(engine);
+ spin_lock_irq(&engine->i915->irq_lock);
+ engine->irq_disable(engine);
+ spin_unlock_irq(&engine->i915->irq_lock);
engine->irq_posted = false;
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8a4b3cd9623f..038040b54b08 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1582,36 +1582,18 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
return 0;
}
-static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
+static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
-
- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
- return false;
-
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (engine->irq_refcount++ == 0) {
- I915_WRITE_IMR(engine,
- ~(engine->irq_enable_mask | engine->irq_keep_mask));
- POSTING_READ(RING_IMR(engine->mmio_base));
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
-
- return true;
+ I915_WRITE_IMR(engine,
+ ~(engine->irq_enable_mask | engine->irq_keep_mask));
+ POSTING_READ_FW(RING_IMR(engine->mmio_base));
}
-static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
+static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
-
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--engine->irq_refcount == 0) {
- I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
- POSTING_READ(RING_IMR(engine->mmio_base));
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+ I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
}
static int gen8_emit_flush(struct drm_i915_gem_request *request,
@@ -1899,8 +1881,8 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->init_hw = gen8_init_common_ring;
engine->emit_request = gen8_emit_request;
engine->emit_flush = gen8_emit_flush;
- engine->irq_get = gen8_logical_ring_get_irq;
- engine->irq_put = gen8_logical_ring_put_irq;
+ engine->irq_enable = gen8_logical_ring_enable_irq;
+ engine->irq_disable = gen8_logical_ring_disable_irq;
engine->emit_bb_start = gen8_emit_bb_start;
if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
engine->irq_seqno_barrier = bxt_a_seqno_barrier;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2624cc7184dc..65522c920883 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1567,103 +1567,54 @@ gen6_seqno_barrier(struct intel_engine_cs *engine)
spin_unlock_irq(&dev_priv->uncore.lock);
}
-static bool
-gen5_ring_get_irq(struct intel_engine_cs *engine)
+static void
+gen5_ring_enable_irq(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
-
- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
- return false;
-
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (engine->irq_refcount++ == 0)
- gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
-
- return true;
+ gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
}
static void
-gen5_ring_put_irq(struct intel_engine_cs *engine)
+gen5_ring_disable_irq(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
-
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--engine->irq_refcount == 0)
- gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+ gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
}
-static bool
-i9xx_ring_get_irq(struct intel_engine_cs *engine)
+static void
+i9xx_ring_enable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
-
- if (!intel_irqs_enabled(dev_priv))
- return false;
-
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (engine->irq_refcount++ == 0) {
- dev_priv->irq_mask &= ~engine->irq_enable_mask;
- I915_WRITE(IMR, dev_priv->irq_mask);
- POSTING_READ(IMR);
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
- return true;
+ dev_priv->irq_mask &= ~engine->irq_enable_mask;
+ I915_WRITE(IMR, dev_priv->irq_mask);
+ POSTING_READ_FW(RING_IMR(engine->mmio_base));
}
static void
-i9xx_ring_put_irq(struct intel_engine_cs *engine)
+i9xx_ring_disable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--engine->irq_refcount == 0) {
- dev_priv->irq_mask |= engine->irq_enable_mask;
- I915_WRITE(IMR, dev_priv->irq_mask);
- POSTING_READ(IMR);
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+ dev_priv->irq_mask |= engine->irq_enable_mask;
+ I915_WRITE(IMR, dev_priv->irq_mask);
}
-static bool
-i8xx_ring_get_irq(struct intel_engine_cs *engine)
+static void
+i8xx_ring_enable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
- if (!intel_irqs_enabled(dev_priv))
- return false;
-
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (engine->irq_refcount++ == 0) {
- dev_priv->irq_mask &= ~engine->irq_enable_mask;
- I915_WRITE16(IMR, dev_priv->irq_mask);
- POSTING_READ16(IMR);
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
-
- return true;
+ dev_priv->irq_mask &= ~engine->irq_enable_mask;
+ I915_WRITE16(IMR, dev_priv->irq_mask);
+ POSTING_READ16(RING_IMR(engine->mmio_base));
}
static void
-i8xx_ring_put_irq(struct intel_engine_cs *engine)
+i8xx_ring_disable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--engine->irq_refcount == 0) {
- dev_priv->irq_mask |= engine->irq_enable_mask;
- I915_WRITE16(IMR, dev_priv->irq_mask);
- POSTING_READ16(IMR);
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+ dev_priv->irq_mask |= engine->irq_enable_mask;
+ I915_WRITE16(IMR, dev_priv->irq_mask);
}
static int
@@ -1704,122 +1655,74 @@ i9xx_add_request(struct drm_i915_gem_request *req)
return 0;
}
-static bool
-gen6_ring_get_irq(struct intel_engine_cs *engine)
+static void
+gen6_ring_enable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
-
- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
- return false;
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (engine->irq_refcount++ == 0) {
- if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
- I915_WRITE_IMR(engine,
- ~(engine->irq_enable_mask |
- GT_PARITY_ERROR(dev_priv)));
- else
- I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
- gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
-
- return true;
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
+ I915_WRITE_IMR(engine,
+ ~(engine->irq_enable_mask |
+ GT_PARITY_ERROR(dev_priv)));
+ else
+ I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
+ gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
}
static void
-gen6_ring_put_irq(struct intel_engine_cs *engine)
+gen6_ring_disable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--engine->irq_refcount == 0) {
- if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
- I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
- else
- I915_WRITE_IMR(engine, ~0);
- gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
+ I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
+ else
+ I915_WRITE_IMR(engine, ~0);
+ gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
}
-static bool
-hsw_vebox_get_irq(struct intel_engine_cs *engine)
+static void
+hsw_vebox_enable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
-
- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
- return false;
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (engine->irq_refcount++ == 0) {
- I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
- gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
-
- return true;
+ I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
+ gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
}
static void
-hsw_vebox_put_irq(struct intel_engine_cs *engine)
+hsw_vebox_disable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--engine->irq_refcount == 0) {
- I915_WRITE_IMR(engine, ~0);
- gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+ I915_WRITE_IMR(engine, ~0);
+ gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
}
-static bool
-gen8_ring_get_irq(struct intel_engine_cs *engine)
+static void
+gen8_ring_enable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
- return false;
-
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (engine->irq_refcount++ == 0) {
- if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
- I915_WRITE_IMR(engine,
- ~(engine->irq_enable_mask |
- GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
- } else {
- I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
- }
- POSTING_READ(RING_IMR(engine->mmio_base));
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
-
- return true;
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
+ I915_WRITE_IMR(engine,
+ ~(engine->irq_enable_mask |
+ GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
+ else
+ I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
+ POSTING_READ_FW(RING_IMR(engine->mmio_base));
}
static void
-gen8_ring_put_irq(struct intel_engine_cs *engine)
+gen8_ring_disable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- unsigned long flags;
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--engine->irq_refcount == 0) {
- if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
- I915_WRITE_IMR(engine,
- ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
- } else {
- I915_WRITE_IMR(engine, ~0);
- }
- POSTING_READ(RING_IMR(engine->mmio_base));
- }
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
+ I915_WRITE_IMR(engine,
+ ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
+ else
+ I915_WRITE_IMR(engine, ~0);
}
static int
@@ -2688,8 +2591,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->init_context = intel_rcs_ctx_init;
engine->add_request = gen8_render_add_request;
engine->flush = gen8_render_ring_flush;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
+ engine->irq_enable = gen8_ring_enable_irq;
+ engine->irq_disable = gen8_ring_disable_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
if (i915_semaphore_is_enabled(dev_priv)) {
WARN_ON(!dev_priv->semaphore_obj);
@@ -2703,8 +2606,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen7_render_ring_flush;
if (INTEL_INFO(dev)->gen == 6)
engine->flush = gen6_render_ring_flush;
- engine->irq_get = gen6_ring_get_irq;
- engine->irq_put = gen6_ring_put_irq;
+ engine->irq_enable = gen6_ring_enable_irq;
+ engine->irq_disable = gen6_ring_disable_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine->irq_seqno_barrier = gen6_seqno_barrier;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -2731,8 +2634,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
} else if (IS_GEN5(dev)) {
engine->add_request = i9xx_add_request;
engine->flush = gen4_render_ring_flush;
- engine->irq_get = gen5_ring_get_irq;
- engine->irq_put = gen5_ring_put_irq;
+ engine->irq_enable = gen5_ring_enable_irq;
+ engine->irq_disable = gen5_ring_disable_irq;
engine->irq_seqno_barrier = gen5_seqno_barrier;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
} else {
@@ -2742,11 +2645,11 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
else
engine->flush = gen4_render_ring_flush;
if (IS_GEN2(dev)) {
- engine->irq_get = i8xx_ring_get_irq;
- engine->irq_put = i8xx_ring_put_irq;
+ engine->irq_enable = i8xx_ring_enable_irq;
+ engine->irq_disable = i8xx_ring_disable_irq;
} else {
- engine->irq_get = i9xx_ring_get_irq;
- engine->irq_put = i9xx_ring_put_irq;
+ engine->irq_enable = i9xx_ring_enable_irq;
+ engine->irq_disable = i9xx_ring_disable_irq;
}
engine->irq_enable_mask = I915_USER_INTERRUPT;
}
@@ -2821,8 +2724,8 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (INTEL_INFO(dev)->gen >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
+ engine->irq_enable = gen8_ring_enable_irq;
+ engine->irq_disable = gen8_ring_disable_irq;
engine->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -2832,8 +2735,8 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
- engine->irq_get = gen6_ring_get_irq;
- engine->irq_put = gen6_ring_put_irq;
+ engine->irq_enable = gen6_ring_enable_irq;
+ engine->irq_disable = gen6_ring_disable_irq;
engine->dispatch_execbuffer =
gen6_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -2857,13 +2760,13 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->add_request = i9xx_add_request;
if (IS_GEN5(dev)) {
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
- engine->irq_get = gen5_ring_get_irq;
- engine->irq_put = gen5_ring_put_irq;
+ engine->irq_enable = gen5_ring_enable_irq;
+ engine->irq_disable = gen5_ring_disable_irq;
engine->irq_seqno_barrier = gen5_seqno_barrier;
} else {
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
- engine->irq_get = i9xx_ring_get_irq;
- engine->irq_put = i9xx_ring_put_irq;
+ engine->irq_enable = i9xx_ring_enable_irq;
+ engine->irq_disable = i9xx_ring_disable_irq;
}
engine->dispatch_execbuffer = i965_dispatch_execbuffer;
}
@@ -2892,8 +2795,8 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
+ engine->irq_enable = gen8_ring_enable_irq;
+ engine->irq_disable = gen8_ring_disable_irq;
engine->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -2924,8 +2827,8 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
if (INTEL_INFO(dev)->gen >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
+ engine->irq_enable = gen8_ring_enable_irq;
+ engine->irq_disable = gen8_ring_disable_irq;
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
@@ -2934,8 +2837,8 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
- engine->irq_get = gen6_ring_get_irq;
- engine->irq_put = gen6_ring_put_irq;
+ engine->irq_enable = gen6_ring_enable_irq;
+ engine->irq_disable = gen6_ring_disable_irq;
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.signal = gen6_signal;
@@ -2983,8 +2886,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
if (INTEL_INFO(dev)->gen >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
+ engine->irq_enable = gen8_ring_enable_irq;
+ engine->irq_disable = gen8_ring_disable_irq;
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
@@ -2993,8 +2896,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
- engine->irq_get = hsw_vebox_get_irq;
- engine->irq_put = hsw_vebox_put_irq;
+ engine->irq_enable = hsw_vebox_enable_irq;
+ engine->irq_disable = hsw_vebox_disable_irq;
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8abc2b83a15e..df3dac727809 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -200,11 +200,10 @@ struct intel_engine_cs {
struct intel_hw_status_page status_page;
struct i915_ctx_workarounds wa_ctx;
- unsigned irq_refcount; /* protected by dev_priv->irq_lock */
bool irq_posted;
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
- bool __must_check (*irq_get)(struct intel_engine_cs *ring);
- void (*irq_put)(struct intel_engine_cs *ring);
+ void (*irq_enable)(struct intel_engine_cs *ring);
+ void (*irq_disable)(struct intel_engine_cs *ring);
int (*init_hw)(struct intel_engine_cs *ring);
--
2.8.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 18/19] drm/i915: Simplify enabling user-interrupts with L3-remapping
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (15 preceding siblings ...)
2016-05-05 9:16 ` [PATCH 17/19] drm/i915: Move the get/put irq locking into the caller Chris Wilson
@ 2016-05-05 9:16 ` Chris Wilson
2016-05-05 9:16 ` [PATCH 19/19] drm/i915: Remove debug noise on detecting fault-injection of missed interrupts Chris Wilson
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:16 UTC (permalink / raw)
To: intel-gfx
Borrow the idea from intel_lrc.c to precompute the mask of interrupts we
wish to always enable to avoid having lots of conditionals inside the
interrupt enabling.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 +++++++++++----------------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
2 files changed, 14 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 65522c920883..72f3bf3fbf6c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1243,8 +1243,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
- if (HAS_L3_DPF(dev_priv))
- I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
+ I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
return init_workarounds_ring(engine);
}
@@ -1660,12 +1659,9 @@ gen6_ring_enable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
- I915_WRITE_IMR(engine,
- ~(engine->irq_enable_mask |
- GT_PARITY_ERROR(dev_priv)));
- else
- I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
+ I915_WRITE_IMR(engine,
+ ~(engine->irq_enable_mask |
+ engine->irq_keep_mask));
gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
}
@@ -1674,10 +1670,7 @@ gen6_ring_disable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
- I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
- else
- I915_WRITE_IMR(engine, ~0);
+ I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
}
@@ -1704,12 +1697,9 @@ gen8_ring_enable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
- I915_WRITE_IMR(engine,
- ~(engine->irq_enable_mask |
- GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
- else
- I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
+ I915_WRITE_IMR(engine,
+ ~(engine->irq_enable_mask |
+ engine->irq_keep_mask));
POSTING_READ_FW(RING_IMR(engine->mmio_base));
}
@@ -1718,11 +1708,7 @@ gen8_ring_disable_irq(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
- I915_WRITE_IMR(engine,
- ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
- else
- I915_WRITE_IMR(engine, ~0);
+ I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
}
static int
@@ -2570,6 +2556,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->hw_id = 0;
engine->mmio_base = RENDER_RING_BASE;
+ if (HAS_L3_DPF(dev_priv))
+ engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+
if (INTEL_INFO(dev)->gen >= 8) {
if (i915_semaphore_is_enabled(dev_priv)) {
obj = i915_gem_object_create(dev, 4096);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index df3dac727809..52e1b574181c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -201,7 +201,8 @@ struct intel_engine_cs {
struct i915_ctx_workarounds wa_ctx;
bool irq_posted;
- u32 irq_enable_mask; /* bitmask to enable ring interrupt */
+ u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
+ u32 irq_enable_mask;/* bitmask to enable ring interrupt */
void (*irq_enable)(struct intel_engine_cs *ring);
void (*irq_disable)(struct intel_engine_cs *ring);
@@ -298,7 +299,6 @@ struct intel_engine_cs {
unsigned int idle_lite_restore_wa;
bool disable_lite_restore_wa;
u32 ctx_desc_template;
- u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
int (*emit_request)(struct drm_i915_gem_request *request);
int (*emit_flush)(struct drm_i915_gem_request *request,
u32 invalidate_domains,
--
2.8.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 19/19] drm/i915: Remove debug noise on detecting fault-injection of missed interrupts
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
` (16 preceding siblings ...)
2016-05-05 9:16 ` [PATCH 18/19] drm/i915: Simplify enabling user-interrupts with L3-remapping Chris Wilson
@ 2016-05-05 9:16 ` Chris Wilson
17 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 9:16 UTC (permalink / raw)
To: intel-gfx
Since the tests can and do explicitly check debugfs/i915_ring_missed_irqs
for the handling of a "missed interrupt", adding it to the dmesg at INFO
is just noise. When it happens for real, we still class it as an ERROR.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_irq.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 09d5de154aee..74a86b09660e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3112,9 +3112,6 @@ static unsigned kick_waiters(struct intel_engine_cs *engine)
if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
engine->name);
- else
- DRM_INFO("Fake missed irq on %s\n",
- engine->name);
intel_engine_enable_fake_irq(engine);
}
--
2.8.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 02/19] drm/i915/execlists: Refactor common engine setup
2016-05-05 9:15 ` [PATCH 02/19] drm/i915/execlists: Refactor common engine setup Chris Wilson
@ 2016-05-05 10:18 ` Tvrtko Ursulin
2016-05-05 10:33 ` Chris Wilson
0 siblings, 1 reply; 27+ messages in thread
From: Tvrtko Ursulin @ 2016-05-05 10:18 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Hi,
On 05/05/16 10:15, Chris Wilson wrote:
> Move all of the constant assignments up front and into a common
> function. This is primarily to ensure the backpointers are set as early
> as possible for later use during initialisation.
>
> v2: Use a constant struct so that all the similar values are set
> together.
> v3: Sanitize the engine's IMR to disable any potential interrupt before
> we are ready (enabled in init_hw).
Same as before - I don't like hardware access in this code path since we
otherwise have it split into a later init_hw phase. And I don't like
engine->dev being used for intel_engine_initialized.
On retrospect, interrupt vs engine->irq_queue race is already there now,
for the render ring at least. So maybe just drop the IMR bit which would
make the patch pure refactoring and can have my R-b then.
Regards,
Tvrtko
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 180 +++++++++++++++++++++------------------
> 1 file changed, 97 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d8763524319d..8106316ce56f 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1918,8 +1918,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
> }
>
> static void
> -logical_ring_default_vfuncs(struct drm_device *dev,
> - struct intel_engine_cs *engine)
> +logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> {
> /* Default vfuncs which can be overriden by each engine. */
> engine->init_hw = gen8_init_common_ring;
> @@ -1930,7 +1929,7 @@ logical_ring_default_vfuncs(struct drm_device *dev,
> engine->emit_bb_start = gen8_emit_bb_start;
> engine->get_seqno = gen8_get_seqno;
> engine->set_seqno = gen8_set_seqno;
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(engine->dev, 0, BXT_REVID_A1)) {
> engine->irq_seqno_barrier = bxt_a_seqno_barrier;
> engine->set_seqno = bxt_a_set_seqno;
> }
> @@ -1941,6 +1940,7 @@ logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
> {
> engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
> engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
> + init_waitqueue_head(&engine->irq_queue);
> }
>
> static int
> @@ -1961,31 +1961,72 @@ lrc_setup_hws(struct intel_engine_cs *engine,
> return 0;
> }
>
> -static int
> -logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
> +static const struct logical_ring_info {
> + const char *name;
> + unsigned exec_id;
> + unsigned guc_id;
> + u32 mmio_base;
> + unsigned irq_shift;
> +} logical_rings[] = {
> + [RCS] = {
> + .name = "render ring",
> + .exec_id = I915_EXEC_RENDER,
> + .guc_id = GUC_RENDER_ENGINE,
> + .mmio_base = RENDER_RING_BASE,
> + .irq_shift = GEN8_RCS_IRQ_SHIFT,
> + },
> + [BCS] = {
> + .name = "blitter ring",
> + .exec_id = I915_EXEC_BLT,
> + .guc_id = GUC_BLITTER_ENGINE,
> + .mmio_base = BLT_RING_BASE,
> + .irq_shift = GEN8_BCS_IRQ_SHIFT,
> + },
> + [VCS] = {
> + .name = "bsd ring",
> + .exec_id = I915_EXEC_BSD,
> + .guc_id = GUC_VIDEO_ENGINE,
> + .mmio_base = GEN6_BSD_RING_BASE,
> + .irq_shift = GEN8_VCS1_IRQ_SHIFT,
> + },
> + [VCS2] = {
> + .name = "bsd2 ring",
> + .exec_id = I915_EXEC_BSD,
> + .guc_id = GUC_VIDEO_ENGINE2,
> + .mmio_base = GEN8_BSD2_RING_BASE,
> + .irq_shift = GEN8_VCS2_IRQ_SHIFT,
> + },
> + [VECS] = {
> + .name = "video enhancement ring",
> + .exec_id = I915_EXEC_VEBOX,
> + .guc_id = GUC_VIDEOENHANCE_ENGINE,
> + .mmio_base = VEBOX_RING_BASE,
> + .irq_shift = GEN8_VECS_IRQ_SHIFT,
> + },
> +};
> +
> +static struct intel_engine_cs *
> +logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
> {
> + const struct logical_ring_info *info = &logical_rings[id];
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_context *dctx = dev_priv->kernel_context;
> + struct intel_engine_cs *engine = &dev_priv->engine[id];
> enum forcewake_domains fw_domains;
> - int ret;
>
> - /* Intentionally left blank. */
> - engine->buffer = NULL;
> + engine->id = id;
> + engine->name = info->name;
> + engine->exec_id = info->exec_id;
> + engine->guc_id = info->guc_id;
> + engine->mmio_base = info->mmio_base;
>
> - engine->dev = dev;
> - INIT_LIST_HEAD(&engine->active_list);
> - INIT_LIST_HEAD(&engine->request_list);
> - i915_gem_batch_pool_init(dev, &engine->batch_pool);
> - init_waitqueue_head(&engine->irq_queue);
> + /* disable interrupts to this engine before we install ourselves */
> + I915_WRITE_IMR(engine, ~0);
> + POSTING_READ(RING_IMR(engine->mmio_base));
>
> - INIT_LIST_HEAD(&engine->buffers);
> - INIT_LIST_HEAD(&engine->execlist_queue);
> - spin_lock_init(&engine->execlist_lock);
> -
> - tasklet_init(&engine->irq_tasklet,
> - intel_lrc_irq_handler, (unsigned long)engine);
> + engine->dev = dev;
>
> - logical_ring_init_platform_invariants(engine);
> + /* Intentionally left blank. */
> + engine->buffer = NULL;
>
> fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
> RING_ELSP(engine),
> @@ -2001,6 +2042,31 @@ logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
>
> engine->fw_domains = fw_domains;
>
> + INIT_LIST_HEAD(&engine->active_list);
> + INIT_LIST_HEAD(&engine->request_list);
> + INIT_LIST_HEAD(&engine->buffers);
> + INIT_LIST_HEAD(&engine->execlist_queue);
> + spin_lock_init(&engine->execlist_lock);
> +
> + tasklet_init(&engine->irq_tasklet,
> + intel_lrc_irq_handler, (unsigned long)engine);
> +
> + logical_ring_init_platform_invariants(engine);
> + logical_ring_default_vfuncs(engine);
> + logical_ring_default_irqs(engine, info->irq_shift);
> +
> + intel_engine_init_hangcheck(engine);
> + i915_gem_batch_pool_init(engine->dev, &engine->batch_pool);
> +
> + return engine;
> +}
> +
> +static int
> +logical_ring_init(struct intel_engine_cs *engine)
> +{
> + struct intel_context *dctx = to_i915(engine->dev)->kernel_context;
> + int ret;
> +
> ret = i915_cmd_parser_init_ring(engine);
> if (ret)
> goto error;
> @@ -2033,22 +2099,12 @@ error:
>
> static int logical_render_ring_init(struct drm_device *dev)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_engine_cs *engine = &dev_priv->engine[RCS];
> + struct intel_engine_cs *engine = logical_ring_setup(dev, RCS);
> int ret;
>
> - engine->name = "render ring";
> - engine->id = RCS;
> - engine->exec_id = I915_EXEC_RENDER;
> - engine->guc_id = GUC_RENDER_ENGINE;
> - engine->mmio_base = RENDER_RING_BASE;
> -
> - logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT);
> if (HAS_L3_DPF(dev))
> engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
>
> - logical_ring_default_vfuncs(dev, engine);
> -
> /* Override some for render ring. */
> if (INTEL_INFO(dev)->gen >= 9)
> engine->init_hw = gen9_init_render_ring;
> @@ -2059,8 +2115,6 @@ static int logical_render_ring_init(struct drm_device *dev)
> engine->emit_flush = gen8_emit_flush_render;
> engine->emit_request = gen8_emit_request_render;
>
> - engine->dev = dev;
> -
> ret = intel_init_pipe_control(engine);
> if (ret)
> return ret;
> @@ -2076,7 +2130,7 @@ static int logical_render_ring_init(struct drm_device *dev)
> ret);
> }
>
> - ret = logical_ring_init(dev, engine);
> + ret = logical_ring_init(engine);
> if (ret) {
> lrc_destroy_wa_ctx_obj(engine);
> }
> @@ -2086,70 +2140,30 @@ static int logical_render_ring_init(struct drm_device *dev)
>
> static int logical_bsd_ring_init(struct drm_device *dev)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_engine_cs *engine = &dev_priv->engine[VCS];
> -
> - engine->name = "bsd ring";
> - engine->id = VCS;
> - engine->exec_id = I915_EXEC_BSD;
> - engine->guc_id = GUC_VIDEO_ENGINE;
> - engine->mmio_base = GEN6_BSD_RING_BASE;
> + struct intel_engine_cs *engine = logical_ring_setup(dev, VCS);
>
> - logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT);
> - logical_ring_default_vfuncs(dev, engine);
> -
> - return logical_ring_init(dev, engine);
> + return logical_ring_init(engine);
> }
>
> static int logical_bsd2_ring_init(struct drm_device *dev)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
> -
> - engine->name = "bsd2 ring";
> - engine->id = VCS2;
> - engine->exec_id = I915_EXEC_BSD;
> - engine->guc_id = GUC_VIDEO_ENGINE2;
> - engine->mmio_base = GEN8_BSD2_RING_BASE;
> + struct intel_engine_cs *engine = logical_ring_setup(dev, VCS2);
>
> - logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT);
> - logical_ring_default_vfuncs(dev, engine);
> -
> - return logical_ring_init(dev, engine);
> + return logical_ring_init(engine);
> }
>
> static int logical_blt_ring_init(struct drm_device *dev)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_engine_cs *engine = &dev_priv->engine[BCS];
> -
> - engine->name = "blitter ring";
> - engine->id = BCS;
> - engine->exec_id = I915_EXEC_BLT;
> - engine->guc_id = GUC_BLITTER_ENGINE;
> - engine->mmio_base = BLT_RING_BASE;
> -
> - logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT);
> - logical_ring_default_vfuncs(dev, engine);
> + struct intel_engine_cs *engine = logical_ring_setup(dev, BCS);
>
> - return logical_ring_init(dev, engine);
> + return logical_ring_init(engine);
> }
>
> static int logical_vebox_ring_init(struct drm_device *dev)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_engine_cs *engine = &dev_priv->engine[VECS];
> -
> - engine->name = "video enhancement ring";
> - engine->id = VECS;
> - engine->exec_id = I915_EXEC_VEBOX;
> - engine->guc_id = GUC_VIDEOENHANCE_ENGINE;
> - engine->mmio_base = VEBOX_RING_BASE;
> -
> - logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT);
> - logical_ring_default_vfuncs(dev, engine);
> + struct intel_engine_cs *engine = logical_ring_setup(dev, VECS);
>
> - return logical_ring_init(dev, engine);
> + return logical_ring_init(engine);
> }
>
> /**
>
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 02/19] drm/i915/execlists: Refactor common engine setup
2016-05-05 10:18 ` Tvrtko Ursulin
@ 2016-05-05 10:33 ` Chris Wilson
2016-05-05 11:17 ` Tvrtko Ursulin
0 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 10:33 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Thu, May 05, 2016 at 11:18:41AM +0100, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 05/05/16 10:15, Chris Wilson wrote:
> >Move all of the constant assignments up front and into a common
> >function. This is primarily to ensure the backpointers are set as early
> >as possible for later use during initialisation.
> >
> >v2: Use a constant struct so that all the similar values are set
> >together.
> >v3: Sanitize the engine's IMR to disable any potential interrupt before
> >we are ready (enabled in init_hw).
>
> Same as before - I don't like hardware access in this code path
> since we otherwise have it split into a later init_hw phase. And I
> don't like engine->dev being used for intel_engine_initialized.
I think you raised a good point on the last round! It is an oversight
that we have not explicitly sanitized the per-engine registers as is our
mo. This gives us the symmetry with the init_hw phase where they are
enabled.
> On retrospect, interrupt vs engine->irq_queue race is already there
> now, for the render ring at least. So maybe just drop the IMR bit
> which would make the patch pure refactoring and can have my R-b
> then.
And this closes a race with a potential interrupt pending from takeover.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 03/19] drm/i915: Store a i915 backpointer from engine, and use it
2016-05-05 9:15 ` [PATCH 03/19] drm/i915: Store a i915 backpointer from engine, and use it Chris Wilson
@ 2016-05-05 11:15 ` Tvrtko Ursulin
2016-05-05 11:26 ` Chris Wilson
2016-05-05 11:37 ` [PATCH v2] " Chris Wilson
0 siblings, 2 replies; 27+ messages in thread
From: Tvrtko Ursulin @ 2016-05-05 11:15 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 05/05/16 10:15, Chris Wilson wrote:
> text data bss dec hex filename
> 6309351 3578714 696320 10584385 a18141 vmlinux
> 6308391 3578714 696320 10583425 a17d81 vmlinux
>
> Almost 1KiB of code reduction.
I read it all - it was one tedious review. :) Found some missed
opportunities here and there, read below.
Either way,
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
But would recommend collecting some acks since it will disturb a lot of
work.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 12 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
> drivers/gpu/drm/i915/i915_dma.c | 9 +-
> drivers/gpu/drm/i915/i915_drv.c | 10 +-
> drivers/gpu/drm/i915/i915_drv.h | 35 ++--
> drivers/gpu/drm/i915/i915_gem.c | 47 ++---
> drivers/gpu/drm/i915/i915_gem_context.c | 48 ++---
> drivers/gpu/drm/i915/i915_gem_evict.c | 4 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +--
> drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +-
> drivers/gpu/drm/i915/i915_gem_shrinker.c | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 79 ++++----
> drivers/gpu/drm/i915/i915_irq.c | 80 ++++----
> drivers/gpu/drm/i915/i915_trace.h | 36 ++--
> drivers/gpu/drm/i915/intel_display.c | 49 +++--
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_lrc.c | 138 ++++++-------
> drivers/gpu/drm/i915/intel_lrc.h | 3 +-
> drivers/gpu/drm/i915/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/intel_overlay.c | 3 +-
> drivers/gpu/drm/i915/intel_pm.c | 5 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 290 ++++++++++++---------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 8 +-
> drivers/gpu/drm/i915/intel_uncore.c | 14 +-
> 26 files changed, 442 insertions(+), 499 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 69a1ba8ebdfb..35224ea30201 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -750,12 +750,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
> int cmd_table_count;
> int ret;
>
> - if (!IS_GEN7(engine->dev))
> + if (!IS_GEN7(engine->i915))
> return 0;
>
> switch (engine->id) {
> case RCS:
> - if (IS_HASWELL(engine->dev)) {
> + if (IS_HASWELL(engine->i915)) {
> cmd_tables = hsw_render_ring_cmds;
> cmd_table_count =
> ARRAY_SIZE(hsw_render_ring_cmds);
> @@ -764,7 +764,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
> cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
> }
>
> - if (IS_HASWELL(engine->dev)) {
> + if (IS_HASWELL(engine->i915)) {
> engine->reg_tables = hsw_render_reg_tables;
> engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
> } else {
> @@ -780,7 +780,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
> engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
> break;
> case BCS:
> - if (IS_HASWELL(engine->dev)) {
> + if (IS_HASWELL(engine->i915)) {
> cmd_tables = hsw_blt_ring_cmds;
> cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
> } else {
> @@ -788,7 +788,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
> cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
> }
>
> - if (IS_HASWELL(engine->dev)) {
> + if (IS_HASWELL(engine->i915)) {
> engine->reg_tables = hsw_blt_reg_tables;
> engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
> } else {
> @@ -1035,7 +1035,7 @@ bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
> if (!engine->needs_cmd_parser)
> return false;
>
> - if (!USES_PPGTT(engine->dev))
> + if (!USES_PPGTT(engine->i915))
> return false;
>
> return (i915.enable_cmd_parser == 1);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6ad008c196b5..6698957ede3f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1383,7 +1383,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
> seqno[id] = engine->get_seqno(engine);
> }
>
> - i915_get_extra_instdone(dev, instdone);
> + i915_get_extra_instdone(dev_priv, instdone);
>
> intel_runtime_pm_put(dev_priv);
>
> @@ -3165,7 +3165,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused)
> enum intel_engine_id id;
> int j, ret;
>
> - if (!i915_semaphore_is_enabled(dev)) {
> + if (!i915_semaphore_is_enabled(dev_priv)) {
> seq_puts(m, "Semaphores are disabled\n");
> return 0;
> }
> @@ -4766,7 +4766,7 @@ i915_wedged_set(void *data, u64 val)
>
> intel_runtime_pm_get(dev_priv);
>
> - i915_handle_error(dev, val,
> + i915_handle_error(dev_priv, val,
> "Manually setting wedged to %llu", val);
>
> intel_runtime_pm_put(dev_priv);
> @@ -4916,7 +4916,7 @@ i915_drop_caches_set(void *data, u64 val)
> }
>
> if (val & (DROP_RETIRE | DROP_ACTIVE))
> - i915_gem_retire_requests(dev);
> + i915_gem_retire_requests(dev_priv);
>
> if (val & DROP_BOUND)
> i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index ad7abe517700..46ac1da64a09 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -186,7 +186,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
> value = 1;
> break;
> case I915_PARAM_HAS_SEMAPHORES:
> - value = i915_semaphore_is_enabled(dev);
> + value = i915_semaphore_is_enabled(dev_priv);
> break;
> case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
> value = 1;
> @@ -970,7 +970,8 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> info->has_eu_pg ? "y" : "n");
>
> i915.enable_execlists =
> - intel_sanitize_enable_execlists(dev, i915.enable_execlists);
> + intel_sanitize_enable_execlists(dev_priv,
> + i915.enable_execlists);
>
> /*
> * i915.enable_ppgtt is read-only, so do an early pass to validate the
> @@ -979,7 +980,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> * than every time we check intel_enable_ppgtt().
> */
> i915.enable_ppgtt =
> - intel_sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
> + intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
> DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
> }
>
> @@ -1345,7 +1346,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
> * Notify a valid surface after modesetting,
> * when running inside a VM.
> */
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
>
> i915_setup_sysfs(dev);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 9fd221c97275..17aef1e92770 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -530,9 +530,9 @@ void intel_detect_pch(struct drm_device *dev)
> pci_dev_put(pch);
> }
>
> -bool i915_semaphore_is_enabled(struct drm_device *dev)
> +bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
> {
> - if (INTEL_INFO(dev)->gen < 6)
> + if (INTEL_GEN(dev_priv) < 6)
> return false;
>
> if (i915.semaphores >= 0)
> @@ -544,7 +544,7 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
>
> #ifdef CONFIG_INTEL_IOMMU
> /* Enable semaphores on SNB when IO remapping is off */
> - if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
> + if (INTEL_GEN(dev_priv) == 6 && intel_iommu_gfx_mapped)
Could use IS_GEN6.
> return false;
> #endif
>
> @@ -914,9 +914,9 @@ int i915_resume_switcheroo(struct drm_device *dev)
> * - re-init interrupt state
> * - re-init display
> */
> -int i915_reset(struct drm_device *dev)
> +int i915_reset(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_device *dev = dev_priv->dev;
> struct i915_gpu_error *error = &dev_priv->gpu_error;
> unsigned reset_counter;
> int ret;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d5496aba1cd5..c162b825273f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2754,7 +2754,8 @@ extern int i915_max_ioctl;
> extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
> extern int i915_resume_switcheroo(struct drm_device *dev);
>
> -int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt);
> +int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> + int enable_ppgtt);
>
> /* i915_dma.c */
> void __printf(3, 4)
> @@ -2778,7 +2779,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
> #endif
> extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
> extern bool intel_has_gpu_reset(struct drm_device *dev);
> -extern int i915_reset(struct drm_device *dev);
> +extern int i915_reset(struct drm_i915_private *dev_priv);
> extern int intel_guc_reset(struct drm_i915_private *dev_priv);
> extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
> extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
> @@ -2795,9 +2796,10 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
> bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
>
> /* i915_irq.c */
> -void i915_queue_hangcheck(struct drm_device *dev);
> +void i915_queue_hangcheck(struct drm_i915_private *dev_priv);
> __printf(3, 4)
> -void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> +void i915_handle_error(struct drm_i915_private *dev_priv,
> + u32 engine_mask,
> const char *fmt, ...);
>
> extern void intel_irq_init(struct drm_i915_private *dev_priv);
> @@ -2827,9 +2829,9 @@ void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
> u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
>
> void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
> -static inline bool intel_vgpu_active(struct drm_device *dev)
> +static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
> {
> - return to_i915(dev)->vgpu.active;
> + return dev_priv->vgpu.active;
> }
>
> void
> @@ -3097,13 +3099,13 @@ static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
> req->seqno);
> }
>
> -int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
> +int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno);
> int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
>
> struct drm_i915_gem_request *
> i915_gem_find_active_request(struct intel_engine_cs *engine);
>
> -bool i915_gem_retire_requests(struct drm_device *dev);
> +bool i915_gem_retire_requests(struct drm_i915_private *dev_priv);
> void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
>
> static inline u32 i915_reset_counter(struct i915_gpu_error *error)
> @@ -3350,9 +3352,9 @@ int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
> int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
>
> /* belongs in i915_gem_gtt.h */
> -static inline void i915_gem_chipset_flush(struct drm_device *dev)
> +static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
> {
> - if (INTEL_INFO(dev)->gen < 6)
> + if (INTEL_INFO(dev_priv)->gen < 6)
INTEL_GEN
> intel_gtt_chipset_flush();
> }
>
> @@ -3431,14 +3433,15 @@ static inline void i915_error_state_buf_release(
> {
> kfree(eb->buf);
> }
> -void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
> +void i915_capture_error_state(struct drm_i915_private *dev_priv,
> + u32 engine_mask,
> const char *error_msg);
> void i915_error_state_get(struct drm_device *dev,
> struct i915_error_state_file_priv *error_priv);
> void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
> void i915_destroy_error_state(struct drm_device *dev);
>
> -void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
> +void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
> const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
>
> /* i915_cmd_parser.c */
> @@ -3546,18 +3549,20 @@ extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
> extern void intel_detect_pch(struct drm_device *dev);
> extern int intel_enable_rc6(const struct drm_device *dev);
>
> -extern bool i915_semaphore_is_enabled(struct drm_device *dev);
> +extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
> int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
>
> /* overlay */
> -extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
> +extern struct intel_overlay_error_state *
> +intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
> extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
> struct intel_overlay_error_state *error);
>
> -extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
> +extern struct intel_display_error_state *
> +intel_display_capture_error_state(struct drm_i915_private *dev_priv);
> extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
> struct drm_device *dev,
> struct intel_display_error_state *error);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index a88e6c9e9516..c99d1b2c65d4 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -177,7 +177,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
> vaddr += PAGE_SIZE;
> }
>
> - i915_gem_chipset_flush(obj->base.dev);
> + i915_gem_chipset_flush(to_i915(obj->base.dev));
>
> st = kmalloc(sizeof(*st), GFP_KERNEL);
> if (st == NULL)
> @@ -347,7 +347,7 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
> }
>
> drm_clflush_virt_range(vaddr, args->size);
> - i915_gem_chipset_flush(dev);
> + i915_gem_chipset_flush(to_i915(dev));
>
> out:
> intel_fb_obj_flush(obj, false, ORIGIN_CPU);
> @@ -1006,7 +1006,7 @@ out:
> }
>
> if (needs_clflush_after)
> - i915_gem_chipset_flush(dev);
> + i915_gem_chipset_flush(to_i915(dev));
> else
> obj->cache_dirty = true;
>
> @@ -1230,8 +1230,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> struct intel_rps_client *rps)
> {
> struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = req->i915;
> const bool irq_test_in_progress =
> ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
> int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
> @@ -1429,7 +1428,7 @@ __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
> struct intel_engine_cs *engine = req->engine;
> struct drm_i915_gem_request *tmp;
>
> - lockdep_assert_held(&engine->dev->struct_mutex);
> + lockdep_assert_held(&engine->i915->dev->struct_mutex);
>
> if (list_empty(&req->list))
> return;
> @@ -2502,9 +2501,8 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
> }
>
> static int
> -i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
> +i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *engine;
> int ret;
>
> @@ -2514,7 +2512,7 @@ i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
> if (ret)
> return ret;
> }
> - i915_gem_retire_requests(dev);
> + i915_gem_retire_requests(dev_priv);
>
> /* Finally reset hw state */
> for_each_engine(engine, dev_priv)
> @@ -2534,7 +2532,7 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
> /* HWS page needs to be set less than what we
> * will inject to ring
> */
> - ret = i915_gem_init_seqno(dev, seqno - 1);
> + ret = i915_gem_init_seqno(dev_priv, seqno - 1);
> if (ret)
> return ret;
>
> @@ -2550,13 +2548,11 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
> }
>
> int
> -i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
> +i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> /* reserve 0 for non-seqno */
> if (dev_priv->next_seqno == 0) {
> - int ret = i915_gem_init_seqno(dev, 0);
> + int ret = i915_gem_init_seqno(dev_priv, 0);
> if (ret)
> return ret;
>
> @@ -2654,7 +2650,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> /* Not allowed to fail! */
> WARN(ret, "emit|add_request failed: %d!\n", ret);
>
> - i915_queue_hangcheck(engine->dev);
> + i915_queue_hangcheck(engine->i915);
>
> queue_delayed_work(dev_priv->wq,
> &dev_priv->mm.retire_work,
> @@ -2728,7 +2724,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
> struct intel_context *ctx,
> struct drm_i915_gem_request **req_out)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
> struct drm_i915_gem_request *req;
> int ret;
> @@ -2750,7 +2746,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
> if (req == NULL)
> return -ENOMEM;
>
> - ret = i915_gem_get_seqno(engine->dev, &req->seqno);
> + ret = i915_gem_get_seqno(engine->i915, &req->seqno);
We have dev_priv above.
> if (ret)
> goto err;
>
> @@ -2807,7 +2803,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
> int err;
>
> if (ctx == NULL)
> - ctx = to_i915(engine->dev)->kernel_context;
> + ctx = engine->i915->kernel_context;
> err = __i915_gem_request_alloc(engine, ctx, &req);
> return err ? ERR_PTR(err) : req;
> }
> @@ -2982,9 +2978,8 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
> }
>
> bool
> -i915_gem_retire_requests(struct drm_device *dev)
> +i915_gem_retire_requests(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *engine;
> bool idle = true;
>
> @@ -3017,7 +3012,7 @@ i915_gem_retire_work_handler(struct work_struct *work)
> /* Come back later if the device is busy... */
> idle = false;
> if (mutex_trylock(&dev->struct_mutex)) {
> - idle = i915_gem_retire_requests(dev);
> + idle = i915_gem_retire_requests(dev_priv);
> mutex_unlock(&dev->struct_mutex);
> }
> if (!idle)
> @@ -3186,7 +3181,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> if (i915_gem_request_completed(from_req, true))
> return 0;
>
> - if (!i915_semaphore_is_enabled(obj->base.dev)) {
> + if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
Maybe worth pulling up the local to function level since there are now
two lines next to each other doing the same dereferencing?
> ret = __i915_wait_request(from_req,
> i915->mm.interruptible,
> @@ -3719,7 +3714,7 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
> return;
>
> if (i915_gem_clflush_object(obj, obj->pin_display))
> - i915_gem_chipset_flush(obj->base.dev);
> + i915_gem_chipset_flush(to_i915(obj->base.dev));
>
> old_write_domain = obj->base.write_domain;
> obj->base.write_domain = 0;
> @@ -3917,7 +3912,7 @@ out:
> obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
> cpu_write_needs_clflush(obj)) {
> if (i915_gem_clflush_object(obj, true))
> - i915_gem_chipset_flush(obj->base.dev);
> + i915_gem_chipset_flush(to_i915(obj->base.dev));
> }
>
> return 0;
> @@ -4695,7 +4690,7 @@ i915_gem_suspend(struct drm_device *dev)
> if (ret)
> goto err;
>
> - i915_gem_retire_requests(dev);
> + i915_gem_retire_requests(dev_priv);
>
> i915_gem_stop_engines(dev);
> i915_gem_context_lost(dev_priv);
> @@ -4986,7 +4981,7 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
> else
> dev_priv->num_fence_regs = 8;
>
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> dev_priv->num_fence_regs =
> I915_READ(vgtif_reg(avail_rs.fence_num));
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index b1b704c2c001..2dcf18cfc809 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -99,28 +99,27 @@
> #define GEN6_CONTEXT_ALIGN (64<<10)
> #define GEN7_CONTEXT_ALIGN 4096
>
> -static size_t get_context_alignment(struct drm_device *dev)
> +static size_t get_context_alignment(struct drm_i915_private *dev_priv)
> {
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> return GEN6_CONTEXT_ALIGN;
>
> return GEN7_CONTEXT_ALIGN;
> }
>
> -static int get_context_size(struct drm_device *dev)
> +static int get_context_size(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> int ret;
> u32 reg;
>
> - switch (INTEL_INFO(dev)->gen) {
> + switch (INTEL_INFO(dev_priv)->gen) {
INTEL_GEN
> case 6:
> reg = I915_READ(CXT_SIZE);
> ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
> break;
> case 7:
> reg = I915_READ(GEN7_CXT_SIZE);
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
> ret = HSW_CXT_TOTAL_SIZE;
> else
> ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
> @@ -224,7 +223,7 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
> * Flush any pending retires to hopefully release some
> * stale contexts and try again.
> */
> - i915_gem_retire_requests(dev_priv->dev);
> + i915_gem_retire_requests(dev_priv);
> ret = ida_simple_get(&dev_priv->context_hw_ida,
> 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
> if (ret < 0)
> @@ -320,7 +319,7 @@ i915_gem_create_context(struct drm_device *dev,
> * context.
> */
> ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
> - get_context_alignment(dev), 0);
> + get_context_alignment(to_i915(dev)), 0);
> if (ret) {
> DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
> goto err_destroy;
> @@ -389,7 +388,8 @@ int i915_gem_context_init(struct drm_device *dev)
> if (WARN_ON(dev_priv->kernel_context))
> return 0;
>
> - if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
> + if (intel_vgpu_active(dev_priv) &&
> + HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
> if (!i915.enable_execlists) {
> DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
> return -EINVAL;
> @@ -404,8 +404,9 @@ int i915_gem_context_init(struct drm_device *dev)
> /* NB: intentionally left blank. We will allocate our own
> * backing objects as we need them, thank you very much */
> dev_priv->hw_context_size = 0;
> - } else if (HAS_HW_CONTEXTS(dev)) {
> - dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
> + } else if (HAS_HW_CONTEXTS(dev_priv)) {
> + dev_priv->hw_context_size =
> + round_up(get_context_size(dev_priv), 4096);
> if (dev_priv->hw_context_size > (1<<20)) {
> DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
> dev_priv->hw_context_size);
> @@ -509,12 +510,13 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
> static inline int
> mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> {
> + struct drm_i915_private *dev_priv = req->i915;
> struct intel_engine_cs *engine = req->engine;
> u32 flags = hw_flags | MI_MM_SPACE_GTT;
> const int num_rings =
> /* Use an extended w/a on ivb+ if signalling from other rings */
> - i915_semaphore_is_enabled(engine->dev) ?
> - hweight32(INTEL_INFO(engine->dev)->ring_mask) - 1 :
> + i915_semaphore_is_enabled(dev_priv) ?
> + hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 :
> 0;
> int len, ret;
>
> @@ -523,21 +525,21 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> * explicitly, so we rely on the value at ring init, stored in
> * itlb_before_ctx_switch.
> */
> - if (IS_GEN6(engine->dev)) {
> + if (IS_GEN6(dev_priv)) {
> ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
> if (ret)
> return ret;
> }
>
> /* These flags are for resource streamer on HSW+ */
> - if (IS_HASWELL(engine->dev) || INTEL_INFO(engine->dev)->gen >= 8)
> + if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
> flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
> - else if (INTEL_INFO(engine->dev)->gen < 8)
> + else if (INTEL_GEN(dev_priv) < 8)
> flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
>
>
> len = 4;
> - if (INTEL_INFO(engine->dev)->gen >= 7)
> + if (INTEL_GEN(dev_priv) >= 7)
> len += 2 + (num_rings ? 4*num_rings + 6 : 0);
>
> ret = intel_ring_begin(req, len);
> @@ -545,14 +547,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> return ret;
>
> /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
> - if (INTEL_INFO(engine->dev)->gen >= 7) {
> + if (INTEL_GEN(dev_priv) >= 7) {
> intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
> if (num_rings) {
> struct intel_engine_cs *signaller;
>
> intel_ring_emit(engine,
> MI_LOAD_REGISTER_IMM(num_rings));
> - for_each_engine(signaller, to_i915(engine->dev)) {
> + for_each_engine(signaller, dev_priv) {
> if (signaller == engine)
> continue;
>
> @@ -575,14 +577,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> */
> intel_ring_emit(engine, MI_NOOP);
>
> - if (INTEL_INFO(engine->dev)->gen >= 7) {
> + if (INTEL_GEN(dev_priv) >= 7) {
> if (num_rings) {
> struct intel_engine_cs *signaller;
> i915_reg_t last_reg = {}; /* keep gcc quiet */
>
> intel_ring_emit(engine,
> MI_LOAD_REGISTER_IMM(num_rings));
> - for_each_engine(signaller, to_i915(engine->dev)) {
> + for_each_engine(signaller, dev_priv) {
> if (signaller == engine)
> continue;
>
> @@ -673,7 +675,7 @@ needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
> if (engine->id != RCS)
> return true;
>
> - if (INTEL_INFO(engine->dev)->gen < 8)
> + if (INTEL_GEN(engine->i915) < 8)
> return true;
>
> return false;
> @@ -710,7 +712,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
>
> /* Trying to pin first makes error handling easier. */
> ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
> - get_context_alignment(engine->dev),
> + get_context_alignment(engine->i915),
> 0);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
> index ea1f8d1bd228..b144c3f5c650 100644
> --- a/drivers/gpu/drm/i915/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/i915_gem_evict.c
> @@ -154,7 +154,7 @@ none:
> if (ret)
> return ret;
>
> - i915_gem_retire_requests(dev);
> + i915_gem_retire_requests(to_i915(dev));
> goto search_again;
> }
>
> @@ -265,7 +265,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle)
> if (ret)
> return ret;
>
> - i915_gem_retire_requests(vm->dev);
> + i915_gem_retire_requests(to_i915(vm->dev));
>
> WARN_ON(!list_empty(&vm->active_list));
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index e0ee5d1ac372..a54a243ccaac 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -724,7 +724,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
> struct i915_address_space *vm;
> struct list_head ordered_vmas;
> struct list_head pinned_vmas;
> - bool has_fenced_gpu_access = INTEL_INFO(engine->dev)->gen < 4;
> + bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
> int retry;
>
> i915_gem_retire_requests_ring(engine);
> @@ -965,7 +965,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
> }
>
> if (flush_chipset)
> - i915_gem_chipset_flush(req->engine->dev);
> + i915_gem_chipset_flush(req->engine->i915);
>
> if (flush_domains & I915_GEM_DOMAIN_GTT)
> wmb();
> @@ -1119,7 +1119,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
> if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
> i915_gem_request_assign(&obj->last_fenced_req, req);
> if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
> list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
> &dev_priv->mm.fence_list);
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 364cf8236021..4e344707cebc 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -110,17 +110,19 @@ const struct i915_ggtt_view i915_ggtt_view_rotated = {
> .type = I915_GGTT_VIEW_ROTATED,
> };
>
> -int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
> +int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> + int enable_ppgtt)
> {
> bool has_aliasing_ppgtt;
> bool has_full_ppgtt;
> bool has_full_48bit_ppgtt;
>
> - has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
> - has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
> - has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
> + has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6;
> + has_full_ppgtt = INTEL_GEN(dev_priv) >= 7;
> + has_full_48bit_ppgtt =
> + IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;
>
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> has_full_ppgtt = false; /* emulation is too hard */
>
> if (!has_aliasing_ppgtt)
> @@ -130,7 +132,7 @@ int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
> * We don't allow disabling PPGTT for gen9+ as it's a requirement for
> * execlists, the sole mechanism available to submit work.
> */
> - if (enable_ppgtt == 0 && INTEL_INFO(dev)->gen < 9)
> + if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
> return 0;
>
> if (enable_ppgtt == 1)
> @@ -144,19 +146,19 @@ int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>
> #ifdef CONFIG_INTEL_IOMMU
> /* Disable ppgtt on SNB if VT-d is on. */
> - if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
> + if (INTEL_GEN(dev_priv) == 6 && intel_iommu_gfx_mapped) {
IS_GEN6 ?
> DRM_INFO("Disabling PPGTT because VT-d is on\n");
> return 0;
> }
> #endif
>
> /* Early VLV doesn't have this */
> - if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
> + if (IS_VALLEYVIEW(dev_priv) && dev_priv->dev->pdev->revision < 0xb) {
> DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
> return 0;
> }
>
> - if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
> + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists)
> return has_full_48bit_ppgtt ? 3 : 2;
> else
> return has_aliasing_ppgtt ? 1 : 0;
> @@ -994,7 +996,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
> {
> struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>
> - if (intel_vgpu_active(vm->dev))
> + if (intel_vgpu_active(to_i915(vm->dev)))
> gen8_ppgtt_notify_vgt(ppgtt, false);
>
> if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
> @@ -1545,14 +1547,14 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> 0, 0,
> GEN8_PML4E_SHIFT);
>
> - if (intel_vgpu_active(ppgtt->base.dev)) {
> + if (intel_vgpu_active(to_i915(ppgtt->base.dev))) {
> ret = gen8_preallocate_top_level_pdps(ppgtt);
> if (ret)
> goto free_scratch;
> }
> }
>
> - if (intel_vgpu_active(ppgtt->base.dev))
> + if (intel_vgpu_active(to_i915(ppgtt->base.dev)))
> gen8_ppgtt_notify_vgt(ppgtt, true);
>
> return 0;
> @@ -2080,7 +2082,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> } else
> BUG();
>
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> ppgtt->switch_mm = vgpu_mm_switch;
>
> ret = gen6_ppgtt_alloc(ppgtt);
> @@ -2729,7 +2731,7 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
> i915_address_space_init(&ggtt->base, dev_priv);
> ggtt->base.total += PAGE_SIZE;
>
> - if (intel_vgpu_active(dev)) {
> + if (intel_vgpu_active(dev_priv)) {
> ret = intel_vgt_balloon(dev);
> if (ret)
> return ret;
> @@ -2833,7 +2835,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
> i915_gem_cleanup_stolen(dev);
>
> if (drm_mm_initialized(&ggtt->base.mm)) {
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> intel_vgt_deballoon();
>
> drm_mm_takedown(&ggtt->base.mm);
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index 423cf5144bcb..7c93327b70fe 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -29,7 +29,7 @@
> #include "intel_renderstate.h"
>
> static const struct intel_renderstate_rodata *
> -render_state_get_rodata(struct drm_device *dev, const int gen)
> +render_state_get_rodata(const int gen)
> {
> switch (gen) {
> case 6:
> @@ -45,19 +45,20 @@ render_state_get_rodata(struct drm_device *dev, const int gen)
> return NULL;
> }
>
> -static int render_state_init(struct render_state *so, struct drm_device *dev)
> +static int render_state_init(struct render_state *so,
> + struct drm_i915_private *dev_priv)
> {
> int ret;
>
> - so->gen = INTEL_INFO(dev)->gen;
> - so->rodata = render_state_get_rodata(dev, so->gen);
> + so->gen = INTEL_GEN(dev_priv);
> + so->rodata = render_state_get_rodata(so->gen);
> if (so->rodata == NULL)
> return 0;
>
> if (so->rodata->batch_items * 4 > 4096)
> return -EINVAL;
>
> - so->obj = i915_gem_object_create(dev, 4096);
> + so->obj = i915_gem_object_create(dev_priv->dev, 4096);
> if (IS_ERR(so->obj))
> return PTR_ERR(so->obj);
>
> @@ -177,7 +178,7 @@ int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
> if (WARN_ON(engine->id != RCS))
> return -ENOENT;
>
> - ret = render_state_init(so, engine->dev);
> + ret = render_state_init(so, engine->i915);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
> index 79004f356174..538c30499848 100644
> --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
> +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
> @@ -131,7 +131,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
> unsigned long count = 0;
>
> trace_i915_gem_shrink(dev_priv, target, flags);
> - i915_gem_retire_requests(dev_priv->dev);
> + i915_gem_retire_requests(dev_priv);
>
> /*
> * Unbinding of objects will require HW access; Let us not wake the
> @@ -209,7 +209,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
> if (flags & I915_SHRINK_BOUND)
> intel_runtime_pm_put(dev_priv);
>
> - i915_gem_retire_requests(dev_priv->dev);
> + i915_gem_retire_requests(dev_priv);
>
> return count;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 89725c9efc25..22d926839b68 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -824,19 +824,18 @@ static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
> return error_code;
> }
>
> -static void i915_gem_record_fences(struct drm_device *dev,
> +static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
> struct drm_i915_error_state *error)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> int i;
>
> - if (IS_GEN3(dev) || IS_GEN2(dev)) {
> + if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
> for (i = 0; i < dev_priv->num_fence_regs; i++)
> error->fence[i] = I915_READ(FENCE_REG(i));
> - } else if (IS_GEN5(dev) || IS_GEN4(dev)) {
> + } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
> for (i = 0; i < dev_priv->num_fence_regs; i++)
> error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> - } else if (INTEL_INFO(dev)->gen >= 6) {
> + } else if (INTEL_GEN(dev_priv) >= 6) {
> for (i = 0; i < dev_priv->num_fence_regs; i++)
> error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> }
> @@ -851,7 +850,7 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
> struct intel_engine_cs *to;
> enum intel_engine_id id;
>
> - if (!i915_semaphore_is_enabled(dev_priv->dev))
> + if (!i915_semaphore_is_enabled(dev_priv))
> return;
>
> if (!error->semaphore_obj)
> @@ -893,31 +892,29 @@ static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void i915_record_ring_state(struct drm_device *dev,
> +static void i915_record_ring_state(struct drm_i915_private *dev_priv,
> struct drm_i915_error_state *error,
> struct intel_engine_cs *engine,
> struct drm_i915_error_ring *ering)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (INTEL_INFO(dev)->gen >= 6) {
> + if (INTEL_GEN(dev_priv) >= 6) {
> ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
> ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
> - if (INTEL_INFO(dev)->gen >= 8)
> + if (INTEL_GEN(dev_priv) >= 8)
> gen8_record_semaphore_state(dev_priv, error, engine,
> ering);
> else
> gen6_record_semaphore_state(dev_priv, engine, ering);
> }
>
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
> ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
> ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
> ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
> ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
> ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
> ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
> }
> @@ -939,10 +936,10 @@ static void i915_record_ring_state(struct drm_device *dev,
> ering->tail = I915_READ_TAIL(engine);
> ering->ctl = I915_READ_CTL(engine);
>
> - if (I915_NEED_GFX_HWS(dev)) {
> + if (I915_NEED_GFX_HWS(dev_priv)) {
> i915_reg_t mmio;
>
> - if (IS_GEN7(dev)) {
> + if (IS_GEN7(dev_priv)) {
> switch (engine->id) {
> default:
> case RCS:
> @@ -958,7 +955,7 @@ static void i915_record_ring_state(struct drm_device *dev,
> mmio = VEBOX_HWS_PGA_GEN7;
> break;
> }
> - } else if (IS_GEN6(engine->dev)) {
> + } else if (IS_GEN6(engine->i915)) {
> mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
> } else {
> /* XXX: gen8 returns to sanity */
> @@ -971,18 +968,18 @@ static void i915_record_ring_state(struct drm_device *dev,
> ering->hangcheck_score = engine->hangcheck.score;
> ering->hangcheck_action = engine->hangcheck.action;
>
> - if (USES_PPGTT(dev)) {
> + if (USES_PPGTT(dev_priv)) {
> int i;
>
> ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> ering->vm_info.pp_dir_base =
> I915_READ(RING_PP_DIR_BASE_READ(engine));
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> ering->vm_info.pp_dir_base =
> I915_READ(RING_PP_DIR_BASE(engine));
> - else if (INTEL_INFO(dev)->gen >= 8)
> + else if (INTEL_GEN(dev_priv) >= 8)
> for (i = 0; i < 4; i++) {
> ering->vm_info.pdp[i] =
> I915_READ(GEN8_RING_PDP_UDW(engine, i));
> @@ -998,7 +995,7 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
> struct drm_i915_error_state *error,
> struct drm_i915_error_ring *ering)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct drm_i915_gem_object *obj;
>
> /* Currently render ring is the only HW context user */
> @@ -1016,10 +1013,9 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
> }
> }
>
> -static void i915_gem_record_rings(struct drm_device *dev,
> +static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> struct drm_i915_error_state *error)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> struct i915_ggtt *ggtt = &dev_priv->ggtt;
> struct drm_i915_gem_request *request;
> int i, count;
> @@ -1030,12 +1026,12 @@ static void i915_gem_record_rings(struct drm_device *dev,
>
> error->ring[i].pid = -1;
>
> - if (engine->dev == NULL)
> + if (engine->i915 == NULL)
intel_engine_initialized ?
> continue;
>
> error->ring[i].valid = true;
>
> - i915_record_ring_state(dev, error, engine, &error->ring[i]);
> + i915_record_ring_state(dev_priv, error, engine, &error->ring[i]);
>
> request = i915_gem_find_active_request(engine);
> if (request) {
> @@ -1301,15 +1297,14 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> error->eir = I915_READ(EIR);
> error->pgtbl_er = I915_READ(PGTBL_ER);
>
> - i915_get_extra_instdone(dev, error->extra_instdone);
> + i915_get_extra_instdone(dev_priv, error->extra_instdone);
> }
>
> -static void i915_error_capture_msg(struct drm_device *dev,
> +static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
> struct drm_i915_error_state *error,
> u32 engine_mask,
> const char *error_msg)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> u32 ecode;
> int ring_id = -1, len;
>
> @@ -1317,7 +1312,7 @@ static void i915_error_capture_msg(struct drm_device *dev,
>
> len = scnprintf(error->error_msg, sizeof(error->error_msg),
> "GPU HANG: ecode %d:%d:0x%08x",
> - INTEL_INFO(dev)->gen, ring_id, ecode);
> + INTEL_INFO(dev_priv)->gen, ring_id, ecode);
INTEL_GEN
>
> if (ring_id != -1 && error->ring[ring_id].pid != -1)
> len += scnprintf(error->error_msg + len,
> @@ -1352,11 +1347,11 @@ static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
> * out a structure which becomes available in debugfs for user level tools
> * to pick up.
> */
> -void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
> +void i915_capture_error_state(struct drm_i915_private *dev_priv,
> + u32 engine_mask,
> const char *error_msg)
> {
> static bool warned;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct drm_i915_error_state *error;
> unsigned long flags;
>
> @@ -1372,15 +1367,15 @@ void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
> i915_capture_gen_state(dev_priv, error);
> i915_capture_reg_state(dev_priv, error);
> i915_gem_capture_buffers(dev_priv, error);
> - i915_gem_record_fences(dev, error);
> - i915_gem_record_rings(dev, error);
> + i915_gem_record_fences(dev_priv, error);
> + i915_gem_record_rings(dev_priv, error);
>
> do_gettimeofday(&error->time);
>
> - error->overlay = intel_overlay_capture_error_state(dev);
> - error->display = intel_display_capture_error_state(dev);
> + error->overlay = intel_overlay_capture_error_state(dev_priv);
> + error->display = intel_display_capture_error_state(dev_priv);
>
> - i915_error_capture_msg(dev, error, engine_mask, error_msg);
> + i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
> DRM_INFO("%s\n", error->error_msg);
>
> spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
> @@ -1400,7 +1395,7 @@ void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
> DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
> DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
> DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
> - DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
> + DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev_priv->dev->primary->index);
> warned = true;
> }
> }
> @@ -1450,17 +1445,17 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
> }
>
> /* NB: please notice the memset */
> -void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
> +void i915_get_extra_instdone(struct drm_i915_private *dev_priv,
> + uint32_t *instdone)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
>
> - if (IS_GEN2(dev) || IS_GEN3(dev))
> + if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
> instdone[0] = I915_READ(GEN2_INSTDONE);
> - else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
> + else if (IS_GEN4(dev_priv) || IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) {
> instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
> instdone[1] = I915_READ(GEN4_INSTDONE1);
> - } else if (INTEL_INFO(dev)->gen >= 7) {
> + } else if (INTEL_INFO(dev_priv)->gen >= 7) {
INTEL_GEN
> instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
> instdone[1] = I915_READ(GEN7_SC_INSTDONE);
> instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2f6fd33c07ba..8864ee19154f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2555,15 +2555,15 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
> * Fire an error uevent so userspace can see that a hang or error
> * was detected.
> */
> -static void i915_reset_and_wakeup(struct drm_device *dev)
> +static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
> char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
> char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
> char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
> int ret;
>
> - kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
> + kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
>
> /*
> * Note that there's only one work item which does gpu resets, so we
> @@ -2577,8 +2577,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> */
> if (i915_reset_in_progress(&dev_priv->gpu_error)) {
> DRM_DEBUG_DRIVER("resetting chip\n");
> - kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
> - reset_event);
> + kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
>
> /*
> * In most cases it's guaranteed that we get here with an RPM
> @@ -2589,7 +2588,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> */
> intel_runtime_pm_get(dev_priv);
>
> - intel_prepare_reset(dev);
> + intel_prepare_reset(dev_priv);
>
> /*
> * All state reset _must_ be completed before we update the
> @@ -2597,14 +2596,14 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> * pending state and not properly drop locks, resulting in
> * deadlocks with the reset work.
> */
> - ret = i915_reset(dev);
> + ret = i915_reset(dev_priv);
>
> - intel_finish_reset(dev);
> + intel_finish_reset(dev_priv);
>
> intel_runtime_pm_put(dev_priv);
>
> if (ret == 0)
> - kobject_uevent_env(&dev->primary->kdev->kobj,
> + kobject_uevent_env(kobj,
> KOBJ_CHANGE, reset_done_event);
>
> /*
> @@ -2615,9 +2614,8 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> }
> }
>
> -static void i915_report_and_clear_eir(struct drm_device *dev)
> +static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> uint32_t instdone[I915_NUM_INSTDONE_REG];
> u32 eir = I915_READ(EIR);
> int pipe, i;
> @@ -2627,9 +2625,9 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
>
> pr_err("render error detected, EIR: 0x%08x\n", eir);
>
> - i915_get_extra_instdone(dev, instdone);
> + i915_get_extra_instdone(dev_priv, instdone);
>
> - if (IS_G4X(dev)) {
> + if (IS_G4X(dev_priv)) {
> if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
> u32 ipeir = I915_READ(IPEIR_I965);
>
> @@ -2651,7 +2649,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
> }
> }
>
> - if (!IS_GEN2(dev)) {
> + if (!IS_GEN2(dev_priv)) {
> if (eir & I915_ERROR_PAGE_TABLE) {
> u32 pgtbl_err = I915_READ(PGTBL_ER);
> pr_err("page table error\n");
> @@ -2673,7 +2671,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
> pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
> for (i = 0; i < ARRAY_SIZE(instdone); i++)
> pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
> - if (INTEL_INFO(dev)->gen < 4) {
> + if (INTEL_GEN(dev_priv) < 4) {
> u32 ipeir = I915_READ(IPEIR);
>
> pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
> @@ -2717,10 +2715,10 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
> * so userspace knows something bad happened (should trigger collection
> * of a ring dump etc.).
> */
> -void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> +void i915_handle_error(struct drm_i915_private *dev_priv,
> + u32 engine_mask,
> const char *fmt, ...)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> va_list args;
> char error_msg[80];
>
> @@ -2728,8 +2726,8 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> vscnprintf(error_msg, sizeof(error_msg), fmt, args);
> va_end(args);
>
> - i915_capture_error_state(dev, engine_mask, error_msg);
> - i915_report_and_clear_eir(dev);
> + i915_capture_error_state(dev_priv, engine_mask, error_msg);
> + i915_report_and_clear_eir(dev_priv);
>
> if (engine_mask) {
> atomic_or(I915_RESET_IN_PROGRESS_FLAG,
> @@ -2751,7 +2749,7 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> i915_error_wake_up(dev_priv, false);
> }
>
> - i915_reset_and_wakeup(dev);
> + i915_reset_and_wakeup(dev_priv);
> }
>
> /* Called from drm generic code, passed 'crtc' which
> @@ -2869,9 +2867,9 @@ ring_idle(struct intel_engine_cs *engine, u32 seqno)
> }
>
> static bool
> -ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
> +ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr)
> {
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> return (ipehr >> 23) == 0x1c;
> } else {
> ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
> @@ -2884,10 +2882,10 @@ static struct intel_engine_cs *
> semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
> u64 offset)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct intel_engine_cs *signaller;
>
> - if (INTEL_INFO(dev_priv)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> for_each_engine(signaller, dev_priv) {
> if (engine == signaller)
> continue;
> @@ -2916,7 +2914,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
> static struct intel_engine_cs *
> semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u32 cmd, ipehr, head;
> u64 offset = 0;
> int i, backwards;
> @@ -2942,7 +2940,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
> return NULL;
>
> ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
> - if (!ipehr_is_semaphore_wait(engine->dev, ipehr))
> + if (!ipehr_is_semaphore_wait(engine->i915, ipehr))
> return NULL;
>
> /*
> @@ -2954,7 +2952,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
> * ringbuffer itself.
> */
> head = I915_READ_HEAD(engine) & HEAD_ADDR;
> - backwards = (INTEL_INFO(engine->dev)->gen >= 8) ? 5 : 4;
> + backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
>
> for (i = backwards; i; --i) {
> /*
> @@ -2976,7 +2974,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
> return NULL;
>
> *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
> - if (INTEL_INFO(engine->dev)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> offset = ioread32(engine->buffer->virtual_start + head + 12);
> offset <<= 32;
> offset = ioread32(engine->buffer->virtual_start + head + 8);
> @@ -2986,7 +2984,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
>
> static int semaphore_passed(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct intel_engine_cs *signaller;
> u32 seqno;
>
> @@ -3028,7 +3026,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
> if (engine->id != RCS)
> return true;
>
> - i915_get_extra_instdone(engine->dev, instdone);
> + i915_get_extra_instdone(engine->i915, instdone);
>
> /* There might be unstable subunit states even when
> * actual head is not moving. Filter out the unstable ones by
> @@ -3069,8 +3067,7 @@ head_stuck(struct intel_engine_cs *engine, u64 acthd)
> static enum intel_ring_hangcheck_action
> ring_stuck(struct intel_engine_cs *engine, u64 acthd)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> enum intel_ring_hangcheck_action ha;
> u32 tmp;
>
> @@ -3078,7 +3075,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
> if (ha != HANGCHECK_HUNG)
> return ha;
>
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> return HANGCHECK_HUNG;
>
> /* Is the chip hanging on a WAIT_FOR_EVENT?
> @@ -3088,19 +3085,19 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
> */
> tmp = I915_READ_CTL(engine);
> if (tmp & RING_WAIT) {
> - i915_handle_error(dev, 0,
> + i915_handle_error(dev_priv, 0,
> "Kicking stuck wait on %s",
> engine->name);
> I915_WRITE_CTL(engine, tmp);
> return HANGCHECK_KICK;
> }
>
> - if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
> + if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
> switch (semaphore_passed(engine)) {
> default:
> return HANGCHECK_HUNG;
> case 1:
> - i915_handle_error(dev, 0,
> + i915_handle_error(dev_priv, 0,
> "Kicking stuck semaphore on %s",
> engine->name);
> I915_WRITE_CTL(engine, tmp);
> @@ -3115,7 +3112,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
>
> static unsigned kick_waiters(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *i915 = to_i915(engine->dev);
> + struct drm_i915_private *i915 = engine->i915;
> unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
>
> if (engine->hangcheck.user_interrupts == user_interrupts &&
> @@ -3144,7 +3141,6 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> struct drm_i915_private *dev_priv =
> container_of(work, typeof(*dev_priv),
> gpu_error.hangcheck_work.work);
> - struct drm_device *dev = dev_priv->dev;
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> int busy_count = 0, rings_hung = 0;
> @@ -3272,22 +3268,22 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> }
>
> if (rings_hung) {
> - i915_handle_error(dev, rings_hung, "Engine(s) hung");
> + i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
> goto out;
> }
>
> if (busy_count)
> /* Reset timer case chip hangs without another request
> * being added */
> - i915_queue_hangcheck(dev);
> + i915_queue_hangcheck(dev_priv);
>
> out:
> ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
> }
>
> -void i915_queue_hangcheck(struct drm_device *dev)
> +void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
> {
> - struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
> + struct i915_gpu_error *e = &dev_priv->gpu_error;
>
> if (!i915.enable_hangcheck)
> return;
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index dc0def210097..20b2e4039792 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -462,7 +462,7 @@ TRACE_EVENT(i915_gem_ring_sync_to,
> ),
>
> TP_fast_assign(
> - __entry->dev = from->dev->primary->index;
> + __entry->dev = from->i915->dev->primary->index;
> __entry->sync_from = from->id;
> __entry->sync_to = to_req->engine->id;
> __entry->seqno = i915_gem_request_get_seqno(req);
> @@ -486,13 +486,11 @@ TRACE_EVENT(i915_gem_ring_dispatch,
> ),
>
> TP_fast_assign(
> - struct intel_engine_cs *engine =
> - i915_gem_request_get_engine(req);
> - __entry->dev = engine->dev->primary->index;
> - __entry->ring = engine->id;
> - __entry->seqno = i915_gem_request_get_seqno(req);
> + __entry->dev = req->i915->dev->primary->index;
> + __entry->ring = req->engine->id;
> + __entry->seqno = req->seqno;
> __entry->flags = flags;
> - i915_trace_irq_get(engine, req);
> + i915_trace_irq_get(req->engine, req);
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u, flags=%x",
> @@ -511,7 +509,7 @@ TRACE_EVENT(i915_gem_ring_flush,
> ),
>
> TP_fast_assign(
> - __entry->dev = req->engine->dev->primary->index;
> + __entry->dev = req->i915->dev->primary->index;
> __entry->ring = req->engine->id;
> __entry->invalidate = invalidate;
> __entry->flush = flush;
> @@ -533,11 +531,9 @@ DECLARE_EVENT_CLASS(i915_gem_request,
> ),
>
> TP_fast_assign(
> - struct intel_engine_cs *engine =
> - i915_gem_request_get_engine(req);
> - __entry->dev = engine->dev->primary->index;
> - __entry->ring = engine->id;
> - __entry->seqno = i915_gem_request_get_seqno(req);
> + __entry->dev = req->i915->dev->primary->index;
> + __entry->ring = req->engine->id;
> + __entry->seqno = req->seqno;
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u",
> @@ -560,7 +556,7 @@ TRACE_EVENT(i915_gem_request_notify,
> ),
>
> TP_fast_assign(
> - __entry->dev = engine->dev->primary->index;
> + __entry->dev = engine->i915->dev->primary->index;
> __entry->ring = engine->id;
> __entry->seqno = engine->get_seqno(engine);
> ),
> @@ -597,13 +593,11 @@ TRACE_EVENT(i915_gem_request_wait_begin,
> * less desirable.
> */
> TP_fast_assign(
> - struct intel_engine_cs *engine =
> - i915_gem_request_get_engine(req);
> - __entry->dev = engine->dev->primary->index;
> - __entry->ring = engine->id;
> - __entry->seqno = i915_gem_request_get_seqno(req);
> + __entry->dev = req->i915->dev->primary->index;
> + __entry->ring = req->engine->id;
> + __entry->seqno = req->seqno;
> __entry->blocking =
> - mutex_is_locked(&engine->dev->struct_mutex);
> + mutex_is_locked(&req->i915->dev->struct_mutex);
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u, blocking=%s",
> @@ -792,7 +786,7 @@ TRACE_EVENT(switch_mm,
> __entry->ring = engine->id;
> __entry->to = to;
> __entry->vm = to->ppgtt? &to->ppgtt->base : NULL;
> - __entry->dev = engine->dev->primary->index;
> + __entry->dev = engine->i915->dev->primary->index;
> ),
>
> TP_printk("dev=%u, ring=%u, ctx=%p, ctx_vm=%p",
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 45c218db86be..6e2e2b98d323 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3144,41 +3144,39 @@ static void intel_update_primary_planes(struct drm_device *dev)
> }
> }
>
> -void intel_prepare_reset(struct drm_device *dev)
> +void intel_prepare_reset(struct drm_i915_private *dev_priv)
> {
> /* no reset support for gen2 */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> return;
>
> /* reset doesn't touch the display */
> - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
> + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> return;
>
> - drm_modeset_lock_all(dev);
> + drm_modeset_lock_all(dev_priv->dev);
> /*
> * Disabling the crtcs gracefully seems nicer. Also the
> * g33 docs say we should at least disable all the planes.
> */
> - intel_display_suspend(dev);
> + intel_display_suspend(dev_priv->dev);
> }
>
> -void intel_finish_reset(struct drm_device *dev)
> +void intel_finish_reset(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> -
> /*
> * Flips in the rings will be nuked by the reset,
> * so complete all pending flips so that user space
> * will get its events and not get stuck.
> */
> - intel_complete_page_flips(dev);
> + intel_complete_page_flips(dev_priv->dev);
>
> /* no reset support for gen2 */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> return;
>
> /* reset doesn't touch the display */
> - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
> + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> /*
> * Flips in the rings have been nuked by the reset,
> * so update the base address of all primary
> @@ -3188,7 +3186,7 @@ void intel_finish_reset(struct drm_device *dev)
> * FIXME: Atomic will make this obsolete since we won't schedule
> * CS-based flips (which might get lost in gpu resets) any more.
> */
> - intel_update_primary_planes(dev);
> + intel_update_primary_planes(dev_priv->dev);
> return;
> }
>
> @@ -3199,18 +3197,18 @@ void intel_finish_reset(struct drm_device *dev)
> intel_runtime_pm_disable_interrupts(dev_priv);
> intel_runtime_pm_enable_interrupts(dev_priv);
>
> - intel_modeset_init_hw(dev);
> + intel_modeset_init_hw(dev_priv->dev);
>
> spin_lock_irq(&dev_priv->irq_lock);
> if (dev_priv->display.hpd_irq_setup)
> - dev_priv->display.hpd_irq_setup(dev);
> + dev_priv->display.hpd_irq_setup(dev_priv->dev);
> spin_unlock_irq(&dev_priv->irq_lock);
>
> - intel_display_resume(dev);
> + intel_display_resume(dev_priv->dev);
>
> intel_hpd_init(dev_priv);
>
> - drm_modeset_unlock_all(dev);
> + drm_modeset_unlock_all(dev_priv->dev);
> }
>
> static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
> @@ -11256,7 +11254,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
> if (engine == NULL)
> return true;
>
> - if (INTEL_INFO(engine->dev)->gen < 5)
> + if (INTEL_GEN(engine->i915) < 5)
> return false;
>
> if (i915.use_mmio_flip < 0)
> @@ -16185,9 +16183,8 @@ struct intel_display_error_state {
> };
>
> struct intel_display_error_state *
> -intel_display_capture_error_state(struct drm_device *dev)
> +intel_display_capture_error_state(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_display_error_state *error;
> int transcoders[] = {
> TRANSCODER_A,
> @@ -16197,14 +16194,14 @@ intel_display_capture_error_state(struct drm_device *dev)
> };
> int i;
>
> - if (INTEL_INFO(dev)->num_pipes == 0)
> + if (INTEL_INFO(dev_priv)->num_pipes == 0)
> return NULL;
>
> error = kzalloc(sizeof(*error), GFP_ATOMIC);
> if (error == NULL)
> return NULL;
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
>
> for_each_pipe(dev_priv, i) {
> @@ -16220,25 +16217,25 @@ intel_display_capture_error_state(struct drm_device *dev)
>
> error->plane[i].control = I915_READ(DSPCNTR(i));
> error->plane[i].stride = I915_READ(DSPSTRIDE(i));
> - if (INTEL_INFO(dev)->gen <= 3) {
> + if (INTEL_GEN(dev_priv) <= 3) {
> error->plane[i].size = I915_READ(DSPSIZE(i));
> error->plane[i].pos = I915_READ(DSPPOS(i));
> }
> - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
> + if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
> error->plane[i].addr = I915_READ(DSPADDR(i));
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> error->plane[i].surface = I915_READ(DSPSURF(i));
> error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
> }
>
> error->pipe[i].source = I915_READ(PIPESRC(i));
>
> - if (HAS_GMCH_DISPLAY(dev))
> + if (HAS_GMCH_DISPLAY(dev_priv))
> error->pipe[i].stat = I915_READ(PIPESTAT(i));
> }
>
> /* Note: this does not include DSI transcoders. */
> - error->num_transcoders = INTEL_INFO(dev)->num_pipes;
> + error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
> if (HAS_DDI(dev_priv))
> error->num_transcoders++; /* Account for eDP. */
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 51058522741a..66de61669884 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1226,8 +1226,8 @@ u32 intel_compute_tile_offset(int *x, int *y,
> const struct drm_framebuffer *fb, int plane,
> unsigned int pitch,
> unsigned int rotation);
> -void intel_prepare_reset(struct drm_device *dev);
> -void intel_finish_reset(struct drm_device *dev);
> +void intel_prepare_reset(struct drm_i915_private *dev_priv);
> +void intel_finish_reset(struct drm_i915_private *dev_priv);
> void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> void broxton_init_cdclk(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index d5a7cfec589b..4a527d3cf026 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -827,7 +827,7 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc)
> bool enable_by_default = IS_HASWELL(dev_priv) ||
> IS_BROADWELL(dev_priv);
>
> - if (intel_vgpu_active(dev_priv->dev)) {
> + if (intel_vgpu_active(dev_priv)) {
> fbc->no_fbc_reason = "VGPU is active";
> return false;
> }
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 8106316ce56f..e76280d5cdff 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -246,21 +246,22 @@ static int intel_lr_context_pin(struct intel_context *ctx,
> *
> * Return: 1 if Execlists is supported and has to be enabled.
> */
> -int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
> +int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
> {
> /* On platforms with execlist available, vGPU will only
> * support execlist mode, no ring buffer mode.
> */
> - if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
> + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
> return 1;
>
> - if (INTEL_INFO(dev)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return 1;
>
> if (enable_execlists == 0)
> return 0;
>
> - if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
> + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
> + USES_PPGTT(dev_priv) &&
> i915.use_mmio_flip >= 0)
> return 1;
>
> @@ -270,19 +271,19 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists
> static void
> logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> - if (IS_GEN8(dev) || IS_GEN9(dev))
> + if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
> engine->idle_lite_restore_wa = ~0;
>
> - engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
> + engine->disable_lite_restore_wa = (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
> (engine->id == VCS || engine->id == VCS2);
>
> engine->ctx_desc_template = GEN8_CTX_VALID;
> - engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
> + engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
> GEN8_CTX_ADDRESSING_MODE_SHIFT;
> - if (IS_GEN8(dev))
> + if (IS_GEN8(dev_priv))
> engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
> engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
>
> @@ -342,8 +343,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
> {
>
> struct intel_engine_cs *engine = rq0->engine;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = rq0->i915;
> uint64_t desc[2];
>
> if (rq1) {
> @@ -425,7 +425,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
> * If irqs are not active generate a warning as batches that finish
> * without the irqs may get lost and a GPU Hang may occur.
> */
> - WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
> + WARN_ON(!intel_irqs_enabled(engine->i915));
>
> /* Try to read in pairs */
> list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
> @@ -497,7 +497,7 @@ static u32
> get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
> u32 *context_id)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u32 status;
>
> read_pointer %= GEN8_CSB_ENTRIES;
> @@ -523,7 +523,7 @@ get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
> static void intel_lrc_irq_handler(unsigned long data)
> {
> struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u32 status_pointer;
> unsigned int read_pointer, write_pointer;
> u32 csb[GEN8_CSB_ENTRIES][2];
> @@ -884,7 +884,7 @@ void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
> struct drm_i915_gem_request *req, *tmp;
> LIST_HEAD(cancel_list);
>
> - WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
> + WARN_ON(!mutex_is_locked(&engine->i915->dev->struct_mutex));
>
> spin_lock_bh(&engine->execlist_lock);
> list_replace_init(&engine->execlist_queue, &cancel_list);
> @@ -898,7 +898,7 @@ void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
>
> void intel_logical_ring_stop(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
>
> if (!intel_engine_initialized(engine))
> @@ -964,7 +964,7 @@ static int intel_lr_context_pin(struct intel_context *ctx,
> lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
>
> ringbuf = ctx->engine[engine->id].ringbuf;
> - ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
> + ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
> if (ret)
> goto unpin_map;
>
> @@ -1019,9 +1019,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> int ret, i;
> struct intel_engine_cs *engine = req->engine;
> struct intel_ringbuffer *ringbuf = req->ringbuf;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct i915_workarounds *w = &dev_priv->workarounds;
> + struct i915_workarounds *w = &req->i915->workarounds;
>
> if (w->count == 0)
> return 0;
> @@ -1092,7 +1090,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
> * this batch updates GEN8_L3SQCREG4 with default value we need to
> * set this bit here to retain the WA during flush.
> */
> - if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
> + if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0))
> l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
>
> wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
> @@ -1181,7 +1179,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
> wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
>
> /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
> - if (IS_BROADWELL(engine->dev)) {
> + if (IS_BROADWELL(engine->i915)) {
> int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
> if (rc < 0)
> return rc;
> @@ -1253,12 +1251,11 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
> uint32_t *offset)
> {
> int ret;
> - struct drm_device *dev = engine->dev;
> uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>
> /* WaDisableCtxRestoreArbitration:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
> + IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
> wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
>
> /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
> @@ -1279,12 +1276,11 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
> uint32_t *const batch,
> uint32_t *offset)
> {
> - struct drm_device *dev = engine->dev;
> uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>
> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
> + IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
> wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
> wa_ctx_emit(batch, index,
> @@ -1293,7 +1289,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
> }
>
> /* WaClearTdlStateAckDirtyBits:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
> + if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
> wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
>
> wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
> @@ -1312,8 +1308,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
> }
>
> /* WaDisableCtxRestoreArbitration:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
> + IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
> wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
>
> wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
> @@ -1325,7 +1321,7 @@ static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
> {
> int ret;
>
> - engine->wa_ctx.obj = i915_gem_object_create(engine->dev,
> + engine->wa_ctx.obj = i915_gem_object_create(engine->i915->dev,
> PAGE_ALIGN(size));
> if (IS_ERR(engine->wa_ctx.obj)) {
> DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
> @@ -1365,9 +1361,9 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> WARN_ON(engine->id != RCS);
>
> /* update this when WA for higher Gen are added */
> - if (INTEL_INFO(engine->dev)->gen > 9) {
> + if (INTEL_GEN(engine->i915) > 9) {
> DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
> - INTEL_INFO(engine->dev)->gen);
> + INTEL_GEN(engine->i915));
> return 0;
> }
>
> @@ -1387,7 +1383,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> batch = kmap_atomic(page);
> offset = 0;
>
> - if (INTEL_INFO(engine->dev)->gen == 8) {
> + if (INTEL_GEN(engine->i915) == 8) {
IS_GEN8
> ret = gen8_init_indirectctx_bb(engine,
> &wa_ctx->indirect_ctx,
> batch,
> @@ -1401,7 +1397,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> &offset);
> if (ret)
> goto out;
> - } else if (INTEL_INFO(engine->dev)->gen == 9) {
> + } else if (INTEL_GEN(engine->i915) == 9) {
IS_GEN9
> ret = gen9_init_indirectctx_bb(engine,
> &wa_ctx->indirect_ctx,
> batch,
> @@ -1427,7 +1423,7 @@ out:
>
> static void lrc_init_hws(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> I915_WRITE(RING_HWS_PGA(engine->mmio_base),
> (u32)engine->status_page.gfx_addr);
> @@ -1436,8 +1432,7 @@ static void lrc_init_hws(struct intel_engine_cs *engine)
>
> static int gen8_init_common_ring(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned int next_context_status_buffer_hw;
>
> lrc_init_hws(engine);
> @@ -1484,8 +1479,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
>
> static int gen8_init_render_ring(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
>
> ret = gen8_init_common_ring(engine);
> @@ -1562,7 +1556,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
> if (req->ctx->ppgtt &&
> (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
> if (!USES_FULL_48BIT_PPGTT(req->i915) &&
> - !intel_vgpu_active(req->i915->dev)) {
> + !intel_vgpu_active(req->i915)) {
> ret = intel_logical_ring_emit_pdps(req);
> if (ret)
> return ret;
> @@ -1590,8 +1584,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
>
> static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1610,8 +1603,7 @@ static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
>
> static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1628,8 +1620,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
> {
> struct intel_ringbuffer *ringbuf = request->ringbuf;
> struct intel_engine_cs *engine = ringbuf->engine;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = request->i915;
> uint32_t cmd;
> int ret;
>
> @@ -1697,7 +1688,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
> * pipe control.
> */
> - if (IS_GEN9(engine->dev))
> + if (IS_GEN9(request->i915))
> vf_flush_wa = true;
> }
>
> @@ -1890,7 +1881,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
> if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
> tasklet_kill(&engine->irq_tasklet);
>
> - dev_priv = engine->dev->dev_private;
> + dev_priv = engine->i915;
>
> if (engine->buffer) {
> intel_logical_ring_stop(engine);
> @@ -1914,7 +1905,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
> engine->ctx_desc_template = 0;
>
> lrc_destroy_wa_ctx_obj(engine);
> - engine->dev = NULL;
> + engine->i915 = NULL;
> }
>
> static void
> @@ -1929,7 +1920,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> engine->emit_bb_start = gen8_emit_bb_start;
> engine->get_seqno = gen8_get_seqno;
> engine->set_seqno = gen8_set_seqno;
> - if (IS_BXT_REVID(engine->dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
> engine->irq_seqno_barrier = bxt_a_seqno_barrier;
> engine->set_seqno = bxt_a_set_seqno;
> }
> @@ -2023,7 +2014,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
> I915_WRITE_IMR(engine, ~0);
> POSTING_READ(RING_IMR(engine->mmio_base));
>
> - engine->dev = dev;
> + engine->i915 = dev_priv;
>
> /* Intentionally left blank. */
> engine->buffer = NULL;
> @@ -2056,7 +2047,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
> logical_ring_default_irqs(engine, info->irq_shift);
>
> intel_engine_init_hangcheck(engine);
> - i915_gem_batch_pool_init(engine->dev, &engine->batch_pool);
> + i915_gem_batch_pool_init(dev, &engine->batch_pool);
>
> return engine;
> }
> @@ -2064,7 +2055,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
> static int
> logical_ring_init(struct intel_engine_cs *engine)
> {
> - struct intel_context *dctx = to_i915(engine->dev)->kernel_context;
> + struct intel_context *dctx = engine->i915->kernel_context;
> int ret;
>
> ret = i915_cmd_parser_init_ring(engine);
> @@ -2224,7 +2215,7 @@ cleanup_render_ring:
> }
>
> static u32
> -make_rpcs(struct drm_device *dev)
> +make_rpcs(struct drm_i915_private *dev_priv)
> {
> u32 rpcs = 0;
>
> @@ -2232,7 +2223,7 @@ make_rpcs(struct drm_device *dev)
> * No explicit RPCS request is needed to ensure full
> * slice/subslice/EU enablement prior to Gen9.
> */
> - if (INTEL_INFO(dev)->gen < 9)
> + if (INTEL_GEN(dev_priv) < 9)
> return 0;
>
> /*
> @@ -2241,24 +2232,24 @@ make_rpcs(struct drm_device *dev)
> * must make an explicit request through RPCS for full
> * enablement.
> */
> - if (INTEL_INFO(dev)->has_slice_pg) {
> + if (INTEL_INFO(dev_priv)->has_slice_pg) {
> rpcs |= GEN8_RPCS_S_CNT_ENABLE;
> - rpcs |= INTEL_INFO(dev)->slice_total <<
> + rpcs |= INTEL_INFO(dev_priv)->slice_total <<
> GEN8_RPCS_S_CNT_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
>
> - if (INTEL_INFO(dev)->has_subslice_pg) {
> + if (INTEL_INFO(dev_priv)->has_subslice_pg) {
> rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
> - rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
> + rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice <<
> GEN8_RPCS_SS_CNT_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
>
> - if (INTEL_INFO(dev)->has_eu_pg) {
> - rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
> + if (INTEL_INFO(dev_priv)->has_eu_pg) {
> + rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
> GEN8_RPCS_EU_MIN_SHIFT;
> - rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
> + rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
> GEN8_RPCS_EU_MAX_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
> @@ -2270,9 +2261,9 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
> {
> u32 indirect_ctx_offset;
>
> - switch (INTEL_INFO(engine->dev)->gen) {
> + switch (INTEL_GEN(engine->i915)) {
> default:
> - MISSING_CASE(INTEL_INFO(engine->dev)->gen);
> + MISSING_CASE(INTEL_GEN(engine->i915));
> /* fall through */
> case 9:
> indirect_ctx_offset =
> @@ -2293,8 +2284,7 @@ populate_lr_context(struct intel_context *ctx,
> struct intel_engine_cs *engine,
> struct intel_ringbuffer *ringbuf)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = ctx->i915;
> struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
> void *vaddr;
> u32 *reg_state;
> @@ -2332,7 +2322,7 @@ populate_lr_context(struct intel_context *ctx,
> RING_CONTEXT_CONTROL(engine),
> _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
> CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
> - (HAS_RESOURCE_STREAMER(dev) ?
> + (HAS_RESOURCE_STREAMER(dev_priv) ?
> CTX_CTRL_RS_CTX_ENABLE : 0)));
> ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
> 0);
> @@ -2421,7 +2411,7 @@ populate_lr_context(struct intel_context *ctx,
> if (engine->id == RCS) {
> reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
> ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
> - make_rpcs(dev));
> + make_rpcs(dev_priv));
> }
>
> i915_gem_object_unpin_map(ctx_obj);
> @@ -2472,11 +2462,11 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> {
> int ret = 0;
>
> - WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
> + WARN_ON(INTEL_GEN(engine->i915) < 8);
Bah this is probably way too low level for this warn. /digression
>
> switch (engine->id) {
> case RCS:
> - if (INTEL_INFO(engine->dev)->gen >= 9)
> + if (INTEL_GEN(engine->i915) >= 9)
> ret = GEN9_LR_CONTEXT_RENDER_SIZE;
> else
> ret = GEN8_LR_CONTEXT_RENDER_SIZE;
> @@ -2508,7 +2498,7 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> static int execlists_context_deferred_alloc(struct intel_context *ctx,
> struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> + struct drm_device *dev = engine->i915->dev;
Variable used only once, could kill it.
> struct drm_i915_gem_object *ctx_obj;
> uint32_t context_size;
> struct intel_ringbuffer *ringbuf;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 229b8a974262..1afba0331dc6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -112,7 +112,8 @@ uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
> struct intel_engine_cs *engine);
>
> /* Execlists */
> -int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
> +int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
> + int enable_execlists);
> struct i915_execbuffer_params;
> int intel_execlists_submission(struct i915_execbuffer_params *params,
> struct drm_i915_gem_execbuffer2 *args,
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 6ba4bf7f2a89..b765c75f3fcd 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -189,7 +189,7 @@ static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
> */
> int intel_mocs_init_engine(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
> struct drm_i915_mocs_table table;
> unsigned int index;
>
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index 8570c60c6fc0..4a1e774ba8cc 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -1508,9 +1508,8 @@ static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
>
>
> struct intel_overlay_error_state *
> -intel_overlay_capture_error_state(struct drm_device *dev)
> +intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_overlay *overlay = dev_priv->overlay;
> struct intel_overlay_error_state *error;
> struct overlay_registers __iomem *regs;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 017c431f9363..ba097f2dd561 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6349,7 +6349,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> /* Powersaving is controlled by the host when inside a VM */
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> return;
>
> if (IS_IRONLAKE_M(dev)) {
> @@ -7405,8 +7405,7 @@ static void __intel_rps_boost_work(struct work_struct *work)
> struct drm_i915_gem_request *req = boost->req;
>
> if (!i915_gem_request_completed(req, true))
> - gen6_rps_boost(to_i915(req->engine->dev), NULL,
> - req->emitted_jiffies);
> + gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
>
> i915_gem_request_unreference(req);
> kfree(boost);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8f3eb3033da0..e8a28b0ccab9 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -60,7 +60,7 @@ void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
>
> bool intel_engine_stopped(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
> }
>
> @@ -106,7 +106,6 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> u32 flush_domains)
> {
> struct intel_engine_cs *engine = req->engine;
> - struct drm_device *dev = engine->dev;
> u32 cmd;
> int ret;
>
> @@ -145,7 +144,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> cmd |= MI_EXE_FLUSH;
>
> if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
> - (IS_G4X(dev) || IS_GEN5(dev)))
> + (IS_G4X(req->i915) || IS_GEN5(req->i915)))
> cmd |= MI_INVALIDATE_ISP;
>
> ret = intel_ring_begin(req, 2);
> @@ -431,19 +430,19 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> static void ring_write_tail(struct intel_engine_cs *engine,
> u32 value)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> I915_WRITE_TAIL(engine, value);
> }
>
> u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u64 acthd;
>
> - if (INTEL_INFO(engine->dev)->gen >= 8)
> + if (INTEL_GEN(dev_priv) >= 8)
> acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
> RING_ACTHD_UDW(engine->mmio_base));
> - else if (INTEL_INFO(engine->dev)->gen >= 4)
> + else if (INTEL_GEN(dev_priv) >= 4)
> acthd = I915_READ(RING_ACTHD(engine->mmio_base));
> else
> acthd = I915_READ(ACTHD);
> @@ -453,25 +452,24 @@ u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
>
> static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u32 addr;
>
> addr = dev_priv->status_page_dmah->busaddr;
> - if (INTEL_INFO(engine->dev)->gen >= 4)
> + if (INTEL_GEN(dev_priv) >= 4)
> addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
> I915_WRITE(HWS_PGA, addr);
> }
>
> static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> i915_reg_t mmio;
>
> /* The ring status page addresses are no longer next to the rest of
> * the ring registers as of gen7.
> */
> - if (IS_GEN7(dev)) {
> + if (IS_GEN7(dev_priv)) {
> switch (engine->id) {
> case RCS:
> mmio = RENDER_HWS_PGA_GEN7;
> @@ -491,7 +489,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> mmio = VEBOX_HWS_PGA_GEN7;
> break;
> }
> - } else if (IS_GEN6(engine->dev)) {
> + } else if (IS_GEN6(dev_priv)) {
> mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
> } else {
> /* XXX: gen8 returns to sanity */
> @@ -508,7 +506,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> * arises: do we still need this and if so how should we go about
> * invalidating the TLB?
> */
> - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
> + if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8) {
> i915_reg_t reg = RING_INSTPM(engine->mmio_base);
>
> /* ring should be idle before issuing a sync flush*/
> @@ -526,9 +524,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>
> static bool stop_ring(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
>
> - if (!IS_GEN2(engine->dev)) {
> + if (!IS_GEN2(dev_priv)) {
> I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
> if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
> DRM_ERROR("%s : timed out trying to stop ring\n",
> @@ -546,7 +544,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
> I915_WRITE_HEAD(engine, 0);
> engine->write_tail(engine, 0);
>
> - if (!IS_GEN2(engine->dev)) {
> + if (!IS_GEN2(dev_priv)) {
> (void)I915_READ_CTL(engine);
> I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
> }
> @@ -561,8 +559,7 @@ void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
>
> static int init_ring_common(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct intel_ringbuffer *ringbuf = engine->buffer;
> struct drm_i915_gem_object *obj = ringbuf->obj;
> int ret = 0;
> @@ -592,7 +589,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
> }
> }
>
> - if (I915_NEED_GFX_HWS(dev))
> + if (I915_NEED_GFX_HWS(dev_priv))
> intel_ring_setup_status_page(engine);
> else
> ring_setup_phys_status_page(engine);
> @@ -649,12 +646,10 @@ out:
> void
> intel_fini_pipe_control(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> -
> if (engine->scratch.obj == NULL)
> return;
>
> - if (INTEL_INFO(dev)->gen >= 5) {
> + if (INTEL_GEN(engine->i915) >= 5) {
> kunmap(sg_page(engine->scratch.obj->pages->sgl));
> i915_gem_object_ggtt_unpin(engine->scratch.obj);
> }
> @@ -670,7 +665,7 @@ intel_init_pipe_control(struct intel_engine_cs *engine)
>
> WARN_ON(engine->scratch.obj);
>
> - engine->scratch.obj = i915_gem_object_create(engine->dev, 4096);
> + engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
> if (IS_ERR(engine->scratch.obj)) {
> DRM_ERROR("Failed to allocate seqno page\n");
> ret = PTR_ERR(engine->scratch.obj);
> @@ -708,11 +703,9 @@ err:
>
> static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
> {
> - int ret, i;
> struct intel_engine_cs *engine = req->engine;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct i915_workarounds *w = &dev_priv->workarounds;
> + struct i915_workarounds *w = &req->i915->workarounds;
> + int ret, i;
>
> if (w->count == 0)
> return 0;
> @@ -801,7 +794,7 @@ static int wa_add(struct drm_i915_private *dev_priv,
> static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
> i915_reg_t reg)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct i915_workarounds *wa = &dev_priv->workarounds;
> const uint32_t index = wa->hw_whitelist_count[engine->id];
>
> @@ -817,8 +810,7 @@ static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
>
> static int gen8_init_workarounds(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>
> @@ -869,9 +861,8 @@ static int gen8_init_workarounds(struct intel_engine_cs *engine)
>
> static int bdw_init_workarounds(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
>
> ret = gen8_init_workarounds(engine);
> if (ret)
> @@ -891,16 +882,15 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
> /* WaForceContextSaveRestoreNonCoherent:bdw */
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
> - (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
> + (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
>
> return 0;
> }
>
> static int chv_init_workarounds(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
>
> ret = gen8_init_workarounds(engine);
> if (ret)
> @@ -917,8 +907,7 @@ static int chv_init_workarounds(struct intel_engine_cs *engine)
>
> static int gen9_init_workarounds(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> uint32_t tmp;
> int ret;
>
> @@ -941,14 +930,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>
> /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> GEN9_DG_MIRROR_FIX_ENABLE);
>
> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> GEN9_RHWO_OPTIMIZATION_DISABLE);
> /*
> @@ -974,20 +963,20 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> GEN9_CCS_TLB_PREFETCH_ENABLE);
>
> /* WaDisableMaskBasedCammingInRCC:skl,bxt */
> - if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> PIXEL_MASK_CAMMING_DISABLE);
>
> /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
> tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
> - if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
> - IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_F0, REVID_FOREVER) ||
> + IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
> tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
>
> /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
> - if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
> + if (IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> @@ -1013,8 +1002,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>
> static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u8 vals[3] = { 0, 0, 0 };
> unsigned int i;
>
> @@ -1055,9 +1043,8 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
>
> static int skl_init_workarounds(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
>
> ret = gen9_init_workarounds(engine);
> if (ret)
> @@ -1068,12 +1055,12 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
> * until D0 which is the default case so this is equivalent to
> * !WaDisablePerCtxtPreemptionGranularityControl:skl
> */
> - if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
> I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> }
>
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
> /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
> I915_WRITE(FF_SLICE_CS_CHICKEN2,
> _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
> @@ -1082,24 +1069,24 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
> /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
> * involving this register should also be added to WA batch as required.
> */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
> /* WaDisableLSQCROPERFforOCL:skl */
> I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
> GEN8_LQSC_RO_PERF_DIS);
>
> /* WaEnableGapsTsvCreditFix:skl */
> - if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
> I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> GEN9_GAPS_TSV_CREDIT_DISABLE));
> }
>
> /* WaDisablePowerCompilerClockGating:skl */
> - if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
> WA_SET_BIT_MASKED(HIZ_CHICKEN,
> BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
>
> /* This is tied to WaForceContextSaveRestoreNonCoherent */
> - if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
> + if (IS_SKL_REVID(dev_priv, 0, REVID_FOREVER)) {
> /*
> *Use Force Non-Coherent whenever executing a 3D context. This
> * is a workaround for a possible hang in the unlikely event
> @@ -1115,13 +1102,13 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
> }
>
> /* WaBarrierPerformanceFixDisable:skl */
> - if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
> WA_SET_BIT_MASKED(HDC_CHICKEN0,
> HDC_FENCE_DEST_SLM_DISABLE |
> HDC_BARRIER_PERFORMANCE_DISABLE);
>
> /* WaDisableSbeCacheDispatchPortSharing:skl */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
> WA_SET_BIT_MASKED(
> GEN7_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> @@ -1136,9 +1123,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
>
> static int bxt_init_workarounds(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
>
> ret = gen9_init_workarounds(engine);
> if (ret)
> @@ -1146,11 +1132,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>
> /* WaStoreMultiplePTEenable:bxt */
> /* This is a requirement according to Hardware specification */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
>
> /* WaSetClckGatingDisableMedia:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
> ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
> }
> @@ -1160,7 +1146,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> STALL_DOP_GATING_DISABLE);
>
> /* WaDisableSbeCacheDispatchPortSharing:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
> WA_SET_BIT_MASKED(
> GEN7_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> @@ -1170,7 +1156,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
> /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
> /* WaDisableLSQCROPERFforOCL:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
> if (ret)
> return ret;
> @@ -1181,7 +1167,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> }
>
> /* WaProgramL3SqcReg1DefaultForPerf:bxt */
> - if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
> + if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
> I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
> L3_HIGH_PRIO_CREDITS(2));
>
> @@ -1190,24 +1176,23 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>
> int init_workarounds_ring(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> WARN_ON(engine->id != RCS);
>
> dev_priv->workarounds.count = 0;
> dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
>
> - if (IS_BROADWELL(dev))
> + if (IS_BROADWELL(dev_priv))
> return bdw_init_workarounds(engine);
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> return chv_init_workarounds(engine);
>
> - if (IS_SKYLAKE(dev))
> + if (IS_SKYLAKE(dev_priv))
> return skl_init_workarounds(engine);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> return bxt_init_workarounds(engine);
>
> return 0;
> @@ -1215,14 +1200,13 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
>
> static int init_render_ring(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret = init_ring_common(engine);
> if (ret)
> return ret;
>
> /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> - if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
> + if (INTEL_GEN(dev_priv) >= 4 && INTEL_GEN(dev_priv) < 7)
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
>
> /* We need to disable the AsyncFlip performance optimisations in order
> @@ -1231,22 +1215,22 @@ static int init_render_ring(struct intel_engine_cs *engine)
> *
> * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
> */
> - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
> + if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
>
> /* Required for the hardware to program scanline values for waiting */
> /* WaEnableFlushTlbInvalidationMode:snb */
> - if (INTEL_INFO(dev)->gen == 6)
> + if (INTEL_GEN(dev_priv) == 6)
IS_GEN6
> I915_WRITE(GFX_MODE,
> _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
>
> /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> - if (IS_GEN7(dev))
> + if (IS_GEN7(dev_priv))
> I915_WRITE(GFX_MODE_GEN7,
> _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
> _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
>
> - if (IS_GEN6(dev)) {
> + if (IS_GEN6(dev_priv)) {
> /* From the Sandybridge PRM, volume 1 part 3, page 24:
> * "If this bit is set, STCunit will have LRA as replacement
> * policy. [...] This bit must be reset. LRA replacement
> @@ -1256,19 +1240,18 @@ static int init_render_ring(struct intel_engine_cs *engine)
> _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
> }
>
> - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
> + if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
> I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>
> - if (HAS_L3_DPF(dev))
> - I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
> + if (HAS_L3_DPF(dev_priv))
> + I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
>
> return init_workarounds_ring(engine);
> }
>
> static void render_ring_cleanup(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> if (dev_priv->semaphore_obj) {
> i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
> @@ -1284,13 +1267,12 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
> {
> #define MBOX_UPDATE_DWORDS 8
> struct intel_engine_cs *signaller = signaller_req->engine;
> - struct drm_device *dev = signaller->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> enum intel_engine_id id;
> int ret, num_rings;
>
> - num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
> #undef MBOX_UPDATE_DWORDS
>
> @@ -1326,13 +1308,12 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> {
> #define MBOX_UPDATE_DWORDS 6
> struct intel_engine_cs *signaller = signaller_req->engine;
> - struct drm_device *dev = signaller->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> enum intel_engine_id id;
> int ret, num_rings;
>
> - num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
> #undef MBOX_UPDATE_DWORDS
>
> @@ -1365,14 +1346,13 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> unsigned int num_dwords)
> {
> struct intel_engine_cs *signaller = signaller_req->engine;
> - struct drm_device *dev = signaller->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *useless;
> enum intel_engine_id id;
> int ret, num_rings;
>
> #define MBOX_UPDATE_DWORDS 3
> - num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
> #undef MBOX_UPDATE_DWORDS
>
> @@ -1460,10 +1440,9 @@ gen8_render_add_request(struct drm_i915_gem_request *req)
> return 0;
> }
>
> -static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
> +static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
> u32 seqno)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> return dev_priv->last_seqno < seqno;
> }
>
> @@ -1481,7 +1460,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
> u32 seqno)
> {
> struct intel_engine_cs *waiter = waiter_req->engine;
> - struct drm_i915_private *dev_priv = waiter->dev->dev_private;
> + struct drm_i915_private *dev_priv = waiter_req->i915;
> struct i915_hw_ppgtt *ppgtt;
> int ret;
>
> @@ -1535,7 +1514,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
> return ret;
>
> /* If seqno wrap happened, omit the wait with no-ops */
> - if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
> + if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
> intel_ring_emit(waiter, dw1 | wait_mbox);
> intel_ring_emit(waiter, seqno);
> intel_ring_emit(waiter, 0);
> @@ -1616,7 +1595,7 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> static void
> gen6_seqno_barrier(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> /* Workaround to force correct ordering between irq and seqno writes on
> * ivb (and maybe also on snb) by reading from a CS register (like
> @@ -1665,8 +1644,7 @@ pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
> static bool
> gen5_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1683,8 +1661,7 @@ gen5_ring_get_irq(struct intel_engine_cs *engine)
> static void
> gen5_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1696,8 +1673,7 @@ gen5_ring_put_irq(struct intel_engine_cs *engine)
> static bool
> i9xx_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (!intel_irqs_enabled(dev_priv))
> @@ -1717,8 +1693,7 @@ i9xx_ring_get_irq(struct intel_engine_cs *engine)
> static void
> i9xx_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1733,8 +1708,7 @@ i9xx_ring_put_irq(struct intel_engine_cs *engine)
> static bool
> i8xx_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (!intel_irqs_enabled(dev_priv))
> @@ -1754,8 +1728,7 @@ i8xx_ring_get_irq(struct intel_engine_cs *engine)
> static void
> i8xx_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1808,8 +1781,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
> static bool
> gen6_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1817,10 +1789,10 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> if (engine->irq_refcount++ == 0) {
> - if (HAS_L3_DPF(dev) && engine->id == RCS)
> + if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
> I915_WRITE_IMR(engine,
> ~(engine->irq_enable_mask |
> - GT_PARITY_ERROR(dev)));
> + GT_PARITY_ERROR(dev_priv)));
> else
> I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
> gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
> @@ -1833,14 +1805,13 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
> static void
> gen6_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> if (--engine->irq_refcount == 0) {
> - if (HAS_L3_DPF(dev) && engine->id == RCS)
> - I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
> + if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
> + I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
> else
> I915_WRITE_IMR(engine, ~0);
> gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
> @@ -1851,8 +1822,7 @@ gen6_ring_put_irq(struct intel_engine_cs *engine)
> static bool
> hsw_vebox_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1871,8 +1841,7 @@ hsw_vebox_get_irq(struct intel_engine_cs *engine)
> static void
> hsw_vebox_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1886,8 +1855,7 @@ hsw_vebox_put_irq(struct intel_engine_cs *engine)
> static bool
> gen8_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1895,7 +1863,7 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> if (engine->irq_refcount++ == 0) {
> - if (HAS_L3_DPF(dev) && engine->id == RCS) {
> + if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
> I915_WRITE_IMR(engine,
> ~(engine->irq_enable_mask |
> GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
> @@ -1912,13 +1880,12 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
> static void
> gen8_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> if (--engine->irq_refcount == 0) {
> - if (HAS_L3_DPF(dev) && engine->id == RCS) {
> + if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
This condition repeats enough to almost deserve
ENGINE_NEEDS_SOMETHING(engine). /digression
> I915_WRITE_IMR(engine,
> ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
> } else {
> @@ -2040,12 +2007,12 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
>
> static void cleanup_phys_status_page(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
>
> if (!dev_priv->status_page_dmah)
> return;
>
> - drm_pci_free(engine->dev, dev_priv->status_page_dmah);
> + drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
> engine->status_page.page_addr = NULL;
> }
>
> @@ -2071,7 +2038,7 @@ static int init_status_page(struct intel_engine_cs *engine)
> unsigned flags;
> int ret;
>
> - obj = i915_gem_object_create(engine->dev, 4096);
> + obj = i915_gem_object_create(engine->i915->dev, 4096);
> if (IS_ERR(obj)) {
> DRM_ERROR("Failed to allocate status page\n");
> return PTR_ERR(obj);
> @@ -2082,7 +2049,7 @@ static int init_status_page(struct intel_engine_cs *engine)
> goto err_unref;
>
> flags = 0;
> - if (!HAS_LLC(engine->dev))
> + if (!HAS_LLC(engine->i915))
> /* On g33, we cannot place HWS above 256MiB, so
> * restrict its pinning to the low mappable arena.
> * Though this restriction is not documented for
> @@ -2116,11 +2083,11 @@ err_unref:
>
> static int init_phys_status_page(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> if (!dev_priv->status_page_dmah) {
> dev_priv->status_page_dmah =
> - drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
> + drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
> if (!dev_priv->status_page_dmah)
> return -ENOMEM;
> }
> @@ -2146,10 +2113,9 @@ void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
> ringbuf->vma = NULL;
> }
>
> -int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
> +int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
> struct intel_ringbuffer *ringbuf)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_i915_gem_object *obj = ringbuf->obj;
> /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
> unsigned flags = PIN_OFFSET_BIAS | 4096;
> @@ -2248,13 +2214,13 @@ intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
> * of the buffer.
> */
> ring->effective_size = size;
> - if (IS_I830(engine->dev) || IS_845G(engine->dev))
> + if (IS_I830(engine->i915) || IS_845G(engine->i915))
> ring->effective_size -= 2 * CACHELINE_BYTES;
>
> ring->last_retired_head = -1;
> intel_ring_update_space(ring);
>
> - ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
> + ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
> if (ret) {
> DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
> engine->name, ret);
> @@ -2277,12 +2243,13 @@ intel_ringbuffer_free(struct intel_ringbuffer *ring)
> static int intel_init_ring_buffer(struct drm_device *dev,
> struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_ringbuffer *ringbuf;
> int ret;
>
> WARN_ON(engine->buffer);
>
> - engine->dev = dev;
> + engine->i915 = dev_priv;
> INIT_LIST_HEAD(&engine->active_list);
> INIT_LIST_HEAD(&engine->request_list);
> INIT_LIST_HEAD(&engine->execlist_queue);
> @@ -2300,7 +2267,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
> }
> engine->buffer = ringbuf;
>
> - if (I915_NEED_GFX_HWS(dev)) {
> + if (I915_NEED_GFX_HWS(dev_priv)) {
> ret = init_status_page(engine);
> if (ret)
> goto error;
> @@ -2311,7 +2278,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
> goto error;
> }
>
> - ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
> + ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
> if (ret) {
> DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
> engine->name, ret);
> @@ -2337,11 +2304,11 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
> if (!intel_engine_initialized(engine))
> return;
>
> - dev_priv = to_i915(engine->dev);
> + dev_priv = engine->i915;
>
> if (engine->buffer) {
> intel_stop_engine(engine);
> - WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
> + WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
>
> intel_unpin_ringbuffer_obj(engine->buffer);
> intel_ringbuffer_free(engine->buffer);
> @@ -2351,7 +2318,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
> if (engine->cleanup)
> engine->cleanup(engine);
>
> - if (I915_NEED_GFX_HWS(engine->dev)) {
> + if (I915_NEED_GFX_HWS(dev_priv)) {
> cleanup_status_page(engine);
> } else {
> WARN_ON(engine->id != RCS);
> @@ -2360,7 +2327,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
>
> i915_cmd_parser_fini_ring(engine);
> i915_gem_batch_pool_fini(&engine->batch_pool);
> - engine->dev = NULL;
> + engine->i915 = NULL;
> }
>
> int intel_engine_idle(struct intel_engine_cs *engine)
> @@ -2526,7 +2493,7 @@ int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
>
> void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
>
> /* Our semaphore implementation is strictly monotonic (i.e. we proceed
> * so long as the semaphore value in the register/page is greater
> @@ -2562,7 +2529,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
> static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
> u32 value)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> /* Every tail move must follow the sequence below */
>
> @@ -2604,7 +2571,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
> return ret;
>
> cmd = MI_FLUSH_DW;
> - if (INTEL_INFO(engine->dev)->gen >= 8)
> + if (INTEL_GEN(req->i915) >= 8)
> cmd += 1;
>
> /* We always require a command barrier so that subsequent
> @@ -2626,7 +2593,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
> intel_ring_emit(engine, cmd);
> intel_ring_emit(engine,
> I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
> - if (INTEL_INFO(engine->dev)->gen >= 8) {
> + if (INTEL_GEN(req->i915) >= 8) {
> intel_ring_emit(engine, 0); /* upper addr */
> intel_ring_emit(engine, 0); /* value */
> } else {
> @@ -2717,7 +2684,6 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate, u32 flush)
> {
> struct intel_engine_cs *engine = req->engine;
> - struct drm_device *dev = engine->dev;
> uint32_t cmd;
> int ret;
>
> @@ -2726,7 +2692,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
> return ret;
>
> cmd = MI_FLUSH_DW;
> - if (INTEL_INFO(dev)->gen >= 8)
> + if (INTEL_GEN(req->i915) >= 8)
> cmd += 1;
>
> /* We always require a command barrier so that subsequent
> @@ -2747,7 +2713,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
> intel_ring_emit(engine, cmd);
> intel_ring_emit(engine,
> I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(req->i915) >= 8) {
> intel_ring_emit(engine, 0); /* upper addr */
> intel_ring_emit(engine, 0); /* value */
> } else {
> @@ -2773,7 +2739,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->mmio_base = RENDER_RING_BASE;
>
> if (INTEL_INFO(dev)->gen >= 8) {
Double miss! :)
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> obj = i915_gem_object_create(dev, 4096);
> if (IS_ERR(obj)) {
> DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
> @@ -2798,7 +2764,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> engine->get_seqno = ring_get_seqno;
> engine->set_seqno = ring_set_seqno;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> WARN_ON(!dev_priv->semaphore_obj);
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_rcs_signal;
> @@ -2816,7 +2782,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->irq_seqno_barrier = gen6_seqno_barrier;
> engine->get_seqno = ring_get_seqno;
> engine->set_seqno = ring_set_seqno;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen6_ring_sync;
> engine->semaphore.signal = gen6_signal;
> /*
> @@ -2940,7 +2906,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> engine->irq_put = gen8_ring_put_irq;
> engine->dispatch_execbuffer =
> gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT(engine);
> @@ -2951,7 +2917,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> engine->irq_put = gen6_ring_put_irq;
> engine->dispatch_execbuffer =
> gen6_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen6_ring_sync;
> engine->semaphore.signal = gen6_signal;
> engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
> @@ -3014,7 +2980,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
> engine->irq_put = gen8_ring_put_irq;
> engine->dispatch_execbuffer =
> gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT(engine);
> @@ -3047,7 +3013,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> engine->irq_get = gen8_ring_get_irq;
> engine->irq_put = gen8_ring_put_irq;
> engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT(engine);
> @@ -3057,7 +3023,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> engine->irq_get = gen6_ring_get_irq;
> engine->irq_put = gen6_ring_put_irq;
> engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.signal = gen6_signal;
> engine->semaphore.sync_to = gen6_ring_sync;
> /*
> @@ -3108,7 +3074,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> engine->irq_get = gen8_ring_get_irq;
> engine->irq_put = gen8_ring_put_irq;
> engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT(engine);
> @@ -3118,7 +3084,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> engine->irq_get = hsw_vebox_get_irq;
> engine->irq_put = hsw_vebox_put_irq;
> engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen6_ring_sync;
> engine->semaphore.signal = gen6_signal;
> engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 723ff6160fbb..929e7b4af2a4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -141,7 +141,8 @@ struct i915_ctx_workarounds {
> struct drm_i915_gem_object *obj;
> };
>
> -struct intel_engine_cs {
> +struct intel_engine_cs {
> + struct drm_i915_private *i915;
> const char *name;
> enum intel_engine_id {
> RCS = 0,
> @@ -156,7 +157,6 @@ struct intel_engine_cs {
> unsigned int hw_id;
> unsigned int guc_id; /* XXX same as hw_id? */
> u32 mmio_base;
> - struct drm_device *dev;
> struct intel_ringbuffer *buffer;
> struct list_head buffers;
>
> @@ -350,7 +350,7 @@ struct intel_engine_cs {
> static inline bool
> intel_engine_initialized(struct intel_engine_cs *engine)
> {
> - return engine->dev != NULL;
> + return engine->i915 != NULL;
> }
>
> static inline unsigned
> @@ -425,7 +425,7 @@ intel_write_status_page(struct intel_engine_cs *engine,
>
> struct intel_ringbuffer *
> intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
> -int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
> +int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
> struct intel_ringbuffer *ringbuf);
> void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
> void intel_ringbuffer_free(struct intel_ringbuffer *ring);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 4f1dfe616856..4ea2bf2c2a4a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1381,7 +1381,7 @@ void intel_uncore_init(struct drm_device *dev)
> break;
> }
>
> - if (intel_vgpu_active(dev)) {
> + if (intel_vgpu_active(dev_priv)) {
> ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
> ASSIGN_READ_MMIO_VFUNCS(vgpu);
> }
> @@ -1663,8 +1663,8 @@ static int wait_for_register_fw(struct drm_i915_private *dev_priv,
>
> static int gen8_request_engine_reset(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
>
> I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
> _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
> @@ -1682,7 +1682,7 @@ static int gen8_request_engine_reset(struct intel_engine_cs *engine)
>
> static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
> _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
> @@ -1802,10 +1802,10 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
> {
> enum forcewake_domains fw_domains;
>
> - if (intel_vgpu_active(dev_priv->dev))
> + if (intel_vgpu_active(dev_priv))
> return 0;
>
> - switch (INTEL_INFO(dev_priv)->gen) {
> + switch (INTEL_GEN(dev_priv)) {
> case 9:
> fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg));
> break;
> @@ -1842,10 +1842,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
> {
> enum forcewake_domains fw_domains;
>
> - if (intel_vgpu_active(dev_priv->dev))
> + if (intel_vgpu_active(dev_priv))
> return 0;
>
> - switch (INTEL_INFO(dev_priv)->gen) {
> + switch (INTEL_GEN(dev_priv)) {
> case 9:
> fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
> break;
>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 02/19] drm/i915/execlists: Refactor common engine setup
2016-05-05 10:33 ` Chris Wilson
@ 2016-05-05 11:17 ` Tvrtko Ursulin
2016-05-05 11:55 ` Tvrtko Ursulin
0 siblings, 1 reply; 27+ messages in thread
From: Tvrtko Ursulin @ 2016-05-05 11:17 UTC (permalink / raw)
To: Chris Wilson, intel-gfx, Dave Gordon
On 05/05/16 11:33, Chris Wilson wrote:
> On Thu, May 05, 2016 at 11:18:41AM +0100, Tvrtko Ursulin wrote:
>>
>> Hi,
>>
>> On 05/05/16 10:15, Chris Wilson wrote:
>>> Move all of the constant assignments up front and into a common
>>> function. This is primarily to ensure the backpointers are set as early
>>> as possible for later use during initialisation.
>>>
>>> v2: Use a constant struct so that all the similar values are set
>>> together.
>>> v3: Sanitize the engine's IMR to disable any potential interrupt before
>>> we are ready (enabled in init_hw).
>>
>> Same as before - I don't like hardware access in this code path
>> since we otherwise have it split into a later init_hw phase. And I
>> don't like engine->dev being used for intel_engine_initialized.
>
> I think you raised a good point on the last round! It is an oversight
> that we have not explicitly sanitized the per-engine registers as is our
> mo. This gives us the symmetry with the init_hw phase where they are
> enabled.
>
>> On retrospect, interrupt vs engine->irq_queue race is already there
>> now, for the render ring at least. So maybe just drop the IMR bit
>> which would make the patch pure refactoring and can have my R-b
>> then.
>
> And this closes a race with a potential interrupt pending from takeover.
Okay but whether or not I have raised a good point I think it wouldn't
harm to split the pure refactoring from functional changes. You get at
least one R-b like that. ;)
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 03/19] drm/i915: Store a i915 backpointer from engine, and use it
2016-05-05 11:15 ` Tvrtko Ursulin
@ 2016-05-05 11:26 ` Chris Wilson
2016-05-05 11:37 ` [PATCH v2] " Chris Wilson
1 sibling, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 11:26 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Thu, May 05, 2016 at 12:15:40PM +0100, Tvrtko Ursulin wrote:
>
> On 05/05/16 10:15, Chris Wilson wrote:
> >@@ -3186,7 +3181,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> > if (i915_gem_request_completed(from_req, true))
> > return 0;
> >
> >- if (!i915_semaphore_is_enabled(obj->base.dev)) {
> >+ if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
> > struct drm_i915_private *i915 = to_i915(obj->base.dev);
>
> Maybe worth pulling up the local to function level since there are
> now two lines next to each other doing the same dereferencing?
This one gets changed quite a few times in forthcoming patches, the
double pointer chasing is indeed killed but here I opted for less churn
for myself.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2] drm/i915: Store a i915 backpointer from engine, and use it
2016-05-05 11:15 ` Tvrtko Ursulin
2016-05-05 11:26 ` Chris Wilson
@ 2016-05-05 11:37 ` Chris Wilson
2016-05-05 12:54 ` Tvrtko Ursulin
1 sibling, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2016-05-05 11:37 UTC (permalink / raw)
To: intel-gfx
text data bss dec hex filename
6309351 3578714 696320 10584385 a18141 vmlinux
6308391 3578714 696320 10583425 a17d81 vmlinux
Almost 1KiB of code reduction.
v2: More s/INTEL_INFO()->gen/INTEL_GEN()/ and IS_GENx() conversions
text data bss dec hex filename
6304579 3578778 696320 10579677 a16edd vmlinux
6303427 3578778 696320 10578525 a16a5d vmlinux
Now over 1KiB!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 12 +-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/i915_dma.c | 9 +-
drivers/gpu/drm/i915/i915_drv.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 35 +--
drivers/gpu/drm/i915/i915_gem.c | 47 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 48 ++--
drivers/gpu/drm/i915/i915_gem_evict.c | 4 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +--
drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +-
drivers/gpu/drm/i915/i915_gem_shrinker.c | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 79 +++----
drivers/gpu/drm/i915/i915_irq.c | 80 ++++---
drivers/gpu/drm/i915/i915_trace.h | 36 ++-
drivers/gpu/drm/i915/intel_display.c | 49 ++--
drivers/gpu/drm/i915/intel_drv.h | 4 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 139 ++++++------
drivers/gpu/drm/i915/intel_lrc.h | 3 +-
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_overlay.c | 3 +-
drivers/gpu/drm/i915/intel_pm.c | 5 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 328 ++++++++++++---------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 8 +-
drivers/gpu/drm/i915/intel_uncore.c | 14 +-
26 files changed, 461 insertions(+), 519 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 69a1ba8ebdfb..35224ea30201 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -750,12 +750,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
int cmd_table_count;
int ret;
- if (!IS_GEN7(engine->dev))
+ if (!IS_GEN7(engine->i915))
return 0;
switch (engine->id) {
case RCS:
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine->i915)) {
cmd_tables = hsw_render_ring_cmds;
cmd_table_count =
ARRAY_SIZE(hsw_render_ring_cmds);
@@ -764,7 +764,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
}
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine->i915)) {
engine->reg_tables = hsw_render_reg_tables;
engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
} else {
@@ -780,7 +780,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
break;
case BCS:
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine->i915)) {
cmd_tables = hsw_blt_ring_cmds;
cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
} else {
@@ -788,7 +788,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
}
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine->i915)) {
engine->reg_tables = hsw_blt_reg_tables;
engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
} else {
@@ -1035,7 +1035,7 @@ bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
if (!engine->needs_cmd_parser)
return false;
- if (!USES_PPGTT(engine->dev))
+ if (!USES_PPGTT(engine->i915))
return false;
return (i915.enable_cmd_parser == 1);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6ad008c196b5..6698957ede3f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1383,7 +1383,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
seqno[id] = engine->get_seqno(engine);
}
- i915_get_extra_instdone(dev, instdone);
+ i915_get_extra_instdone(dev_priv, instdone);
intel_runtime_pm_put(dev_priv);
@@ -3165,7 +3165,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused)
enum intel_engine_id id;
int j, ret;
- if (!i915_semaphore_is_enabled(dev)) {
+ if (!i915_semaphore_is_enabled(dev_priv)) {
seq_puts(m, "Semaphores are disabled\n");
return 0;
}
@@ -4766,7 +4766,7 @@ i915_wedged_set(void *data, u64 val)
intel_runtime_pm_get(dev_priv);
- i915_handle_error(dev, val,
+ i915_handle_error(dev_priv, val,
"Manually setting wedged to %llu", val);
intel_runtime_pm_put(dev_priv);
@@ -4916,7 +4916,7 @@ i915_drop_caches_set(void *data, u64 val)
}
if (val & (DROP_RETIRE | DROP_ACTIVE))
- i915_gem_retire_requests(dev);
+ i915_gem_retire_requests(dev_priv);
if (val & DROP_BOUND)
i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ad7abe517700..46ac1da64a09 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -186,7 +186,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = 1;
break;
case I915_PARAM_HAS_SEMAPHORES:
- value = i915_semaphore_is_enabled(dev);
+ value = i915_semaphore_is_enabled(dev_priv);
break;
case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
value = 1;
@@ -970,7 +970,8 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
info->has_eu_pg ? "y" : "n");
i915.enable_execlists =
- intel_sanitize_enable_execlists(dev, i915.enable_execlists);
+ intel_sanitize_enable_execlists(dev_priv,
+ i915.enable_execlists);
/*
* i915.enable_ppgtt is read-only, so do an early pass to validate the
@@ -979,7 +980,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
* than every time we check intel_enable_ppgtt().
*/
i915.enable_ppgtt =
- intel_sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
+ intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
}
@@ -1345,7 +1346,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
* Notify a valid surface after modesetting,
* when running inside a VM.
*/
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
i915_setup_sysfs(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9fd221c97275..ffbc61e9ff62 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -530,9 +530,9 @@ void intel_detect_pch(struct drm_device *dev)
pci_dev_put(pch);
}
-bool i915_semaphore_is_enabled(struct drm_device *dev)
+bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
{
- if (INTEL_INFO(dev)->gen < 6)
+ if (INTEL_GEN(dev_priv) < 6)
return false;
if (i915.semaphores >= 0)
@@ -544,7 +544,7 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
#ifdef CONFIG_INTEL_IOMMU
/* Enable semaphores on SNB when IO remapping is off */
- if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
+ if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped)
return false;
#endif
@@ -914,9 +914,9 @@ int i915_resume_switcheroo(struct drm_device *dev)
* - re-init interrupt state
* - re-init display
*/
-int i915_reset(struct drm_device *dev)
+int i915_reset(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_device *dev = dev_priv->dev;
struct i915_gpu_error *error = &dev_priv->gpu_error;
unsigned reset_counter;
int ret;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5496aba1cd5..c26fdf021104 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2754,7 +2754,8 @@ extern int i915_max_ioctl;
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
-int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt);
+int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
+ int enable_ppgtt);
/* i915_dma.c */
void __printf(3, 4)
@@ -2778,7 +2779,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
#endif
extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_device *dev);
-extern int i915_reset(struct drm_device *dev);
+extern int i915_reset(struct drm_i915_private *dev_priv);
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
@@ -2795,9 +2796,10 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
/* i915_irq.c */
-void i915_queue_hangcheck(struct drm_device *dev);
+void i915_queue_hangcheck(struct drm_i915_private *dev_priv);
__printf(3, 4)
-void i915_handle_error(struct drm_device *dev, u32 engine_mask,
+void i915_handle_error(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
const char *fmt, ...);
extern void intel_irq_init(struct drm_i915_private *dev_priv);
@@ -2827,9 +2829,9 @@ void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
-static inline bool intel_vgpu_active(struct drm_device *dev)
+static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
{
- return to_i915(dev)->vgpu.active;
+ return dev_priv->vgpu.active;
}
void
@@ -3097,13 +3099,13 @@ static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
req->seqno);
}
-int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
+int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno);
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
struct drm_i915_gem_request *
i915_gem_find_active_request(struct intel_engine_cs *engine);
-bool i915_gem_retire_requests(struct drm_device *dev);
+bool i915_gem_retire_requests(struct drm_i915_private *dev_priv);
void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
static inline u32 i915_reset_counter(struct i915_gpu_error *error)
@@ -3350,9 +3352,9 @@ int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
/* belongs in i915_gem_gtt.h */
-static inline void i915_gem_chipset_flush(struct drm_device *dev)
+static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
{
- if (INTEL_INFO(dev)->gen < 6)
+ if (INTEL_GEN(dev_priv) < 6)
intel_gtt_chipset_flush();
}
@@ -3431,14 +3433,15 @@ static inline void i915_error_state_buf_release(
{
kfree(eb->buf);
}
-void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
+void i915_capture_error_state(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
const char *error_msg);
void i915_error_state_get(struct drm_device *dev,
struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);
-void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
+void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
/* i915_cmd_parser.c */
@@ -3546,18 +3549,20 @@ extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_enable_rc6(const struct drm_device *dev);
-extern bool i915_semaphore_is_enabled(struct drm_device *dev);
+extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
/* overlay */
-extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
+extern struct intel_overlay_error_state *
+intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
struct intel_overlay_error_state *error);
-extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
+extern struct intel_display_error_state *
+intel_display_capture_error_state(struct drm_i915_private *dev_priv);
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
struct drm_device *dev,
struct intel_display_error_state *error);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a88e6c9e9516..c99d1b2c65d4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -177,7 +177,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
vaddr += PAGE_SIZE;
}
- i915_gem_chipset_flush(obj->base.dev);
+ i915_gem_chipset_flush(to_i915(obj->base.dev));
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (st == NULL)
@@ -347,7 +347,7 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
}
drm_clflush_virt_range(vaddr, args->size);
- i915_gem_chipset_flush(dev);
+ i915_gem_chipset_flush(to_i915(dev));
out:
intel_fb_obj_flush(obj, false, ORIGIN_CPU);
@@ -1006,7 +1006,7 @@ out:
}
if (needs_clflush_after)
- i915_gem_chipset_flush(dev);
+ i915_gem_chipset_flush(to_i915(dev));
else
obj->cache_dirty = true;
@@ -1230,8 +1230,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
struct intel_rps_client *rps)
{
struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = req->i915;
const bool irq_test_in_progress =
ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
@@ -1429,7 +1428,7 @@ __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
struct intel_engine_cs *engine = req->engine;
struct drm_i915_gem_request *tmp;
- lockdep_assert_held(&engine->dev->struct_mutex);
+ lockdep_assert_held(&engine->i915->dev->struct_mutex);
if (list_empty(&req->list))
return;
@@ -2502,9 +2501,8 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
}
static int
-i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
+i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *engine;
int ret;
@@ -2514,7 +2512,7 @@ i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
if (ret)
return ret;
}
- i915_gem_retire_requests(dev);
+ i915_gem_retire_requests(dev_priv);
/* Finally reset hw state */
for_each_engine(engine, dev_priv)
@@ -2534,7 +2532,7 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
/* HWS page needs to be set less than what we
* will inject to ring
*/
- ret = i915_gem_init_seqno(dev, seqno - 1);
+ ret = i915_gem_init_seqno(dev_priv, seqno - 1);
if (ret)
return ret;
@@ -2550,13 +2548,11 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
}
int
-i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
+i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
/* reserve 0 for non-seqno */
if (dev_priv->next_seqno == 0) {
- int ret = i915_gem_init_seqno(dev, 0);
+ int ret = i915_gem_init_seqno(dev_priv, 0);
if (ret)
return ret;
@@ -2654,7 +2650,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
/* Not allowed to fail! */
WARN(ret, "emit|add_request failed: %d!\n", ret);
- i915_queue_hangcheck(engine->dev);
+ i915_queue_hangcheck(engine->i915);
queue_delayed_work(dev_priv->wq,
&dev_priv->mm.retire_work,
@@ -2728,7 +2724,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
struct intel_context *ctx,
struct drm_i915_gem_request **req_out)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
struct drm_i915_gem_request *req;
int ret;
@@ -2750,7 +2746,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
if (req == NULL)
return -ENOMEM;
- ret = i915_gem_get_seqno(engine->dev, &req->seqno);
+ ret = i915_gem_get_seqno(engine->i915, &req->seqno);
if (ret)
goto err;
@@ -2807,7 +2803,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
int err;
if (ctx == NULL)
- ctx = to_i915(engine->dev)->kernel_context;
+ ctx = engine->i915->kernel_context;
err = __i915_gem_request_alloc(engine, ctx, &req);
return err ? ERR_PTR(err) : req;
}
@@ -2982,9 +2978,8 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
}
bool
-i915_gem_retire_requests(struct drm_device *dev)
+i915_gem_retire_requests(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *engine;
bool idle = true;
@@ -3017,7 +3012,7 @@ i915_gem_retire_work_handler(struct work_struct *work)
/* Come back later if the device is busy... */
idle = false;
if (mutex_trylock(&dev->struct_mutex)) {
- idle = i915_gem_retire_requests(dev);
+ idle = i915_gem_retire_requests(dev_priv);
mutex_unlock(&dev->struct_mutex);
}
if (!idle)
@@ -3186,7 +3181,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (i915_gem_request_completed(from_req, true))
return 0;
- if (!i915_semaphore_is_enabled(obj->base.dev)) {
+ if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
ret = __i915_wait_request(from_req,
i915->mm.interruptible,
@@ -3719,7 +3714,7 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
return;
if (i915_gem_clflush_object(obj, obj->pin_display))
- i915_gem_chipset_flush(obj->base.dev);
+ i915_gem_chipset_flush(to_i915(obj->base.dev));
old_write_domain = obj->base.write_domain;
obj->base.write_domain = 0;
@@ -3917,7 +3912,7 @@ out:
obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
cpu_write_needs_clflush(obj)) {
if (i915_gem_clflush_object(obj, true))
- i915_gem_chipset_flush(obj->base.dev);
+ i915_gem_chipset_flush(to_i915(obj->base.dev));
}
return 0;
@@ -4695,7 +4690,7 @@ i915_gem_suspend(struct drm_device *dev)
if (ret)
goto err;
- i915_gem_retire_requests(dev);
+ i915_gem_retire_requests(dev_priv);
i915_gem_stop_engines(dev);
i915_gem_context_lost(dev_priv);
@@ -4986,7 +4981,7 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
else
dev_priv->num_fence_regs = 8;
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
dev_priv->num_fence_regs =
I915_READ(vgtif_reg(avail_rs.fence_num));
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b1b704c2c001..0fffebcc0ace 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -99,28 +99,27 @@
#define GEN6_CONTEXT_ALIGN (64<<10)
#define GEN7_CONTEXT_ALIGN 4096
-static size_t get_context_alignment(struct drm_device *dev)
+static size_t get_context_alignment(struct drm_i915_private *dev_priv)
{
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
return GEN6_CONTEXT_ALIGN;
return GEN7_CONTEXT_ALIGN;
}
-static int get_context_size(struct drm_device *dev)
+static int get_context_size(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
u32 reg;
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_GEN(dev_priv)) {
case 6:
reg = I915_READ(CXT_SIZE);
ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
break;
case 7:
reg = I915_READ(GEN7_CXT_SIZE);
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev_priv))
ret = HSW_CXT_TOTAL_SIZE;
else
ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
@@ -224,7 +223,7 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
* Flush any pending retires to hopefully release some
* stale contexts and try again.
*/
- i915_gem_retire_requests(dev_priv->dev);
+ i915_gem_retire_requests(dev_priv);
ret = ida_simple_get(&dev_priv->context_hw_ida,
0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
if (ret < 0)
@@ -320,7 +319,7 @@ i915_gem_create_context(struct drm_device *dev,
* context.
*/
ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
- get_context_alignment(dev), 0);
+ get_context_alignment(to_i915(dev)), 0);
if (ret) {
DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
goto err_destroy;
@@ -389,7 +388,8 @@ int i915_gem_context_init(struct drm_device *dev)
if (WARN_ON(dev_priv->kernel_context))
return 0;
- if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
+ if (intel_vgpu_active(dev_priv) &&
+ HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
if (!i915.enable_execlists) {
DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
return -EINVAL;
@@ -404,8 +404,9 @@ int i915_gem_context_init(struct drm_device *dev)
/* NB: intentionally left blank. We will allocate our own
* backing objects as we need them, thank you very much */
dev_priv->hw_context_size = 0;
- } else if (HAS_HW_CONTEXTS(dev)) {
- dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
+ } else if (HAS_HW_CONTEXTS(dev_priv)) {
+ dev_priv->hw_context_size =
+ round_up(get_context_size(dev_priv), 4096);
if (dev_priv->hw_context_size > (1<<20)) {
DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
dev_priv->hw_context_size);
@@ -509,12 +510,13 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
+ struct drm_i915_private *dev_priv = req->i915;
struct intel_engine_cs *engine = req->engine;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
/* Use an extended w/a on ivb+ if signalling from other rings */
- i915_semaphore_is_enabled(engine->dev) ?
- hweight32(INTEL_INFO(engine->dev)->ring_mask) - 1 :
+ i915_semaphore_is_enabled(dev_priv) ?
+ hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 :
0;
int len, ret;
@@ -523,21 +525,21 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
* explicitly, so we rely on the value at ring init, stored in
* itlb_before_ctx_switch.
*/
- if (IS_GEN6(engine->dev)) {
+ if (IS_GEN6(dev_priv)) {
ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
if (ret)
return ret;
}
/* These flags are for resource streamer on HSW+ */
- if (IS_HASWELL(engine->dev) || INTEL_INFO(engine->dev)->gen >= 8)
+ if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
- else if (INTEL_INFO(engine->dev)->gen < 8)
+ else if (INTEL_GEN(dev_priv) < 8)
flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
len = 4;
- if (INTEL_INFO(engine->dev)->gen >= 7)
+ if (INTEL_GEN(dev_priv) >= 7)
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
ret = intel_ring_begin(req, len);
@@ -545,14 +547,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
return ret;
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
- if (INTEL_INFO(engine->dev)->gen >= 7) {
+ if (INTEL_GEN(dev_priv) >= 7) {
intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
if (num_rings) {
struct intel_engine_cs *signaller;
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_engine(signaller, to_i915(engine->dev)) {
+ for_each_engine(signaller, dev_priv) {
if (signaller == engine)
continue;
@@ -575,14 +577,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
*/
intel_ring_emit(engine, MI_NOOP);
- if (INTEL_INFO(engine->dev)->gen >= 7) {
+ if (INTEL_GEN(dev_priv) >= 7) {
if (num_rings) {
struct intel_engine_cs *signaller;
i915_reg_t last_reg = {}; /* keep gcc quiet */
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_engine(signaller, to_i915(engine->dev)) {
+ for_each_engine(signaller, dev_priv) {
if (signaller == engine)
continue;
@@ -673,7 +675,7 @@ needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
if (engine->id != RCS)
return true;
- if (INTEL_INFO(engine->dev)->gen < 8)
+ if (INTEL_GEN(engine->i915) < 8)
return true;
return false;
@@ -710,7 +712,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
/* Trying to pin first makes error handling easier. */
ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
- get_context_alignment(engine->dev),
+ get_context_alignment(engine->i915),
0);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index ea1f8d1bd228..b144c3f5c650 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -154,7 +154,7 @@ none:
if (ret)
return ret;
- i915_gem_retire_requests(dev);
+ i915_gem_retire_requests(to_i915(dev));
goto search_again;
}
@@ -265,7 +265,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle)
if (ret)
return ret;
- i915_gem_retire_requests(vm->dev);
+ i915_gem_retire_requests(to_i915(vm->dev));
WARN_ON(!list_empty(&vm->active_list));
}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index e0ee5d1ac372..a54a243ccaac 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -724,7 +724,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
struct i915_address_space *vm;
struct list_head ordered_vmas;
struct list_head pinned_vmas;
- bool has_fenced_gpu_access = INTEL_INFO(engine->dev)->gen < 4;
+ bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
int retry;
i915_gem_retire_requests_ring(engine);
@@ -965,7 +965,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
}
if (flush_chipset)
- i915_gem_chipset_flush(req->engine->dev);
+ i915_gem_chipset_flush(req->engine->i915);
if (flush_domains & I915_GEM_DOMAIN_GTT)
wmb();
@@ -1119,7 +1119,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
i915_gem_request_assign(&obj->last_fenced_req, req);
if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
&dev_priv->mm.fence_list);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 364cf8236021..3c474d594f47 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -110,17 +110,19 @@ const struct i915_ggtt_view i915_ggtt_view_rotated = {
.type = I915_GGTT_VIEW_ROTATED,
};
-int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
+int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
+ int enable_ppgtt)
{
bool has_aliasing_ppgtt;
bool has_full_ppgtt;
bool has_full_48bit_ppgtt;
- has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
- has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
- has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
+ has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6;
+ has_full_ppgtt = INTEL_GEN(dev_priv) >= 7;
+ has_full_48bit_ppgtt =
+ IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
has_full_ppgtt = false; /* emulation is too hard */
if (!has_aliasing_ppgtt)
@@ -130,7 +132,7 @@ int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
* We don't allow disabling PPGTT for gen9+ as it's a requirement for
* execlists, the sole mechanism available to submit work.
*/
- if (enable_ppgtt == 0 && INTEL_INFO(dev)->gen < 9)
+ if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
return 0;
if (enable_ppgtt == 1)
@@ -144,19 +146,19 @@ int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
#ifdef CONFIG_INTEL_IOMMU
/* Disable ppgtt on SNB if VT-d is on. */
- if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
+ if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) {
DRM_INFO("Disabling PPGTT because VT-d is on\n");
return 0;
}
#endif
/* Early VLV doesn't have this */
- if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
+ if (IS_VALLEYVIEW(dev_priv) && dev_priv->dev->pdev->revision < 0xb) {
DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
return 0;
}
- if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
+ if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists)
return has_full_48bit_ppgtt ? 3 : 2;
else
return has_aliasing_ppgtt ? 1 : 0;
@@ -994,7 +996,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
- if (intel_vgpu_active(vm->dev))
+ if (intel_vgpu_active(to_i915(vm->dev)))
gen8_ppgtt_notify_vgt(ppgtt, false);
if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
@@ -1545,14 +1547,14 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
0, 0,
GEN8_PML4E_SHIFT);
- if (intel_vgpu_active(ppgtt->base.dev)) {
+ if (intel_vgpu_active(to_i915(ppgtt->base.dev))) {
ret = gen8_preallocate_top_level_pdps(ppgtt);
if (ret)
goto free_scratch;
}
}
- if (intel_vgpu_active(ppgtt->base.dev))
+ if (intel_vgpu_active(to_i915(ppgtt->base.dev)))
gen8_ppgtt_notify_vgt(ppgtt, true);
return 0;
@@ -2080,7 +2082,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
} else
BUG();
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
ppgtt->switch_mm = vgpu_mm_switch;
ret = gen6_ppgtt_alloc(ppgtt);
@@ -2729,7 +2731,7 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
i915_address_space_init(&ggtt->base, dev_priv);
ggtt->base.total += PAGE_SIZE;
- if (intel_vgpu_active(dev)) {
+ if (intel_vgpu_active(dev_priv)) {
ret = intel_vgt_balloon(dev);
if (ret)
return ret;
@@ -2833,7 +2835,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
i915_gem_cleanup_stolen(dev);
if (drm_mm_initialized(&ggtt->base.mm)) {
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
intel_vgt_deballoon();
drm_mm_takedown(&ggtt->base.mm);
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 423cf5144bcb..7c93327b70fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -29,7 +29,7 @@
#include "intel_renderstate.h"
static const struct intel_renderstate_rodata *
-render_state_get_rodata(struct drm_device *dev, const int gen)
+render_state_get_rodata(const int gen)
{
switch (gen) {
case 6:
@@ -45,19 +45,20 @@ render_state_get_rodata(struct drm_device *dev, const int gen)
return NULL;
}
-static int render_state_init(struct render_state *so, struct drm_device *dev)
+static int render_state_init(struct render_state *so,
+ struct drm_i915_private *dev_priv)
{
int ret;
- so->gen = INTEL_INFO(dev)->gen;
- so->rodata = render_state_get_rodata(dev, so->gen);
+ so->gen = INTEL_GEN(dev_priv);
+ so->rodata = render_state_get_rodata(so->gen);
if (so->rodata == NULL)
return 0;
if (so->rodata->batch_items * 4 > 4096)
return -EINVAL;
- so->obj = i915_gem_object_create(dev, 4096);
+ so->obj = i915_gem_object_create(dev_priv->dev, 4096);
if (IS_ERR(so->obj))
return PTR_ERR(so->obj);
@@ -177,7 +178,7 @@ int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
if (WARN_ON(engine->id != RCS))
return -ENOENT;
- ret = render_state_init(so, engine->dev);
+ ret = render_state_init(so, engine->i915);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 79004f356174..538c30499848 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -131,7 +131,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
unsigned long count = 0;
trace_i915_gem_shrink(dev_priv, target, flags);
- i915_gem_retire_requests(dev_priv->dev);
+ i915_gem_retire_requests(dev_priv);
/*
* Unbinding of objects will require HW access; Let us not wake the
@@ -209,7 +209,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
if (flags & I915_SHRINK_BOUND)
intel_runtime_pm_put(dev_priv);
- i915_gem_retire_requests(dev_priv->dev);
+ i915_gem_retire_requests(dev_priv);
return count;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 89725c9efc25..0f6002cb86f4 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -824,19 +824,18 @@ static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
return error_code;
}
-static void i915_gem_record_fences(struct drm_device *dev,
+static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
int i;
- if (IS_GEN3(dev) || IS_GEN2(dev)) {
+ if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
for (i = 0; i < dev_priv->num_fence_regs; i++)
error->fence[i] = I915_READ(FENCE_REG(i));
- } else if (IS_GEN5(dev) || IS_GEN4(dev)) {
+ } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
for (i = 0; i < dev_priv->num_fence_regs; i++)
error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
- } else if (INTEL_INFO(dev)->gen >= 6) {
+ } else if (INTEL_GEN(dev_priv) >= 6) {
for (i = 0; i < dev_priv->num_fence_regs; i++)
error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
}
@@ -851,7 +850,7 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
struct intel_engine_cs *to;
enum intel_engine_id id;
- if (!i915_semaphore_is_enabled(dev_priv->dev))
+ if (!i915_semaphore_is_enabled(dev_priv))
return;
if (!error->semaphore_obj)
@@ -893,31 +892,29 @@ static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
}
}
-static void i915_record_ring_state(struct drm_device *dev,
+static void i915_record_ring_state(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error,
struct intel_engine_cs *engine,
struct drm_i915_error_ring *ering)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- if (INTEL_INFO(dev)->gen >= 6) {
+ if (INTEL_GEN(dev_priv) >= 6) {
ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
- if (INTEL_INFO(dev)->gen >= 8)
+ if (INTEL_GEN(dev_priv) >= 8)
gen8_record_semaphore_state(dev_priv, error, engine,
ering);
else
gen6_record_semaphore_state(dev_priv, engine, ering);
}
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_GEN(dev_priv) >= 4) {
ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
}
@@ -939,10 +936,10 @@ static void i915_record_ring_state(struct drm_device *dev,
ering->tail = I915_READ_TAIL(engine);
ering->ctl = I915_READ_CTL(engine);
- if (I915_NEED_GFX_HWS(dev)) {
+ if (I915_NEED_GFX_HWS(dev_priv)) {
i915_reg_t mmio;
- if (IS_GEN7(dev)) {
+ if (IS_GEN7(dev_priv)) {
switch (engine->id) {
default:
case RCS:
@@ -958,7 +955,7 @@ static void i915_record_ring_state(struct drm_device *dev,
mmio = VEBOX_HWS_PGA_GEN7;
break;
}
- } else if (IS_GEN6(engine->dev)) {
+ } else if (IS_GEN6(engine->i915)) {
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
} else {
/* XXX: gen8 returns to sanity */
@@ -971,18 +968,18 @@ static void i915_record_ring_state(struct drm_device *dev,
ering->hangcheck_score = engine->hangcheck.score;
ering->hangcheck_action = engine->hangcheck.action;
- if (USES_PPGTT(dev)) {
+ if (USES_PPGTT(dev_priv)) {
int i;
ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
ering->vm_info.pp_dir_base =
I915_READ(RING_PP_DIR_BASE_READ(engine));
- else if (IS_GEN7(dev))
+ else if (IS_GEN7(dev_priv))
ering->vm_info.pp_dir_base =
I915_READ(RING_PP_DIR_BASE(engine));
- else if (INTEL_INFO(dev)->gen >= 8)
+ else if (INTEL_GEN(dev_priv) >= 8)
for (i = 0; i < 4; i++) {
ering->vm_info.pdp[i] =
I915_READ(GEN8_RING_PDP_UDW(engine, i));
@@ -998,7 +995,7 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
struct drm_i915_error_state *error,
struct drm_i915_error_ring *ering)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct drm_i915_gem_object *obj;
/* Currently render ring is the only HW context user */
@@ -1016,10 +1013,9 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
}
}
-static void i915_gem_record_rings(struct drm_device *dev,
+static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_ggtt *ggtt = &dev_priv->ggtt;
struct drm_i915_gem_request *request;
int i, count;
@@ -1030,12 +1026,12 @@ static void i915_gem_record_rings(struct drm_device *dev,
error->ring[i].pid = -1;
- if (engine->dev == NULL)
+ if (!intel_engine_initialized(engine))
continue;
error->ring[i].valid = true;
- i915_record_ring_state(dev, error, engine, &error->ring[i]);
+ i915_record_ring_state(dev_priv, error, engine, &error->ring[i]);
request = i915_gem_find_active_request(engine);
if (request) {
@@ -1301,15 +1297,14 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
error->eir = I915_READ(EIR);
error->pgtbl_er = I915_READ(PGTBL_ER);
- i915_get_extra_instdone(dev, error->extra_instdone);
+ i915_get_extra_instdone(dev_priv, error->extra_instdone);
}
-static void i915_error_capture_msg(struct drm_device *dev,
+static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
struct drm_i915_error_state *error,
u32 engine_mask,
const char *error_msg)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
u32 ecode;
int ring_id = -1, len;
@@ -1317,7 +1312,7 @@ static void i915_error_capture_msg(struct drm_device *dev,
len = scnprintf(error->error_msg, sizeof(error->error_msg),
"GPU HANG: ecode %d:%d:0x%08x",
- INTEL_INFO(dev)->gen, ring_id, ecode);
+ INTEL_GEN(dev_priv), ring_id, ecode);
if (ring_id != -1 && error->ring[ring_id].pid != -1)
len += scnprintf(error->error_msg + len,
@@ -1352,11 +1347,11 @@ static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
* out a structure which becomes available in debugfs for user level tools
* to pick up.
*/
-void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
+void i915_capture_error_state(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
const char *error_msg)
{
static bool warned;
- struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_error_state *error;
unsigned long flags;
@@ -1372,15 +1367,15 @@ void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
i915_capture_gen_state(dev_priv, error);
i915_capture_reg_state(dev_priv, error);
i915_gem_capture_buffers(dev_priv, error);
- i915_gem_record_fences(dev, error);
- i915_gem_record_rings(dev, error);
+ i915_gem_record_fences(dev_priv, error);
+ i915_gem_record_rings(dev_priv, error);
do_gettimeofday(&error->time);
- error->overlay = intel_overlay_capture_error_state(dev);
- error->display = intel_display_capture_error_state(dev);
+ error->overlay = intel_overlay_capture_error_state(dev_priv);
+ error->display = intel_display_capture_error_state(dev_priv);
- i915_error_capture_msg(dev, error, engine_mask, error_msg);
+ i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
DRM_INFO("%s\n", error->error_msg);
spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
@@ -1400,7 +1395,7 @@ void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
- DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
+ DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev_priv->dev->primary->index);
warned = true;
}
}
@@ -1450,17 +1445,17 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
}
/* NB: please notice the memset */
-void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
+void i915_get_extra_instdone(struct drm_i915_private *dev_priv,
+ uint32_t *instdone)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
- if (IS_GEN2(dev) || IS_GEN3(dev))
+ if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
instdone[0] = I915_READ(GEN2_INSTDONE);
- else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
+ else if (IS_GEN4(dev_priv) || IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) {
instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
instdone[1] = I915_READ(GEN4_INSTDONE1);
- } else if (INTEL_INFO(dev)->gen >= 7) {
+ } else if (INTEL_GEN(dev_priv) >= 7) {
instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
instdone[1] = I915_READ(GEN7_SC_INSTDONE);
instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2f6fd33c07ba..8864ee19154f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2555,15 +2555,15 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
* Fire an error uevent so userspace can see that a hang or error
* was detected.
*/
-static void i915_reset_and_wakeup(struct drm_device *dev)
+static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
int ret;
- kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
+ kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
/*
* Note that there's only one work item which does gpu resets, so we
@@ -2577,8 +2577,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
*/
if (i915_reset_in_progress(&dev_priv->gpu_error)) {
DRM_DEBUG_DRIVER("resetting chip\n");
- kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
- reset_event);
+ kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
/*
* In most cases it's guaranteed that we get here with an RPM
@@ -2589,7 +2588,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
*/
intel_runtime_pm_get(dev_priv);
- intel_prepare_reset(dev);
+ intel_prepare_reset(dev_priv);
/*
* All state reset _must_ be completed before we update the
@@ -2597,14 +2596,14 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
* pending state and not properly drop locks, resulting in
* deadlocks with the reset work.
*/
- ret = i915_reset(dev);
+ ret = i915_reset(dev_priv);
- intel_finish_reset(dev);
+ intel_finish_reset(dev_priv);
intel_runtime_pm_put(dev_priv);
if (ret == 0)
- kobject_uevent_env(&dev->primary->kdev->kobj,
+ kobject_uevent_env(kobj,
KOBJ_CHANGE, reset_done_event);
/*
@@ -2615,9 +2614,8 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
}
}
-static void i915_report_and_clear_eir(struct drm_device *dev)
+static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t instdone[I915_NUM_INSTDONE_REG];
u32 eir = I915_READ(EIR);
int pipe, i;
@@ -2627,9 +2625,9 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
pr_err("render error detected, EIR: 0x%08x\n", eir);
- i915_get_extra_instdone(dev, instdone);
+ i915_get_extra_instdone(dev_priv, instdone);
- if (IS_G4X(dev)) {
+ if (IS_G4X(dev_priv)) {
if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
u32 ipeir = I915_READ(IPEIR_I965);
@@ -2651,7 +2649,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
}
}
- if (!IS_GEN2(dev)) {
+ if (!IS_GEN2(dev_priv)) {
if (eir & I915_ERROR_PAGE_TABLE) {
u32 pgtbl_err = I915_READ(PGTBL_ER);
pr_err("page table error\n");
@@ -2673,7 +2671,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
for (i = 0; i < ARRAY_SIZE(instdone); i++)
pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
- if (INTEL_INFO(dev)->gen < 4) {
+ if (INTEL_GEN(dev_priv) < 4) {
u32 ipeir = I915_READ(IPEIR);
pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
@@ -2717,10 +2715,10 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
* so userspace knows something bad happened (should trigger collection
* of a ring dump etc.).
*/
-void i915_handle_error(struct drm_device *dev, u32 engine_mask,
+void i915_handle_error(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
const char *fmt, ...)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
va_list args;
char error_msg[80];
@@ -2728,8 +2726,8 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
vscnprintf(error_msg, sizeof(error_msg), fmt, args);
va_end(args);
- i915_capture_error_state(dev, engine_mask, error_msg);
- i915_report_and_clear_eir(dev);
+ i915_capture_error_state(dev_priv, engine_mask, error_msg);
+ i915_report_and_clear_eir(dev_priv);
if (engine_mask) {
atomic_or(I915_RESET_IN_PROGRESS_FLAG,
@@ -2751,7 +2749,7 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
i915_error_wake_up(dev_priv, false);
}
- i915_reset_and_wakeup(dev);
+ i915_reset_and_wakeup(dev_priv);
}
/* Called from drm generic code, passed 'crtc' which
@@ -2869,9 +2867,9 @@ ring_idle(struct intel_engine_cs *engine, u32 seqno)
}
static bool
-ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
+ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr)
{
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
return (ipehr >> 23) == 0x1c;
} else {
ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
@@ -2884,10 +2882,10 @@ static struct intel_engine_cs *
semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
u64 offset)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct intel_engine_cs *signaller;
- if (INTEL_INFO(dev_priv)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
for_each_engine(signaller, dev_priv) {
if (engine == signaller)
continue;
@@ -2916,7 +2914,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
static struct intel_engine_cs *
semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u32 cmd, ipehr, head;
u64 offset = 0;
int i, backwards;
@@ -2942,7 +2940,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
return NULL;
ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
- if (!ipehr_is_semaphore_wait(engine->dev, ipehr))
+ if (!ipehr_is_semaphore_wait(engine->i915, ipehr))
return NULL;
/*
@@ -2954,7 +2952,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
* ringbuffer itself.
*/
head = I915_READ_HEAD(engine) & HEAD_ADDR;
- backwards = (INTEL_INFO(engine->dev)->gen >= 8) ? 5 : 4;
+ backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
for (i = backwards; i; --i) {
/*
@@ -2976,7 +2974,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
return NULL;
*seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
- if (INTEL_INFO(engine->dev)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
offset = ioread32(engine->buffer->virtual_start + head + 12);
offset <<= 32;
offset = ioread32(engine->buffer->virtual_start + head + 8);
@@ -2986,7 +2984,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
static int semaphore_passed(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct intel_engine_cs *signaller;
u32 seqno;
@@ -3028,7 +3026,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
if (engine->id != RCS)
return true;
- i915_get_extra_instdone(engine->dev, instdone);
+ i915_get_extra_instdone(engine->i915, instdone);
/* There might be unstable subunit states even when
* actual head is not moving. Filter out the unstable ones by
@@ -3069,8 +3067,7 @@ head_stuck(struct intel_engine_cs *engine, u64 acthd)
static enum intel_ring_hangcheck_action
ring_stuck(struct intel_engine_cs *engine, u64 acthd)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
enum intel_ring_hangcheck_action ha;
u32 tmp;
@@ -3078,7 +3075,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
if (ha != HANGCHECK_HUNG)
return ha;
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
return HANGCHECK_HUNG;
/* Is the chip hanging on a WAIT_FOR_EVENT?
@@ -3088,19 +3085,19 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
*/
tmp = I915_READ_CTL(engine);
if (tmp & RING_WAIT) {
- i915_handle_error(dev, 0,
+ i915_handle_error(dev_priv, 0,
"Kicking stuck wait on %s",
engine->name);
I915_WRITE_CTL(engine, tmp);
return HANGCHECK_KICK;
}
- if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
+ if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
switch (semaphore_passed(engine)) {
default:
return HANGCHECK_HUNG;
case 1:
- i915_handle_error(dev, 0,
+ i915_handle_error(dev_priv, 0,
"Kicking stuck semaphore on %s",
engine->name);
I915_WRITE_CTL(engine, tmp);
@@ -3115,7 +3112,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
static unsigned kick_waiters(struct intel_engine_cs *engine)
{
- struct drm_i915_private *i915 = to_i915(engine->dev);
+ struct drm_i915_private *i915 = engine->i915;
unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
if (engine->hangcheck.user_interrupts == user_interrupts &&
@@ -3144,7 +3141,6 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv),
gpu_error.hangcheck_work.work);
- struct drm_device *dev = dev_priv->dev;
struct intel_engine_cs *engine;
enum intel_engine_id id;
int busy_count = 0, rings_hung = 0;
@@ -3272,22 +3268,22 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
}
if (rings_hung) {
- i915_handle_error(dev, rings_hung, "Engine(s) hung");
+ i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
goto out;
}
if (busy_count)
/* Reset timer case chip hangs without another request
* being added */
- i915_queue_hangcheck(dev);
+ i915_queue_hangcheck(dev_priv);
out:
ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
}
-void i915_queue_hangcheck(struct drm_device *dev)
+void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
- struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
+ struct i915_gpu_error *e = &dev_priv->gpu_error;
if (!i915.enable_hangcheck)
return;
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index dc0def210097..20b2e4039792 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -462,7 +462,7 @@ TRACE_EVENT(i915_gem_ring_sync_to,
),
TP_fast_assign(
- __entry->dev = from->dev->primary->index;
+ __entry->dev = from->i915->dev->primary->index;
__entry->sync_from = from->id;
__entry->sync_to = to_req->engine->id;
__entry->seqno = i915_gem_request_get_seqno(req);
@@ -486,13 +486,11 @@ TRACE_EVENT(i915_gem_ring_dispatch,
),
TP_fast_assign(
- struct intel_engine_cs *engine =
- i915_gem_request_get_engine(req);
- __entry->dev = engine->dev->primary->index;
- __entry->ring = engine->id;
- __entry->seqno = i915_gem_request_get_seqno(req);
+ __entry->dev = req->i915->dev->primary->index;
+ __entry->ring = req->engine->id;
+ __entry->seqno = req->seqno;
__entry->flags = flags;
- i915_trace_irq_get(engine, req);
+ i915_trace_irq_get(req->engine, req);
),
TP_printk("dev=%u, ring=%u, seqno=%u, flags=%x",
@@ -511,7 +509,7 @@ TRACE_EVENT(i915_gem_ring_flush,
),
TP_fast_assign(
- __entry->dev = req->engine->dev->primary->index;
+ __entry->dev = req->i915->dev->primary->index;
__entry->ring = req->engine->id;
__entry->invalidate = invalidate;
__entry->flush = flush;
@@ -533,11 +531,9 @@ DECLARE_EVENT_CLASS(i915_gem_request,
),
TP_fast_assign(
- struct intel_engine_cs *engine =
- i915_gem_request_get_engine(req);
- __entry->dev = engine->dev->primary->index;
- __entry->ring = engine->id;
- __entry->seqno = i915_gem_request_get_seqno(req);
+ __entry->dev = req->i915->dev->primary->index;
+ __entry->ring = req->engine->id;
+ __entry->seqno = req->seqno;
),
TP_printk("dev=%u, ring=%u, seqno=%u",
@@ -560,7 +556,7 @@ TRACE_EVENT(i915_gem_request_notify,
),
TP_fast_assign(
- __entry->dev = engine->dev->primary->index;
+ __entry->dev = engine->i915->dev->primary->index;
__entry->ring = engine->id;
__entry->seqno = engine->get_seqno(engine);
),
@@ -597,13 +593,11 @@ TRACE_EVENT(i915_gem_request_wait_begin,
* less desirable.
*/
TP_fast_assign(
- struct intel_engine_cs *engine =
- i915_gem_request_get_engine(req);
- __entry->dev = engine->dev->primary->index;
- __entry->ring = engine->id;
- __entry->seqno = i915_gem_request_get_seqno(req);
+ __entry->dev = req->i915->dev->primary->index;
+ __entry->ring = req->engine->id;
+ __entry->seqno = req->seqno;
__entry->blocking =
- mutex_is_locked(&engine->dev->struct_mutex);
+ mutex_is_locked(&req->i915->dev->struct_mutex);
),
TP_printk("dev=%u, ring=%u, seqno=%u, blocking=%s",
@@ -792,7 +786,7 @@ TRACE_EVENT(switch_mm,
__entry->ring = engine->id;
__entry->to = to;
__entry->vm = to->ppgtt? &to->ppgtt->base : NULL;
- __entry->dev = engine->dev->primary->index;
+ __entry->dev = engine->i915->dev->primary->index;
),
TP_printk("dev=%u, ring=%u, ctx=%p, ctx_vm=%p",
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 45c218db86be..6e2e2b98d323 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3144,41 +3144,39 @@ static void intel_update_primary_planes(struct drm_device *dev)
}
}
-void intel_prepare_reset(struct drm_device *dev)
+void intel_prepare_reset(struct drm_i915_private *dev_priv)
{
/* no reset support for gen2 */
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
return;
/* reset doesn't touch the display */
- if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+ if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
return;
- drm_modeset_lock_all(dev);
+ drm_modeset_lock_all(dev_priv->dev);
/*
* Disabling the crtcs gracefully seems nicer. Also the
* g33 docs say we should at least disable all the planes.
*/
- intel_display_suspend(dev);
+ intel_display_suspend(dev_priv->dev);
}
-void intel_finish_reset(struct drm_device *dev)
+void intel_finish_reset(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
/*
* Flips in the rings will be nuked by the reset,
* so complete all pending flips so that user space
* will get its events and not get stuck.
*/
- intel_complete_page_flips(dev);
+ intel_complete_page_flips(dev_priv->dev);
/* no reset support for gen2 */
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
return;
/* reset doesn't touch the display */
- if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
+ if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
/*
* Flips in the rings have been nuked by the reset,
* so update the base address of all primary
@@ -3188,7 +3186,7 @@ void intel_finish_reset(struct drm_device *dev)
* FIXME: Atomic will make this obsolete since we won't schedule
* CS-based flips (which might get lost in gpu resets) any more.
*/
- intel_update_primary_planes(dev);
+ intel_update_primary_planes(dev_priv->dev);
return;
}
@@ -3199,18 +3197,18 @@ void intel_finish_reset(struct drm_device *dev)
intel_runtime_pm_disable_interrupts(dev_priv);
intel_runtime_pm_enable_interrupts(dev_priv);
- intel_modeset_init_hw(dev);
+ intel_modeset_init_hw(dev_priv->dev);
spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display.hpd_irq_setup)
- dev_priv->display.hpd_irq_setup(dev);
+ dev_priv->display.hpd_irq_setup(dev_priv->dev);
spin_unlock_irq(&dev_priv->irq_lock);
- intel_display_resume(dev);
+ intel_display_resume(dev_priv->dev);
intel_hpd_init(dev_priv);
- drm_modeset_unlock_all(dev);
+ drm_modeset_unlock_all(dev_priv->dev);
}
static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
@@ -11256,7 +11254,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
if (engine == NULL)
return true;
- if (INTEL_INFO(engine->dev)->gen < 5)
+ if (INTEL_GEN(engine->i915) < 5)
return false;
if (i915.use_mmio_flip < 0)
@@ -16185,9 +16183,8 @@ struct intel_display_error_state {
};
struct intel_display_error_state *
-intel_display_capture_error_state(struct drm_device *dev)
+intel_display_capture_error_state(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_display_error_state *error;
int transcoders[] = {
TRANSCODER_A,
@@ -16197,14 +16194,14 @@ intel_display_capture_error_state(struct drm_device *dev)
};
int i;
- if (INTEL_INFO(dev)->num_pipes == 0)
+ if (INTEL_INFO(dev_priv)->num_pipes == 0)
return NULL;
error = kzalloc(sizeof(*error), GFP_ATOMIC);
if (error == NULL)
return NULL;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
for_each_pipe(dev_priv, i) {
@@ -16220,25 +16217,25 @@ intel_display_capture_error_state(struct drm_device *dev)
error->plane[i].control = I915_READ(DSPCNTR(i));
error->plane[i].stride = I915_READ(DSPSTRIDE(i));
- if (INTEL_INFO(dev)->gen <= 3) {
+ if (INTEL_GEN(dev_priv) <= 3) {
error->plane[i].size = I915_READ(DSPSIZE(i));
error->plane[i].pos = I915_READ(DSPPOS(i));
}
- if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
+ if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
error->plane[i].addr = I915_READ(DSPADDR(i));
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_GEN(dev_priv) >= 4) {
error->plane[i].surface = I915_READ(DSPSURF(i));
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
}
error->pipe[i].source = I915_READ(PIPESRC(i));
- if (HAS_GMCH_DISPLAY(dev))
+ if (HAS_GMCH_DISPLAY(dev_priv))
error->pipe[i].stat = I915_READ(PIPESTAT(i));
}
/* Note: this does not include DSI transcoders. */
- error->num_transcoders = INTEL_INFO(dev)->num_pipes;
+ error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
if (HAS_DDI(dev_priv))
error->num_transcoders++; /* Account for eDP. */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 51058522741a..66de61669884 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1226,8 +1226,8 @@ u32 intel_compute_tile_offset(int *x, int *y,
const struct drm_framebuffer *fb, int plane,
unsigned int pitch,
unsigned int rotation);
-void intel_prepare_reset(struct drm_device *dev);
-void intel_finish_reset(struct drm_device *dev);
+void intel_prepare_reset(struct drm_i915_private *dev_priv);
+void intel_finish_reset(struct drm_i915_private *dev_priv);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void broxton_init_cdclk(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index d5a7cfec589b..4a527d3cf026 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -827,7 +827,7 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc)
bool enable_by_default = IS_HASWELL(dev_priv) ||
IS_BROADWELL(dev_priv);
- if (intel_vgpu_active(dev_priv->dev)) {
+ if (intel_vgpu_active(dev_priv)) {
fbc->no_fbc_reason = "VGPU is active";
return false;
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8106316ce56f..62bea20283df 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -246,21 +246,22 @@ static int intel_lr_context_pin(struct intel_context *ctx,
*
* Return: 1 if Execlists is supported and has to be enabled.
*/
-int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
+int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
{
/* On platforms with execlist available, vGPU will only
* support execlist mode, no ring buffer mode.
*/
- if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
+ if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
return 1;
- if (INTEL_INFO(dev)->gen >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
return 1;
if (enable_execlists == 0)
return 0;
- if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
+ if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
+ USES_PPGTT(dev_priv) &&
i915.use_mmio_flip >= 0)
return 1;
@@ -270,19 +271,19 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists
static void
logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
+ struct drm_i915_private *dev_priv = engine->i915;
- if (IS_GEN8(dev) || IS_GEN9(dev))
+ if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
engine->idle_lite_restore_wa = ~0;
- engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
+ engine->disable_lite_restore_wa = (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
(engine->id == VCS || engine->id == VCS2);
engine->ctx_desc_template = GEN8_CTX_VALID;
- engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
+ engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
GEN8_CTX_ADDRESSING_MODE_SHIFT;
- if (IS_GEN8(dev))
+ if (IS_GEN8(dev_priv))
engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
@@ -342,8 +343,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
{
struct intel_engine_cs *engine = rq0->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = rq0->i915;
uint64_t desc[2];
if (rq1) {
@@ -425,7 +425,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
* If irqs are not active generate a warning as batches that finish
* without the irqs may get lost and a GPU Hang may occur.
*/
- WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
+ WARN_ON(!intel_irqs_enabled(engine->i915));
/* Try to read in pairs */
list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
@@ -497,7 +497,7 @@ static u32
get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
u32 *context_id)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u32 status;
read_pointer %= GEN8_CSB_ENTRIES;
@@ -523,7 +523,7 @@ get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
static void intel_lrc_irq_handler(unsigned long data)
{
struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u32 status_pointer;
unsigned int read_pointer, write_pointer;
u32 csb[GEN8_CSB_ENTRIES][2];
@@ -884,7 +884,7 @@ void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
struct drm_i915_gem_request *req, *tmp;
LIST_HEAD(cancel_list);
- WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
+ WARN_ON(!mutex_is_locked(&engine->i915->dev->struct_mutex));
spin_lock_bh(&engine->execlist_lock);
list_replace_init(&engine->execlist_queue, &cancel_list);
@@ -898,7 +898,7 @@ void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
void intel_logical_ring_stop(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
if (!intel_engine_initialized(engine))
@@ -964,7 +964,7 @@ static int intel_lr_context_pin(struct intel_context *ctx,
lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
ringbuf = ctx->engine[engine->id].ringbuf;
- ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
+ ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
if (ret)
goto unpin_map;
@@ -1019,9 +1019,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
int ret, i;
struct intel_engine_cs *engine = req->engine;
struct intel_ringbuffer *ringbuf = req->ringbuf;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct i915_workarounds *w = &dev_priv->workarounds;
+ struct i915_workarounds *w = &req->i915->workarounds;
if (w->count == 0)
return 0;
@@ -1092,7 +1090,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
* this batch updates GEN8_L3SQCREG4 with default value we need to
* set this bit here to retain the WA during flush.
*/
- if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
+ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0))
l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
@@ -1181,7 +1179,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
- if (IS_BROADWELL(engine->dev)) {
+ if (IS_BROADWELL(engine->i915)) {
int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
if (rc < 0)
return rc;
@@ -1253,12 +1251,11 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
uint32_t *offset)
{
int ret;
- struct drm_device *dev = engine->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
/* WaDisableCtxRestoreArbitration:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
+ IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
@@ -1279,12 +1276,11 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
uint32_t *const batch,
uint32_t *offset)
{
- struct drm_device *dev = engine->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
wa_ctx_emit(batch, index,
@@ -1293,7 +1289,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
}
/* WaClearTdlStateAckDirtyBits:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
+ if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
@@ -1312,8 +1308,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
}
/* WaDisableCtxRestoreArbitration:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
+ IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
@@ -1325,7 +1321,7 @@ static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
{
int ret;
- engine->wa_ctx.obj = i915_gem_object_create(engine->dev,
+ engine->wa_ctx.obj = i915_gem_object_create(engine->i915->dev,
PAGE_ALIGN(size));
if (IS_ERR(engine->wa_ctx.obj)) {
DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
@@ -1365,9 +1361,9 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
WARN_ON(engine->id != RCS);
/* update this when WA for higher Gen are added */
- if (INTEL_INFO(engine->dev)->gen > 9) {
+ if (INTEL_GEN(engine->i915) > 9) {
DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
- INTEL_INFO(engine->dev)->gen);
+ INTEL_GEN(engine->i915));
return 0;
}
@@ -1387,7 +1383,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
batch = kmap_atomic(page);
offset = 0;
- if (INTEL_INFO(engine->dev)->gen == 8) {
+ if (IS_GEN8(engine->i915)) {
ret = gen8_init_indirectctx_bb(engine,
&wa_ctx->indirect_ctx,
batch,
@@ -1401,7 +1397,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
&offset);
if (ret)
goto out;
- } else if (INTEL_INFO(engine->dev)->gen == 9) {
+ } else if (IS_GEN9(engine->i915)) {
ret = gen9_init_indirectctx_bb(engine,
&wa_ctx->indirect_ctx,
batch,
@@ -1427,7 +1423,7 @@ out:
static void lrc_init_hws(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
(u32)engine->status_page.gfx_addr);
@@ -1436,8 +1432,7 @@ static void lrc_init_hws(struct intel_engine_cs *engine)
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned int next_context_status_buffer_hw;
lrc_init_hws(engine);
@@ -1484,8 +1479,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
static int gen8_init_render_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
ret = gen8_init_common_ring(engine);
@@ -1562,7 +1556,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
if (req->ctx->ppgtt &&
(intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
if (!USES_FULL_48BIT_PPGTT(req->i915) &&
- !intel_vgpu_active(req->i915->dev)) {
+ !intel_vgpu_active(req->i915)) {
ret = intel_logical_ring_emit_pdps(req);
if (ret)
return ret;
@@ -1590,8 +1584,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1610,8 +1603,7 @@ static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1628,8 +1620,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
{
struct intel_ringbuffer *ringbuf = request->ringbuf;
struct intel_engine_cs *engine = ringbuf->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = request->i915;
uint32_t cmd;
int ret;
@@ -1697,7 +1688,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
* On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
* pipe control.
*/
- if (IS_GEN9(engine->dev))
+ if (IS_GEN9(request->i915))
vf_flush_wa = true;
}
@@ -1890,7 +1881,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
tasklet_kill(&engine->irq_tasklet);
- dev_priv = engine->dev->dev_private;
+ dev_priv = engine->i915;
if (engine->buffer) {
intel_logical_ring_stop(engine);
@@ -1914,7 +1905,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
engine->ctx_desc_template = 0;
lrc_destroy_wa_ctx_obj(engine);
- engine->dev = NULL;
+ engine->i915 = NULL;
}
static void
@@ -1929,7 +1920,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_bb_start = gen8_emit_bb_start;
engine->get_seqno = gen8_get_seqno;
engine->set_seqno = gen8_set_seqno;
- if (IS_BXT_REVID(engine->dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
engine->irq_seqno_barrier = bxt_a_seqno_barrier;
engine->set_seqno = bxt_a_set_seqno;
}
@@ -2023,7 +2014,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
I915_WRITE_IMR(engine, ~0);
POSTING_READ(RING_IMR(engine->mmio_base));
- engine->dev = dev;
+ engine->i915 = dev_priv;
/* Intentionally left blank. */
engine->buffer = NULL;
@@ -2056,7 +2047,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
logical_ring_default_irqs(engine, info->irq_shift);
intel_engine_init_hangcheck(engine);
- i915_gem_batch_pool_init(engine->dev, &engine->batch_pool);
+ i915_gem_batch_pool_init(dev, &engine->batch_pool);
return engine;
}
@@ -2064,7 +2055,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
static int
logical_ring_init(struct intel_engine_cs *engine)
{
- struct intel_context *dctx = to_i915(engine->dev)->kernel_context;
+ struct intel_context *dctx = engine->i915->kernel_context;
int ret;
ret = i915_cmd_parser_init_ring(engine);
@@ -2224,7 +2215,7 @@ cleanup_render_ring:
}
static u32
-make_rpcs(struct drm_device *dev)
+make_rpcs(struct drm_i915_private *dev_priv)
{
u32 rpcs = 0;
@@ -2232,7 +2223,7 @@ make_rpcs(struct drm_device *dev)
* No explicit RPCS request is needed to ensure full
* slice/subslice/EU enablement prior to Gen9.
*/
- if (INTEL_INFO(dev)->gen < 9)
+ if (INTEL_GEN(dev_priv) < 9)
return 0;
/*
@@ -2241,24 +2232,24 @@ make_rpcs(struct drm_device *dev)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (INTEL_INFO(dev)->has_slice_pg) {
+ if (INTEL_INFO(dev_priv)->has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
- rpcs |= INTEL_INFO(dev)->slice_total <<
+ rpcs |= INTEL_INFO(dev_priv)->slice_total <<
GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev)->has_subslice_pg) {
+ if (INTEL_INFO(dev_priv)->has_subslice_pg) {
rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
- rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
+ rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice <<
GEN8_RPCS_SS_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev)->has_eu_pg) {
- rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
+ if (INTEL_INFO(dev_priv)->has_eu_pg) {
+ rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
GEN8_RPCS_EU_MIN_SHIFT;
- rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
+ rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
GEN8_RPCS_EU_MAX_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
@@ -2270,9 +2261,9 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
{
u32 indirect_ctx_offset;
- switch (INTEL_INFO(engine->dev)->gen) {
+ switch (INTEL_GEN(engine->i915)) {
default:
- MISSING_CASE(INTEL_INFO(engine->dev)->gen);
+ MISSING_CASE(INTEL_GEN(engine->i915));
/* fall through */
case 9:
indirect_ctx_offset =
@@ -2293,8 +2284,7 @@ populate_lr_context(struct intel_context *ctx,
struct intel_engine_cs *engine,
struct intel_ringbuffer *ringbuf)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = ctx->i915;
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
void *vaddr;
u32 *reg_state;
@@ -2332,7 +2322,7 @@ populate_lr_context(struct intel_context *ctx,
RING_CONTEXT_CONTROL(engine),
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
- (HAS_RESOURCE_STREAMER(dev) ?
+ (HAS_RESOURCE_STREAMER(dev_priv) ?
CTX_CTRL_RS_CTX_ENABLE : 0)));
ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
0);
@@ -2421,7 +2411,7 @@ populate_lr_context(struct intel_context *ctx,
if (engine->id == RCS) {
reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
- make_rpcs(dev));
+ make_rpcs(dev_priv));
}
i915_gem_object_unpin_map(ctx_obj);
@@ -2472,11 +2462,11 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
{
int ret = 0;
- WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
+ WARN_ON(INTEL_GEN(engine->i915) < 8);
switch (engine->id) {
case RCS:
- if (INTEL_INFO(engine->dev)->gen >= 9)
+ if (INTEL_GEN(engine->i915) >= 9)
ret = GEN9_LR_CONTEXT_RENDER_SIZE;
else
ret = GEN8_LR_CONTEXT_RENDER_SIZE;
@@ -2508,7 +2498,6 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
static int execlists_context_deferred_alloc(struct intel_context *ctx,
struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
struct drm_i915_gem_object *ctx_obj;
uint32_t context_size;
struct intel_ringbuffer *ringbuf;
@@ -2522,7 +2511,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
/* One extra page as the sharing data between driver and GuC */
context_size += PAGE_SIZE * LRC_PPHWSP_PN;
- ctx_obj = i915_gem_object_create(dev, context_size);
+ ctx_obj = i915_gem_object_create(ctx->i915->dev, context_size);
if (IS_ERR(ctx_obj)) {
DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
return PTR_ERR(ctx_obj);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 229b8a974262..1afba0331dc6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -112,7 +112,8 @@ uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
struct intel_engine_cs *engine);
/* Execlists */
-int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
+int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
+ int enable_execlists);
struct i915_execbuffer_params;
int intel_execlists_submission(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 6ba4bf7f2a89..b765c75f3fcd 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -189,7 +189,7 @@ static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
*/
int intel_mocs_init_engine(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
struct drm_i915_mocs_table table;
unsigned int index;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 8570c60c6fc0..4a1e774ba8cc 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1508,9 +1508,8 @@ static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
struct intel_overlay_error_state *
-intel_overlay_capture_error_state(struct drm_device *dev)
+intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_overlay *overlay = dev_priv->overlay;
struct intel_overlay_error_state *error;
struct overlay_registers __iomem *regs;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 017c431f9363..ba097f2dd561 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6349,7 +6349,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
/* Powersaving is controlled by the host when inside a VM */
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev_priv))
return;
if (IS_IRONLAKE_M(dev)) {
@@ -7405,8 +7405,7 @@ static void __intel_rps_boost_work(struct work_struct *work)
struct drm_i915_gem_request *req = boost->req;
if (!i915_gem_request_completed(req, true))
- gen6_rps_boost(to_i915(req->engine->dev), NULL,
- req->emitted_jiffies);
+ gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
i915_gem_request_unreference(req);
kfree(boost);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8f3eb3033da0..e17a682dd621 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -60,7 +60,7 @@ void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
bool intel_engine_stopped(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
}
@@ -106,7 +106,6 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
u32 flush_domains)
{
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
u32 cmd;
int ret;
@@ -145,7 +144,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
cmd |= MI_EXE_FLUSH;
if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
- (IS_G4X(dev) || IS_GEN5(dev)))
+ (IS_G4X(req->i915) || IS_GEN5(req->i915)))
cmd |= MI_INVALIDATE_ISP;
ret = intel_ring_begin(req, 2);
@@ -431,19 +430,19 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
static void ring_write_tail(struct intel_engine_cs *engine,
u32 value)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
I915_WRITE_TAIL(engine, value);
}
u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u64 acthd;
- if (INTEL_INFO(engine->dev)->gen >= 8)
+ if (INTEL_GEN(dev_priv) >= 8)
acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
RING_ACTHD_UDW(engine->mmio_base));
- else if (INTEL_INFO(engine->dev)->gen >= 4)
+ else if (INTEL_GEN(dev_priv) >= 4)
acthd = I915_READ(RING_ACTHD(engine->mmio_base));
else
acthd = I915_READ(ACTHD);
@@ -453,25 +452,24 @@ u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u32 addr;
addr = dev_priv->status_page_dmah->busaddr;
- if (INTEL_INFO(engine->dev)->gen >= 4)
+ if (INTEL_GEN(dev_priv) >= 4)
addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
I915_WRITE(HWS_PGA, addr);
}
static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
i915_reg_t mmio;
/* The ring status page addresses are no longer next to the rest of
* the ring registers as of gen7.
*/
- if (IS_GEN7(dev)) {
+ if (IS_GEN7(dev_priv)) {
switch (engine->id) {
case RCS:
mmio = RENDER_HWS_PGA_GEN7;
@@ -491,7 +489,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
mmio = VEBOX_HWS_PGA_GEN7;
break;
}
- } else if (IS_GEN6(engine->dev)) {
+ } else if (IS_GEN6(dev_priv)) {
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
} else {
/* XXX: gen8 returns to sanity */
@@ -508,7 +506,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
* arises: do we still need this and if so how should we go about
* invalidating the TLB?
*/
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8) {
i915_reg_t reg = RING_INSTPM(engine->mmio_base);
/* ring should be idle before issuing a sync flush*/
@@ -526,9 +524,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
static bool stop_ring(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
- if (!IS_GEN2(engine->dev)) {
+ if (!IS_GEN2(dev_priv)) {
I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
DRM_ERROR("%s : timed out trying to stop ring\n",
@@ -546,7 +544,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
I915_WRITE_HEAD(engine, 0);
engine->write_tail(engine, 0);
- if (!IS_GEN2(engine->dev)) {
+ if (!IS_GEN2(dev_priv)) {
(void)I915_READ_CTL(engine);
I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
}
@@ -561,8 +559,7 @@ void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
static int init_ring_common(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct intel_ringbuffer *ringbuf = engine->buffer;
struct drm_i915_gem_object *obj = ringbuf->obj;
int ret = 0;
@@ -592,7 +589,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
}
}
- if (I915_NEED_GFX_HWS(dev))
+ if (I915_NEED_GFX_HWS(dev_priv))
intel_ring_setup_status_page(engine);
else
ring_setup_phys_status_page(engine);
@@ -649,12 +646,10 @@ out:
void
intel_fini_pipe_control(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
-
if (engine->scratch.obj == NULL)
return;
- if (INTEL_INFO(dev)->gen >= 5) {
+ if (INTEL_GEN(engine->i915) >= 5) {
kunmap(sg_page(engine->scratch.obj->pages->sgl));
i915_gem_object_ggtt_unpin(engine->scratch.obj);
}
@@ -670,7 +665,7 @@ intel_init_pipe_control(struct intel_engine_cs *engine)
WARN_ON(engine->scratch.obj);
- engine->scratch.obj = i915_gem_object_create(engine->dev, 4096);
+ engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
if (IS_ERR(engine->scratch.obj)) {
DRM_ERROR("Failed to allocate seqno page\n");
ret = PTR_ERR(engine->scratch.obj);
@@ -708,11 +703,9 @@ err:
static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
- int ret, i;
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct i915_workarounds *w = &dev_priv->workarounds;
+ struct i915_workarounds *w = &req->i915->workarounds;
+ int ret, i;
if (w->count == 0)
return 0;
@@ -801,7 +794,7 @@ static int wa_add(struct drm_i915_private *dev_priv,
static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
i915_reg_t reg)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
struct i915_workarounds *wa = &dev_priv->workarounds;
const uint32_t index = wa->hw_whitelist_count[engine->id];
@@ -817,8 +810,7 @@ static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
static int gen8_init_workarounds(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
@@ -869,9 +861,8 @@ static int gen8_init_workarounds(struct intel_engine_cs *engine)
static int bdw_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen8_init_workarounds(engine);
if (ret)
@@ -891,16 +882,15 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
/* WaForceContextSaveRestoreNonCoherent:bdw */
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
- (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
+ (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
return 0;
}
static int chv_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen8_init_workarounds(engine);
if (ret)
@@ -917,8 +907,7 @@ static int chv_init_workarounds(struct intel_engine_cs *engine)
static int gen9_init_workarounds(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
uint32_t tmp;
int ret;
@@ -941,14 +930,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_DG_MIRROR_FIX_ENABLE);
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
GEN9_RHWO_OPTIMIZATION_DISABLE);
/*
@@ -974,20 +963,20 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
GEN9_CCS_TLB_PREFETCH_ENABLE);
/* WaDisableMaskBasedCammingInRCC:skl,bxt */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE);
/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
- if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
- IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_F0, REVID_FOREVER) ||
+ IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
- if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
+ if (IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
@@ -1013,8 +1002,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
u8 vals[3] = { 0, 0, 0 };
unsigned int i;
@@ -1055,9 +1043,8 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
static int skl_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen9_init_workarounds(engine);
if (ret)
@@ -1068,12 +1055,12 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
* until D0 which is the default case so this is equivalent to
* !WaDisablePerCtxtPreemptionGranularityControl:skl
*/
- if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
- if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
I915_WRITE(FF_SLICE_CS_CHICKEN2,
_MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
@@ -1082,24 +1069,24 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
* involving this register should also be added to WA batch as required.
*/
- if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
/* WaDisableLSQCROPERFforOCL:skl */
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_RO_PERF_DIS);
/* WaEnableGapsTsvCreditFix:skl */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN9_GAPS_TSV_CREDIT_DISABLE));
}
/* WaDisablePowerCompilerClockGating:skl */
- if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
WA_SET_BIT_MASKED(HIZ_CHICKEN,
BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
/* This is tied to WaForceContextSaveRestoreNonCoherent */
- if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
+ if (IS_SKL_REVID(dev_priv, 0, REVID_FOREVER)) {
/*
*Use Force Non-Coherent whenever executing a 3D context. This
* is a workaround for a possible hang in the unlikely event
@@ -1115,13 +1102,13 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
}
/* WaBarrierPerformanceFixDisable:skl */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
+ if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
WA_SET_BIT_MASKED(HDC_CHICKEN0,
HDC_FENCE_DEST_SLM_DISABLE |
HDC_BARRIER_PERFORMANCE_DISABLE);
/* WaDisableSbeCacheDispatchPortSharing:skl */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
WA_SET_BIT_MASKED(
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
@@ -1136,9 +1123,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
static int bxt_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen9_init_workarounds(engine);
if (ret)
@@ -1146,11 +1132,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaStoreMultiplePTEenable:bxt */
/* This is a requirement according to Hardware specification */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
/* WaSetClckGatingDisableMedia:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
}
@@ -1160,7 +1146,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
STALL_DOP_GATING_DISABLE);
/* WaDisableSbeCacheDispatchPortSharing:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
WA_SET_BIT_MASKED(
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
@@ -1170,7 +1156,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
/* WaDisableObjectLevelPreemtionForInstanceId:bxt */
/* WaDisableLSQCROPERFforOCL:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
if (ret)
return ret;
@@ -1181,7 +1167,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
}
/* WaProgramL3SqcReg1DefaultForPerf:bxt */
- if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
+ if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
L3_HIGH_PRIO_CREDITS(2));
@@ -1190,24 +1176,23 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
int init_workarounds_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
WARN_ON(engine->id != RCS);
dev_priv->workarounds.count = 0;
dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
- if (IS_BROADWELL(dev))
+ if (IS_BROADWELL(dev_priv))
return bdw_init_workarounds(engine);
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
return chv_init_workarounds(engine);
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(dev_priv))
return skl_init_workarounds(engine);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
return bxt_init_workarounds(engine);
return 0;
@@ -1215,14 +1200,13 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
static int init_render_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
int ret = init_ring_common(engine);
if (ret)
return ret;
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
- if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
+ if (INTEL_GEN(dev_priv) >= 4 && INTEL_GEN(dev_priv) < 7)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
/* We need to disable the AsyncFlip performance optimisations in order
@@ -1231,22 +1215,22 @@ static int init_render_ring(struct intel_engine_cs *engine)
*
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
*/
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
+ if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
/* Required for the hardware to program scanline values for waiting */
/* WaEnableFlushTlbInvalidationMode:snb */
- if (INTEL_INFO(dev)->gen == 6)
+ if (IS_GEN6(dev_priv))
I915_WRITE(GFX_MODE,
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
- if (IS_GEN7(dev))
+ if (IS_GEN7(dev_priv))
I915_WRITE(GFX_MODE_GEN7,
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(dev_priv)) {
/* From the Sandybridge PRM, volume 1 part 3, page 24:
* "If this bit is set, STCunit will have LRA as replacement
* policy. [...] This bit must be reset. LRA replacement
@@ -1256,19 +1240,18 @@ static int init_render_ring(struct intel_engine_cs *engine)
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
}
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
+ if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
- if (HAS_L3_DPF(dev))
- I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
+ if (HAS_L3_DPF(dev_priv))
+ I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
return init_workarounds_ring(engine);
}
static void render_ring_cleanup(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
if (dev_priv->semaphore_obj) {
i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
@@ -1284,13 +1267,12 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
{
#define MBOX_UPDATE_DWORDS 8
struct intel_engine_cs *signaller = signaller_req->engine;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
#undef MBOX_UPDATE_DWORDS
@@ -1326,13 +1308,12 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
{
#define MBOX_UPDATE_DWORDS 6
struct intel_engine_cs *signaller = signaller_req->engine;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
#undef MBOX_UPDATE_DWORDS
@@ -1365,14 +1346,13 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
struct intel_engine_cs *signaller = signaller_req->engine;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *useless;
enum intel_engine_id id;
int ret, num_rings;
#define MBOX_UPDATE_DWORDS 3
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
#undef MBOX_UPDATE_DWORDS
@@ -1460,10 +1440,9 @@ gen8_render_add_request(struct drm_i915_gem_request *req)
return 0;
}
-static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
+static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
u32 seqno)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
return dev_priv->last_seqno < seqno;
}
@@ -1481,7 +1460,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
u32 seqno)
{
struct intel_engine_cs *waiter = waiter_req->engine;
- struct drm_i915_private *dev_priv = waiter->dev->dev_private;
+ struct drm_i915_private *dev_priv = waiter_req->i915;
struct i915_hw_ppgtt *ppgtt;
int ret;
@@ -1535,7 +1514,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
return ret;
/* If seqno wrap happened, omit the wait with no-ops */
- if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
+ if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
intel_ring_emit(waiter, dw1 | wait_mbox);
intel_ring_emit(waiter, seqno);
intel_ring_emit(waiter, 0);
@@ -1616,7 +1595,7 @@ pc_render_add_request(struct drm_i915_gem_request *req)
static void
gen6_seqno_barrier(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
/* Workaround to force correct ordering between irq and seqno writes on
* ivb (and maybe also on snb) by reading from a CS register (like
@@ -1665,8 +1644,7 @@ pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
static bool
gen5_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1683,8 +1661,7 @@ gen5_ring_get_irq(struct intel_engine_cs *engine)
static void
gen5_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1696,8 +1673,7 @@ gen5_ring_put_irq(struct intel_engine_cs *engine)
static bool
i9xx_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (!intel_irqs_enabled(dev_priv))
@@ -1717,8 +1693,7 @@ i9xx_ring_get_irq(struct intel_engine_cs *engine)
static void
i9xx_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1733,8 +1708,7 @@ i9xx_ring_put_irq(struct intel_engine_cs *engine)
static bool
i8xx_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (!intel_irqs_enabled(dev_priv))
@@ -1754,8 +1728,7 @@ i8xx_ring_get_irq(struct intel_engine_cs *engine)
static void
i8xx_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1808,8 +1781,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
static bool
gen6_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1817,10 +1789,10 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (engine->irq_refcount++ == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS)
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
I915_WRITE_IMR(engine,
~(engine->irq_enable_mask |
- GT_PARITY_ERROR(dev)));
+ GT_PARITY_ERROR(dev_priv)));
else
I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
@@ -1833,14 +1805,13 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
static void
gen6_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--engine->irq_refcount == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS)
- I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
+ I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
else
I915_WRITE_IMR(engine, ~0);
gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
@@ -1851,8 +1822,7 @@ gen6_ring_put_irq(struct intel_engine_cs *engine)
static bool
hsw_vebox_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1871,8 +1841,7 @@ hsw_vebox_get_irq(struct intel_engine_cs *engine)
static void
hsw_vebox_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1886,8 +1855,7 @@ hsw_vebox_put_irq(struct intel_engine_cs *engine)
static bool
gen8_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1895,7 +1863,7 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (engine->irq_refcount++ == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS) {
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
I915_WRITE_IMR(engine,
~(engine->irq_enable_mask |
GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
@@ -1912,13 +1880,12 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
static void
gen8_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--engine->irq_refcount == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS) {
+ if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
I915_WRITE_IMR(engine,
~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
} else {
@@ -2040,12 +2007,12 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
static void cleanup_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
if (!dev_priv->status_page_dmah)
return;
- drm_pci_free(engine->dev, dev_priv->status_page_dmah);
+ drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
engine->status_page.page_addr = NULL;
}
@@ -2071,7 +2038,7 @@ static int init_status_page(struct intel_engine_cs *engine)
unsigned flags;
int ret;
- obj = i915_gem_object_create(engine->dev, 4096);
+ obj = i915_gem_object_create(engine->i915->dev, 4096);
if (IS_ERR(obj)) {
DRM_ERROR("Failed to allocate status page\n");
return PTR_ERR(obj);
@@ -2082,7 +2049,7 @@ static int init_status_page(struct intel_engine_cs *engine)
goto err_unref;
flags = 0;
- if (!HAS_LLC(engine->dev))
+ if (!HAS_LLC(engine->i915))
/* On g33, we cannot place HWS above 256MiB, so
* restrict its pinning to the low mappable arena.
* Though this restriction is not documented for
@@ -2116,11 +2083,11 @@ err_unref:
static int init_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
if (!dev_priv->status_page_dmah) {
dev_priv->status_page_dmah =
- drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
+ drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
if (!dev_priv->status_page_dmah)
return -ENOMEM;
}
@@ -2146,10 +2113,9 @@ void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
ringbuf->vma = NULL;
}
-int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
+int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
struct intel_ringbuffer *ringbuf)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_object *obj = ringbuf->obj;
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
unsigned flags = PIN_OFFSET_BIAS | 4096;
@@ -2248,13 +2214,13 @@ intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
* of the buffer.
*/
ring->effective_size = size;
- if (IS_I830(engine->dev) || IS_845G(engine->dev))
+ if (IS_I830(engine->i915) || IS_845G(engine->i915))
ring->effective_size -= 2 * CACHELINE_BYTES;
ring->last_retired_head = -1;
intel_ring_update_space(ring);
- ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
+ ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
if (ret) {
DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
engine->name, ret);
@@ -2277,12 +2243,13 @@ intel_ringbuffer_free(struct intel_ringbuffer *ring)
static int intel_init_ring_buffer(struct drm_device *dev,
struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_ringbuffer *ringbuf;
int ret;
WARN_ON(engine->buffer);
- engine->dev = dev;
+ engine->i915 = dev_priv;
INIT_LIST_HEAD(&engine->active_list);
INIT_LIST_HEAD(&engine->request_list);
INIT_LIST_HEAD(&engine->execlist_queue);
@@ -2300,7 +2267,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
}
engine->buffer = ringbuf;
- if (I915_NEED_GFX_HWS(dev)) {
+ if (I915_NEED_GFX_HWS(dev_priv)) {
ret = init_status_page(engine);
if (ret)
goto error;
@@ -2311,7 +2278,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
goto error;
}
- ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
+ ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
if (ret) {
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
engine->name, ret);
@@ -2337,11 +2304,11 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
if (!intel_engine_initialized(engine))
return;
- dev_priv = to_i915(engine->dev);
+ dev_priv = engine->i915;
if (engine->buffer) {
intel_stop_engine(engine);
- WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
+ WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
intel_unpin_ringbuffer_obj(engine->buffer);
intel_ringbuffer_free(engine->buffer);
@@ -2351,7 +2318,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
if (engine->cleanup)
engine->cleanup(engine);
- if (I915_NEED_GFX_HWS(engine->dev)) {
+ if (I915_NEED_GFX_HWS(dev_priv)) {
cleanup_status_page(engine);
} else {
WARN_ON(engine->id != RCS);
@@ -2360,7 +2327,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
i915_cmd_parser_fini_ring(engine);
i915_gem_batch_pool_fini(&engine->batch_pool);
- engine->dev = NULL;
+ engine->i915 = NULL;
}
int intel_engine_idle(struct intel_engine_cs *engine)
@@ -2526,7 +2493,7 @@ int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = engine->i915;
/* Our semaphore implementation is strictly monotonic (i.e. we proceed
* so long as the semaphore value in the register/page is greater
@@ -2562,7 +2529,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
u32 value)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
/* Every tail move must follow the sequence below */
@@ -2604,7 +2571,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
return ret;
cmd = MI_FLUSH_DW;
- if (INTEL_INFO(engine->dev)->gen >= 8)
+ if (INTEL_GEN(req->i915) >= 8)
cmd += 1;
/* We always require a command barrier so that subsequent
@@ -2626,7 +2593,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
intel_ring_emit(engine, cmd);
intel_ring_emit(engine,
I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (INTEL_INFO(engine->dev)->gen >= 8) {
+ if (INTEL_GEN(req->i915) >= 8) {
intel_ring_emit(engine, 0); /* upper addr */
intel_ring_emit(engine, 0); /* value */
} else {
@@ -2717,7 +2684,6 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
uint32_t cmd;
int ret;
@@ -2726,7 +2692,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
return ret;
cmd = MI_FLUSH_DW;
- if (INTEL_INFO(dev)->gen >= 8)
+ if (INTEL_GEN(req->i915) >= 8)
cmd += 1;
/* We always require a command barrier so that subsequent
@@ -2747,7 +2713,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
intel_ring_emit(engine, cmd);
intel_ring_emit(engine,
I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(req->i915) >= 8) {
intel_ring_emit(engine, 0); /* upper addr */
intel_ring_emit(engine, 0); /* value */
} else {
@@ -2772,8 +2738,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->hw_id = 0;
engine->mmio_base = RENDER_RING_BASE;
- if (INTEL_INFO(dev)->gen >= 8) {
- if (i915_semaphore_is_enabled(dev)) {
+ if (INTEL_GEN(dev_priv) >= 8) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
obj = i915_gem_object_create(dev, 4096);
if (IS_ERR(obj)) {
DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
@@ -2798,17 +2764,17 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
WARN_ON(!dev_priv->semaphore_obj);
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_rcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
}
- } else if (INTEL_INFO(dev)->gen >= 6) {
+ } else if (INTEL_GEN(dev_priv) >= 6) {
engine->init_context = intel_rcs_ctx_init;
engine->add_request = gen6_add_request;
engine->flush = gen7_render_ring_flush;
- if (INTEL_INFO(dev)->gen == 6)
+ if (IS_GEN6(dev_priv))
engine->flush = gen6_render_ring_flush;
engine->irq_get = gen6_ring_get_irq;
engine->irq_put = gen6_ring_put_irq;
@@ -2816,7 +2782,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
/*
@@ -2837,7 +2803,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
}
- } else if (IS_GEN5(dev)) {
+ } else if (IS_GEN5(dev_priv)) {
engine->add_request = pc_render_add_request;
engine->flush = gen4_render_ring_flush;
engine->get_seqno = pc_render_get_seqno;
@@ -2848,13 +2814,13 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
} else {
engine->add_request = i9xx_add_request;
- if (INTEL_INFO(dev)->gen < 4)
+ if (INTEL_GEN(dev_priv) < 4)
engine->flush = gen2_render_ring_flush;
else
engine->flush = gen4_render_ring_flush;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (IS_GEN2(dev)) {
+ if (IS_GEN2(dev_priv)) {
engine->irq_get = i8xx_ring_get_irq;
engine->irq_put = i8xx_ring_put_irq;
} else {
@@ -2865,15 +2831,15 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
}
engine->write_tail = ring_write_tail;
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev_priv))
engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
- else if (IS_GEN8(dev))
+ else if (IS_GEN8(dev_priv))
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- else if (INTEL_INFO(dev)->gen >= 6)
+ else if (INTEL_GEN(dev_priv) >= 6)
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- else if (INTEL_INFO(dev)->gen >= 4)
+ else if (INTEL_GEN(dev_priv) >= 4)
engine->dispatch_execbuffer = i965_dispatch_execbuffer;
- else if (IS_I830(dev) || IS_845G(dev))
+ else if (IS_I830(dev_priv) || IS_845G(dev_priv))
engine->dispatch_execbuffer = i830_dispatch_execbuffer;
else
engine->dispatch_execbuffer = i915_dispatch_execbuffer;
@@ -2881,7 +2847,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->cleanup = render_ring_cleanup;
/* Workaround batchbuffer to combat CS tlb bug. */
- if (HAS_BROKEN_CS_TLB(dev)) {
+ if (HAS_BROKEN_CS_TLB(dev_priv)) {
obj = i915_gem_object_create(dev, I830_WA_SIZE);
if (IS_ERR(obj)) {
DRM_ERROR("Failed to allocate batch bo\n");
@@ -2903,7 +2869,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
if (ret)
return ret;
- if (INTEL_INFO(dev)->gen >= 5) {
+ if (INTEL_GEN(dev_priv) >= 5) {
ret = intel_init_pipe_control(engine);
if (ret)
return ret;
@@ -2923,24 +2889,24 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->hw_id = 1;
engine->write_tail = ring_write_tail;
- if (INTEL_INFO(dev)->gen >= 6) {
+ if (INTEL_GEN(dev_priv) >= 6) {
engine->mmio_base = GEN6_BSD_RING_BASE;
/* gen6 bsd needs a special wa for tail updates */
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
engine->write_tail = gen6_bsd_ring_write_tail;
engine->flush = gen6_bsd_ring_flush;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
engine->irq_get = gen8_ring_get_irq;
engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
@@ -2951,7 +2917,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->irq_put = gen6_ring_put_irq;
engine->dispatch_execbuffer =
gen6_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
@@ -2972,7 +2938,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->add_request = i9xx_add_request;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (IS_GEN5(dev)) {
+ if (IS_GEN5(dev_priv)) {
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
engine->irq_get = gen5_ring_get_irq;
engine->irq_put = gen5_ring_put_irq;
@@ -3014,7 +2980,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
@@ -3041,13 +3007,13 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
engine->irq_get = gen8_ring_get_irq;
engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
@@ -3057,7 +3023,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
engine->irq_get = gen6_ring_get_irq;
engine->irq_put = gen6_ring_put_irq;
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.signal = gen6_signal;
engine->semaphore.sync_to = gen6_ring_sync;
/*
@@ -3102,13 +3068,13 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
engine->irq_get = gen8_ring_get_irq;
engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
@@ -3118,7 +3084,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
engine->irq_get = hsw_vebox_get_irq;
engine->irq_put = hsw_vebox_put_irq;
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 723ff6160fbb..929e7b4af2a4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -141,7 +141,8 @@ struct i915_ctx_workarounds {
struct drm_i915_gem_object *obj;
};
-struct intel_engine_cs {
+struct intel_engine_cs {
+ struct drm_i915_private *i915;
const char *name;
enum intel_engine_id {
RCS = 0,
@@ -156,7 +157,6 @@ struct intel_engine_cs {
unsigned int hw_id;
unsigned int guc_id; /* XXX same as hw_id? */
u32 mmio_base;
- struct drm_device *dev;
struct intel_ringbuffer *buffer;
struct list_head buffers;
@@ -350,7 +350,7 @@ struct intel_engine_cs {
static inline bool
intel_engine_initialized(struct intel_engine_cs *engine)
{
- return engine->dev != NULL;
+ return engine->i915 != NULL;
}
static inline unsigned
@@ -425,7 +425,7 @@ intel_write_status_page(struct intel_engine_cs *engine,
struct intel_ringbuffer *
intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
-int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
+int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
struct intel_ringbuffer *ringbuf);
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
void intel_ringbuffer_free(struct intel_ringbuffer *ring);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 4f1dfe616856..4ea2bf2c2a4a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1381,7 +1381,7 @@ void intel_uncore_init(struct drm_device *dev)
break;
}
- if (intel_vgpu_active(dev)) {
+ if (intel_vgpu_active(dev_priv)) {
ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
ASSIGN_READ_MMIO_VFUNCS(vgpu);
}
@@ -1663,8 +1663,8 @@ static int wait_for_register_fw(struct drm_i915_private *dev_priv,
static int gen8_request_engine_reset(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
@@ -1682,7 +1682,7 @@ static int gen8_request_engine_reset(struct intel_engine_cs *engine)
static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = engine->i915;
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
@@ -1802,10 +1802,10 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
{
enum forcewake_domains fw_domains;
- if (intel_vgpu_active(dev_priv->dev))
+ if (intel_vgpu_active(dev_priv))
return 0;
- switch (INTEL_INFO(dev_priv)->gen) {
+ switch (INTEL_GEN(dev_priv)) {
case 9:
fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg));
break;
@@ -1842,10 +1842,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
{
enum forcewake_domains fw_domains;
- if (intel_vgpu_active(dev_priv->dev))
+ if (intel_vgpu_active(dev_priv))
return 0;
- switch (INTEL_INFO(dev_priv)->gen) {
+ switch (INTEL_GEN(dev_priv)) {
case 9:
fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
break;
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 02/19] drm/i915/execlists: Refactor common engine setup
2016-05-05 11:17 ` Tvrtko Ursulin
@ 2016-05-05 11:55 ` Tvrtko Ursulin
0 siblings, 0 replies; 27+ messages in thread
From: Tvrtko Ursulin @ 2016-05-05 11:55 UTC (permalink / raw)
To: Chris Wilson, intel-gfx, Dave Gordon
On 05/05/16 12:17, Tvrtko Ursulin wrote:
>
> On 05/05/16 11:33, Chris Wilson wrote:
>> On Thu, May 05, 2016 at 11:18:41AM +0100, Tvrtko Ursulin wrote:
>>>
>>> Hi,
>>>
>>> On 05/05/16 10:15, Chris Wilson wrote:
>>>> Move all of the constant assignments up front and into a common
>>>> function. This is primarily to ensure the backpointers are set as early
>>>> as possible for later use during initialisation.
>>>>
>>>> v2: Use a constant struct so that all the similar values are set
>>>> together.
>>>> v3: Sanitize the engine's IMR to disable any potential interrupt before
>>>> we are ready (enabled in init_hw).
>>>
>>> Same as before - I don't like hardware access in this code path
>>> since we otherwise have it split into a later init_hw phase. And I
>>> don't like engine->dev being used for intel_engine_initialized.
>>
>> I think you raised a good point on the last round! It is an oversight
>> that we have not explicitly sanitized the per-engine registers as is our
>> mo. This gives us the symmetry with the init_hw phase where they are
>> enabled.
>>
>>> On retrospect, interrupt vs engine->irq_queue race is already there
>>> now, for the render ring at least. So maybe just drop the IMR bit
>>> which would make the patch pure refactoring and can have my R-b
>>> then.
>>
>> And this closes a race with a potential interrupt pending from takeover.
>
> Okay but whether or not I have raised a good point I think it wouldn't
> harm to split the pure refactoring from functional changes. You get at
> least one R-b like that. ;)
On the other hand, what I called pure refactoring is also adding the
race window to other engines. So don't know.. engine->initialized? :) It
doesn't look like anything in setup depends on it being true.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2] drm/i915: Store a i915 backpointer from engine, and use it
2016-05-05 11:37 ` [PATCH v2] " Chris Wilson
@ 2016-05-05 12:54 ` Tvrtko Ursulin
0 siblings, 0 replies; 27+ messages in thread
From: Tvrtko Ursulin @ 2016-05-05 12:54 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 05/05/16 12:37, Chris Wilson wrote:
> text data bss dec hex filename
> 6309351 3578714 696320 10584385 a18141 vmlinux
> 6308391 3578714 696320 10583425 a17d81 vmlinux
>
> Almost 1KiB of code reduction.
>
> v2: More s/INTEL_INFO()->gen/INTEL_GEN()/ and IS_GENx() conversions
>
> text data bss dec hex filename
> 6304579 3578778 696320 10579677 a16edd vmlinux
> 6303427 3578778 696320 10578525 a16a5d vmlinux
>
> Now over 1KiB!
I'll assume you didn't plant any backdoors in v2 so r-b still applies. :)
Regards,
Tvrtko
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 12 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
> drivers/gpu/drm/i915/i915_dma.c | 9 +-
> drivers/gpu/drm/i915/i915_drv.c | 10 +-
> drivers/gpu/drm/i915/i915_drv.h | 35 +--
> drivers/gpu/drm/i915/i915_gem.c | 47 ++--
> drivers/gpu/drm/i915/i915_gem_context.c | 48 ++--
> drivers/gpu/drm/i915/i915_gem_evict.c | 4 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +--
> drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +-
> drivers/gpu/drm/i915/i915_gem_shrinker.c | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 79 +++----
> drivers/gpu/drm/i915/i915_irq.c | 80 ++++---
> drivers/gpu/drm/i915/i915_trace.h | 36 ++-
> drivers/gpu/drm/i915/intel_display.c | 49 ++--
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_lrc.c | 139 ++++++------
> drivers/gpu/drm/i915/intel_lrc.h | 3 +-
> drivers/gpu/drm/i915/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/intel_overlay.c | 3 +-
> drivers/gpu/drm/i915/intel_pm.c | 5 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 328 ++++++++++++---------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 8 +-
> drivers/gpu/drm/i915/intel_uncore.c | 14 +-
> 26 files changed, 461 insertions(+), 519 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 69a1ba8ebdfb..35224ea30201 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -750,12 +750,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
> int cmd_table_count;
> int ret;
>
> - if (!IS_GEN7(engine->dev))
> + if (!IS_GEN7(engine->i915))
> return 0;
>
> switch (engine->id) {
> case RCS:
> - if (IS_HASWELL(engine->dev)) {
> + if (IS_HASWELL(engine->i915)) {
> cmd_tables = hsw_render_ring_cmds;
> cmd_table_count =
> ARRAY_SIZE(hsw_render_ring_cmds);
> @@ -764,7 +764,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
> cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
> }
>
> - if (IS_HASWELL(engine->dev)) {
> + if (IS_HASWELL(engine->i915)) {
> engine->reg_tables = hsw_render_reg_tables;
> engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
> } else {
> @@ -780,7 +780,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
> engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
> break;
> case BCS:
> - if (IS_HASWELL(engine->dev)) {
> + if (IS_HASWELL(engine->i915)) {
> cmd_tables = hsw_blt_ring_cmds;
> cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
> } else {
> @@ -788,7 +788,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
> cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
> }
>
> - if (IS_HASWELL(engine->dev)) {
> + if (IS_HASWELL(engine->i915)) {
> engine->reg_tables = hsw_blt_reg_tables;
> engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
> } else {
> @@ -1035,7 +1035,7 @@ bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
> if (!engine->needs_cmd_parser)
> return false;
>
> - if (!USES_PPGTT(engine->dev))
> + if (!USES_PPGTT(engine->i915))
> return false;
>
> return (i915.enable_cmd_parser == 1);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6ad008c196b5..6698957ede3f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1383,7 +1383,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
> seqno[id] = engine->get_seqno(engine);
> }
>
> - i915_get_extra_instdone(dev, instdone);
> + i915_get_extra_instdone(dev_priv, instdone);
>
> intel_runtime_pm_put(dev_priv);
>
> @@ -3165,7 +3165,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused)
> enum intel_engine_id id;
> int j, ret;
>
> - if (!i915_semaphore_is_enabled(dev)) {
> + if (!i915_semaphore_is_enabled(dev_priv)) {
> seq_puts(m, "Semaphores are disabled\n");
> return 0;
> }
> @@ -4766,7 +4766,7 @@ i915_wedged_set(void *data, u64 val)
>
> intel_runtime_pm_get(dev_priv);
>
> - i915_handle_error(dev, val,
> + i915_handle_error(dev_priv, val,
> "Manually setting wedged to %llu", val);
>
> intel_runtime_pm_put(dev_priv);
> @@ -4916,7 +4916,7 @@ i915_drop_caches_set(void *data, u64 val)
> }
>
> if (val & (DROP_RETIRE | DROP_ACTIVE))
> - i915_gem_retire_requests(dev);
> + i915_gem_retire_requests(dev_priv);
>
> if (val & DROP_BOUND)
> i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index ad7abe517700..46ac1da64a09 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -186,7 +186,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
> value = 1;
> break;
> case I915_PARAM_HAS_SEMAPHORES:
> - value = i915_semaphore_is_enabled(dev);
> + value = i915_semaphore_is_enabled(dev_priv);
> break;
> case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
> value = 1;
> @@ -970,7 +970,8 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> info->has_eu_pg ? "y" : "n");
>
> i915.enable_execlists =
> - intel_sanitize_enable_execlists(dev, i915.enable_execlists);
> + intel_sanitize_enable_execlists(dev_priv,
> + i915.enable_execlists);
>
> /*
> * i915.enable_ppgtt is read-only, so do an early pass to validate the
> @@ -979,7 +980,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> * than every time we check intel_enable_ppgtt().
> */
> i915.enable_ppgtt =
> - intel_sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
> + intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
> DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
> }
>
> @@ -1345,7 +1346,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
> * Notify a valid surface after modesetting,
> * when running inside a VM.
> */
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
>
> i915_setup_sysfs(dev);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 9fd221c97275..ffbc61e9ff62 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -530,9 +530,9 @@ void intel_detect_pch(struct drm_device *dev)
> pci_dev_put(pch);
> }
>
> -bool i915_semaphore_is_enabled(struct drm_device *dev)
> +bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
> {
> - if (INTEL_INFO(dev)->gen < 6)
> + if (INTEL_GEN(dev_priv) < 6)
> return false;
>
> if (i915.semaphores >= 0)
> @@ -544,7 +544,7 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
>
> #ifdef CONFIG_INTEL_IOMMU
> /* Enable semaphores on SNB when IO remapping is off */
> - if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
> + if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped)
> return false;
> #endif
>
> @@ -914,9 +914,9 @@ int i915_resume_switcheroo(struct drm_device *dev)
> * - re-init interrupt state
> * - re-init display
> */
> -int i915_reset(struct drm_device *dev)
> +int i915_reset(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_device *dev = dev_priv->dev;
> struct i915_gpu_error *error = &dev_priv->gpu_error;
> unsigned reset_counter;
> int ret;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d5496aba1cd5..c26fdf021104 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2754,7 +2754,8 @@ extern int i915_max_ioctl;
> extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
> extern int i915_resume_switcheroo(struct drm_device *dev);
>
> -int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt);
> +int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> + int enable_ppgtt);
>
> /* i915_dma.c */
> void __printf(3, 4)
> @@ -2778,7 +2779,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
> #endif
> extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
> extern bool intel_has_gpu_reset(struct drm_device *dev);
> -extern int i915_reset(struct drm_device *dev);
> +extern int i915_reset(struct drm_i915_private *dev_priv);
> extern int intel_guc_reset(struct drm_i915_private *dev_priv);
> extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
> extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
> @@ -2795,9 +2796,10 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
> bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
>
> /* i915_irq.c */
> -void i915_queue_hangcheck(struct drm_device *dev);
> +void i915_queue_hangcheck(struct drm_i915_private *dev_priv);
> __printf(3, 4)
> -void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> +void i915_handle_error(struct drm_i915_private *dev_priv,
> + u32 engine_mask,
> const char *fmt, ...);
>
> extern void intel_irq_init(struct drm_i915_private *dev_priv);
> @@ -2827,9 +2829,9 @@ void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
> u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
>
> void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
> -static inline bool intel_vgpu_active(struct drm_device *dev)
> +static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
> {
> - return to_i915(dev)->vgpu.active;
> + return dev_priv->vgpu.active;
> }
>
> void
> @@ -3097,13 +3099,13 @@ static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
> req->seqno);
> }
>
> -int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
> +int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno);
> int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
>
> struct drm_i915_gem_request *
> i915_gem_find_active_request(struct intel_engine_cs *engine);
>
> -bool i915_gem_retire_requests(struct drm_device *dev);
> +bool i915_gem_retire_requests(struct drm_i915_private *dev_priv);
> void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
>
> static inline u32 i915_reset_counter(struct i915_gpu_error *error)
> @@ -3350,9 +3352,9 @@ int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
> int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
>
> /* belongs in i915_gem_gtt.h */
> -static inline void i915_gem_chipset_flush(struct drm_device *dev)
> +static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
> {
> - if (INTEL_INFO(dev)->gen < 6)
> + if (INTEL_GEN(dev_priv) < 6)
> intel_gtt_chipset_flush();
> }
>
> @@ -3431,14 +3433,15 @@ static inline void i915_error_state_buf_release(
> {
> kfree(eb->buf);
> }
> -void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
> +void i915_capture_error_state(struct drm_i915_private *dev_priv,
> + u32 engine_mask,
> const char *error_msg);
> void i915_error_state_get(struct drm_device *dev,
> struct i915_error_state_file_priv *error_priv);
> void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
> void i915_destroy_error_state(struct drm_device *dev);
>
> -void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
> +void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
> const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
>
> /* i915_cmd_parser.c */
> @@ -3546,18 +3549,20 @@ extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
> extern void intel_detect_pch(struct drm_device *dev);
> extern int intel_enable_rc6(const struct drm_device *dev);
>
> -extern bool i915_semaphore_is_enabled(struct drm_device *dev);
> +extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
> int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
>
> /* overlay */
> -extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
> +extern struct intel_overlay_error_state *
> +intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
> extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
> struct intel_overlay_error_state *error);
>
> -extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
> +extern struct intel_display_error_state *
> +intel_display_capture_error_state(struct drm_i915_private *dev_priv);
> extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
> struct drm_device *dev,
> struct intel_display_error_state *error);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index a88e6c9e9516..c99d1b2c65d4 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -177,7 +177,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
> vaddr += PAGE_SIZE;
> }
>
> - i915_gem_chipset_flush(obj->base.dev);
> + i915_gem_chipset_flush(to_i915(obj->base.dev));
>
> st = kmalloc(sizeof(*st), GFP_KERNEL);
> if (st == NULL)
> @@ -347,7 +347,7 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
> }
>
> drm_clflush_virt_range(vaddr, args->size);
> - i915_gem_chipset_flush(dev);
> + i915_gem_chipset_flush(to_i915(dev));
>
> out:
> intel_fb_obj_flush(obj, false, ORIGIN_CPU);
> @@ -1006,7 +1006,7 @@ out:
> }
>
> if (needs_clflush_after)
> - i915_gem_chipset_flush(dev);
> + i915_gem_chipset_flush(to_i915(dev));
> else
> obj->cache_dirty = true;
>
> @@ -1230,8 +1230,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> struct intel_rps_client *rps)
> {
> struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = req->i915;
> const bool irq_test_in_progress =
> ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
> int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
> @@ -1429,7 +1428,7 @@ __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
> struct intel_engine_cs *engine = req->engine;
> struct drm_i915_gem_request *tmp;
>
> - lockdep_assert_held(&engine->dev->struct_mutex);
> + lockdep_assert_held(&engine->i915->dev->struct_mutex);
>
> if (list_empty(&req->list))
> return;
> @@ -2502,9 +2501,8 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
> }
>
> static int
> -i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
> +i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *engine;
> int ret;
>
> @@ -2514,7 +2512,7 @@ i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
> if (ret)
> return ret;
> }
> - i915_gem_retire_requests(dev);
> + i915_gem_retire_requests(dev_priv);
>
> /* Finally reset hw state */
> for_each_engine(engine, dev_priv)
> @@ -2534,7 +2532,7 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
> /* HWS page needs to be set less than what we
> * will inject to ring
> */
> - ret = i915_gem_init_seqno(dev, seqno - 1);
> + ret = i915_gem_init_seqno(dev_priv, seqno - 1);
> if (ret)
> return ret;
>
> @@ -2550,13 +2548,11 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
> }
>
> int
> -i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
> +i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> /* reserve 0 for non-seqno */
> if (dev_priv->next_seqno == 0) {
> - int ret = i915_gem_init_seqno(dev, 0);
> + int ret = i915_gem_init_seqno(dev_priv, 0);
> if (ret)
> return ret;
>
> @@ -2654,7 +2650,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> /* Not allowed to fail! */
> WARN(ret, "emit|add_request failed: %d!\n", ret);
>
> - i915_queue_hangcheck(engine->dev);
> + i915_queue_hangcheck(engine->i915);
>
> queue_delayed_work(dev_priv->wq,
> &dev_priv->mm.retire_work,
> @@ -2728,7 +2724,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
> struct intel_context *ctx,
> struct drm_i915_gem_request **req_out)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
> struct drm_i915_gem_request *req;
> int ret;
> @@ -2750,7 +2746,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
> if (req == NULL)
> return -ENOMEM;
>
> - ret = i915_gem_get_seqno(engine->dev, &req->seqno);
> + ret = i915_gem_get_seqno(engine->i915, &req->seqno);
> if (ret)
> goto err;
>
> @@ -2807,7 +2803,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
> int err;
>
> if (ctx == NULL)
> - ctx = to_i915(engine->dev)->kernel_context;
> + ctx = engine->i915->kernel_context;
> err = __i915_gem_request_alloc(engine, ctx, &req);
> return err ? ERR_PTR(err) : req;
> }
> @@ -2982,9 +2978,8 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
> }
>
> bool
> -i915_gem_retire_requests(struct drm_device *dev)
> +i915_gem_retire_requests(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *engine;
> bool idle = true;
>
> @@ -3017,7 +3012,7 @@ i915_gem_retire_work_handler(struct work_struct *work)
> /* Come back later if the device is busy... */
> idle = false;
> if (mutex_trylock(&dev->struct_mutex)) {
> - idle = i915_gem_retire_requests(dev);
> + idle = i915_gem_retire_requests(dev_priv);
> mutex_unlock(&dev->struct_mutex);
> }
> if (!idle)
> @@ -3186,7 +3181,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> if (i915_gem_request_completed(from_req, true))
> return 0;
>
> - if (!i915_semaphore_is_enabled(obj->base.dev)) {
> + if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> ret = __i915_wait_request(from_req,
> i915->mm.interruptible,
> @@ -3719,7 +3714,7 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
> return;
>
> if (i915_gem_clflush_object(obj, obj->pin_display))
> - i915_gem_chipset_flush(obj->base.dev);
> + i915_gem_chipset_flush(to_i915(obj->base.dev));
>
> old_write_domain = obj->base.write_domain;
> obj->base.write_domain = 0;
> @@ -3917,7 +3912,7 @@ out:
> obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
> cpu_write_needs_clflush(obj)) {
> if (i915_gem_clflush_object(obj, true))
> - i915_gem_chipset_flush(obj->base.dev);
> + i915_gem_chipset_flush(to_i915(obj->base.dev));
> }
>
> return 0;
> @@ -4695,7 +4690,7 @@ i915_gem_suspend(struct drm_device *dev)
> if (ret)
> goto err;
>
> - i915_gem_retire_requests(dev);
> + i915_gem_retire_requests(dev_priv);
>
> i915_gem_stop_engines(dev);
> i915_gem_context_lost(dev_priv);
> @@ -4986,7 +4981,7 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
> else
> dev_priv->num_fence_regs = 8;
>
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> dev_priv->num_fence_regs =
> I915_READ(vgtif_reg(avail_rs.fence_num));
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index b1b704c2c001..0fffebcc0ace 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -99,28 +99,27 @@
> #define GEN6_CONTEXT_ALIGN (64<<10)
> #define GEN7_CONTEXT_ALIGN 4096
>
> -static size_t get_context_alignment(struct drm_device *dev)
> +static size_t get_context_alignment(struct drm_i915_private *dev_priv)
> {
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> return GEN6_CONTEXT_ALIGN;
>
> return GEN7_CONTEXT_ALIGN;
> }
>
> -static int get_context_size(struct drm_device *dev)
> +static int get_context_size(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> int ret;
> u32 reg;
>
> - switch (INTEL_INFO(dev)->gen) {
> + switch (INTEL_GEN(dev_priv)) {
> case 6:
> reg = I915_READ(CXT_SIZE);
> ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
> break;
> case 7:
> reg = I915_READ(GEN7_CXT_SIZE);
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
> ret = HSW_CXT_TOTAL_SIZE;
> else
> ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
> @@ -224,7 +223,7 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
> * Flush any pending retires to hopefully release some
> * stale contexts and try again.
> */
> - i915_gem_retire_requests(dev_priv->dev);
> + i915_gem_retire_requests(dev_priv);
> ret = ida_simple_get(&dev_priv->context_hw_ida,
> 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
> if (ret < 0)
> @@ -320,7 +319,7 @@ i915_gem_create_context(struct drm_device *dev,
> * context.
> */
> ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
> - get_context_alignment(dev), 0);
> + get_context_alignment(to_i915(dev)), 0);
> if (ret) {
> DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
> goto err_destroy;
> @@ -389,7 +388,8 @@ int i915_gem_context_init(struct drm_device *dev)
> if (WARN_ON(dev_priv->kernel_context))
> return 0;
>
> - if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
> + if (intel_vgpu_active(dev_priv) &&
> + HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
> if (!i915.enable_execlists) {
> DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
> return -EINVAL;
> @@ -404,8 +404,9 @@ int i915_gem_context_init(struct drm_device *dev)
> /* NB: intentionally left blank. We will allocate our own
> * backing objects as we need them, thank you very much */
> dev_priv->hw_context_size = 0;
> - } else if (HAS_HW_CONTEXTS(dev)) {
> - dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
> + } else if (HAS_HW_CONTEXTS(dev_priv)) {
> + dev_priv->hw_context_size =
> + round_up(get_context_size(dev_priv), 4096);
> if (dev_priv->hw_context_size > (1<<20)) {
> DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
> dev_priv->hw_context_size);
> @@ -509,12 +510,13 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
> static inline int
> mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> {
> + struct drm_i915_private *dev_priv = req->i915;
> struct intel_engine_cs *engine = req->engine;
> u32 flags = hw_flags | MI_MM_SPACE_GTT;
> const int num_rings =
> /* Use an extended w/a on ivb+ if signalling from other rings */
> - i915_semaphore_is_enabled(engine->dev) ?
> - hweight32(INTEL_INFO(engine->dev)->ring_mask) - 1 :
> + i915_semaphore_is_enabled(dev_priv) ?
> + hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 :
> 0;
> int len, ret;
>
> @@ -523,21 +525,21 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> * explicitly, so we rely on the value at ring init, stored in
> * itlb_before_ctx_switch.
> */
> - if (IS_GEN6(engine->dev)) {
> + if (IS_GEN6(dev_priv)) {
> ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
> if (ret)
> return ret;
> }
>
> /* These flags are for resource streamer on HSW+ */
> - if (IS_HASWELL(engine->dev) || INTEL_INFO(engine->dev)->gen >= 8)
> + if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
> flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
> - else if (INTEL_INFO(engine->dev)->gen < 8)
> + else if (INTEL_GEN(dev_priv) < 8)
> flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
>
>
> len = 4;
> - if (INTEL_INFO(engine->dev)->gen >= 7)
> + if (INTEL_GEN(dev_priv) >= 7)
> len += 2 + (num_rings ? 4*num_rings + 6 : 0);
>
> ret = intel_ring_begin(req, len);
> @@ -545,14 +547,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> return ret;
>
> /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
> - if (INTEL_INFO(engine->dev)->gen >= 7) {
> + if (INTEL_GEN(dev_priv) >= 7) {
> intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
> if (num_rings) {
> struct intel_engine_cs *signaller;
>
> intel_ring_emit(engine,
> MI_LOAD_REGISTER_IMM(num_rings));
> - for_each_engine(signaller, to_i915(engine->dev)) {
> + for_each_engine(signaller, dev_priv) {
> if (signaller == engine)
> continue;
>
> @@ -575,14 +577,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> */
> intel_ring_emit(engine, MI_NOOP);
>
> - if (INTEL_INFO(engine->dev)->gen >= 7) {
> + if (INTEL_GEN(dev_priv) >= 7) {
> if (num_rings) {
> struct intel_engine_cs *signaller;
> i915_reg_t last_reg = {}; /* keep gcc quiet */
>
> intel_ring_emit(engine,
> MI_LOAD_REGISTER_IMM(num_rings));
> - for_each_engine(signaller, to_i915(engine->dev)) {
> + for_each_engine(signaller, dev_priv) {
> if (signaller == engine)
> continue;
>
> @@ -673,7 +675,7 @@ needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
> if (engine->id != RCS)
> return true;
>
> - if (INTEL_INFO(engine->dev)->gen < 8)
> + if (INTEL_GEN(engine->i915) < 8)
> return true;
>
> return false;
> @@ -710,7 +712,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
>
> /* Trying to pin first makes error handling easier. */
> ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
> - get_context_alignment(engine->dev),
> + get_context_alignment(engine->i915),
> 0);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
> index ea1f8d1bd228..b144c3f5c650 100644
> --- a/drivers/gpu/drm/i915/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/i915_gem_evict.c
> @@ -154,7 +154,7 @@ none:
> if (ret)
> return ret;
>
> - i915_gem_retire_requests(dev);
> + i915_gem_retire_requests(to_i915(dev));
> goto search_again;
> }
>
> @@ -265,7 +265,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle)
> if (ret)
> return ret;
>
> - i915_gem_retire_requests(vm->dev);
> + i915_gem_retire_requests(to_i915(vm->dev));
>
> WARN_ON(!list_empty(&vm->active_list));
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index e0ee5d1ac372..a54a243ccaac 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -724,7 +724,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
> struct i915_address_space *vm;
> struct list_head ordered_vmas;
> struct list_head pinned_vmas;
> - bool has_fenced_gpu_access = INTEL_INFO(engine->dev)->gen < 4;
> + bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
> int retry;
>
> i915_gem_retire_requests_ring(engine);
> @@ -965,7 +965,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
> }
>
> if (flush_chipset)
> - i915_gem_chipset_flush(req->engine->dev);
> + i915_gem_chipset_flush(req->engine->i915);
>
> if (flush_domains & I915_GEM_DOMAIN_GTT)
> wmb();
> @@ -1119,7 +1119,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
> if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
> i915_gem_request_assign(&obj->last_fenced_req, req);
> if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
> list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
> &dev_priv->mm.fence_list);
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 364cf8236021..3c474d594f47 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -110,17 +110,19 @@ const struct i915_ggtt_view i915_ggtt_view_rotated = {
> .type = I915_GGTT_VIEW_ROTATED,
> };
>
> -int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
> +int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> + int enable_ppgtt)
> {
> bool has_aliasing_ppgtt;
> bool has_full_ppgtt;
> bool has_full_48bit_ppgtt;
>
> - has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
> - has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
> - has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
> + has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6;
> + has_full_ppgtt = INTEL_GEN(dev_priv) >= 7;
> + has_full_48bit_ppgtt =
> + IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;
>
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> has_full_ppgtt = false; /* emulation is too hard */
>
> if (!has_aliasing_ppgtt)
> @@ -130,7 +132,7 @@ int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
> * We don't allow disabling PPGTT for gen9+ as it's a requirement for
> * execlists, the sole mechanism available to submit work.
> */
> - if (enable_ppgtt == 0 && INTEL_INFO(dev)->gen < 9)
> + if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
> return 0;
>
> if (enable_ppgtt == 1)
> @@ -144,19 +146,19 @@ int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>
> #ifdef CONFIG_INTEL_IOMMU
> /* Disable ppgtt on SNB if VT-d is on. */
> - if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
> + if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) {
> DRM_INFO("Disabling PPGTT because VT-d is on\n");
> return 0;
> }
> #endif
>
> /* Early VLV doesn't have this */
> - if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
> + if (IS_VALLEYVIEW(dev_priv) && dev_priv->dev->pdev->revision < 0xb) {
> DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
> return 0;
> }
>
> - if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
> + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists)
> return has_full_48bit_ppgtt ? 3 : 2;
> else
> return has_aliasing_ppgtt ? 1 : 0;
> @@ -994,7 +996,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
> {
> struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>
> - if (intel_vgpu_active(vm->dev))
> + if (intel_vgpu_active(to_i915(vm->dev)))
> gen8_ppgtt_notify_vgt(ppgtt, false);
>
> if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
> @@ -1545,14 +1547,14 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> 0, 0,
> GEN8_PML4E_SHIFT);
>
> - if (intel_vgpu_active(ppgtt->base.dev)) {
> + if (intel_vgpu_active(to_i915(ppgtt->base.dev))) {
> ret = gen8_preallocate_top_level_pdps(ppgtt);
> if (ret)
> goto free_scratch;
> }
> }
>
> - if (intel_vgpu_active(ppgtt->base.dev))
> + if (intel_vgpu_active(to_i915(ppgtt->base.dev)))
> gen8_ppgtt_notify_vgt(ppgtt, true);
>
> return 0;
> @@ -2080,7 +2082,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> } else
> BUG();
>
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> ppgtt->switch_mm = vgpu_mm_switch;
>
> ret = gen6_ppgtt_alloc(ppgtt);
> @@ -2729,7 +2731,7 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
> i915_address_space_init(&ggtt->base, dev_priv);
> ggtt->base.total += PAGE_SIZE;
>
> - if (intel_vgpu_active(dev)) {
> + if (intel_vgpu_active(dev_priv)) {
> ret = intel_vgt_balloon(dev);
> if (ret)
> return ret;
> @@ -2833,7 +2835,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
> i915_gem_cleanup_stolen(dev);
>
> if (drm_mm_initialized(&ggtt->base.mm)) {
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> intel_vgt_deballoon();
>
> drm_mm_takedown(&ggtt->base.mm);
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index 423cf5144bcb..7c93327b70fe 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -29,7 +29,7 @@
> #include "intel_renderstate.h"
>
> static const struct intel_renderstate_rodata *
> -render_state_get_rodata(struct drm_device *dev, const int gen)
> +render_state_get_rodata(const int gen)
> {
> switch (gen) {
> case 6:
> @@ -45,19 +45,20 @@ render_state_get_rodata(struct drm_device *dev, const int gen)
> return NULL;
> }
>
> -static int render_state_init(struct render_state *so, struct drm_device *dev)
> +static int render_state_init(struct render_state *so,
> + struct drm_i915_private *dev_priv)
> {
> int ret;
>
> - so->gen = INTEL_INFO(dev)->gen;
> - so->rodata = render_state_get_rodata(dev, so->gen);
> + so->gen = INTEL_GEN(dev_priv);
> + so->rodata = render_state_get_rodata(so->gen);
> if (so->rodata == NULL)
> return 0;
>
> if (so->rodata->batch_items * 4 > 4096)
> return -EINVAL;
>
> - so->obj = i915_gem_object_create(dev, 4096);
> + so->obj = i915_gem_object_create(dev_priv->dev, 4096);
> if (IS_ERR(so->obj))
> return PTR_ERR(so->obj);
>
> @@ -177,7 +178,7 @@ int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
> if (WARN_ON(engine->id != RCS))
> return -ENOENT;
>
> - ret = render_state_init(so, engine->dev);
> + ret = render_state_init(so, engine->i915);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
> index 79004f356174..538c30499848 100644
> --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
> +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
> @@ -131,7 +131,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
> unsigned long count = 0;
>
> trace_i915_gem_shrink(dev_priv, target, flags);
> - i915_gem_retire_requests(dev_priv->dev);
> + i915_gem_retire_requests(dev_priv);
>
> /*
> * Unbinding of objects will require HW access; Let us not wake the
> @@ -209,7 +209,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
> if (flags & I915_SHRINK_BOUND)
> intel_runtime_pm_put(dev_priv);
>
> - i915_gem_retire_requests(dev_priv->dev);
> + i915_gem_retire_requests(dev_priv);
>
> return count;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 89725c9efc25..0f6002cb86f4 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -824,19 +824,18 @@ static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
> return error_code;
> }
>
> -static void i915_gem_record_fences(struct drm_device *dev,
> +static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
> struct drm_i915_error_state *error)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> int i;
>
> - if (IS_GEN3(dev) || IS_GEN2(dev)) {
> + if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
> for (i = 0; i < dev_priv->num_fence_regs; i++)
> error->fence[i] = I915_READ(FENCE_REG(i));
> - } else if (IS_GEN5(dev) || IS_GEN4(dev)) {
> + } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
> for (i = 0; i < dev_priv->num_fence_regs; i++)
> error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> - } else if (INTEL_INFO(dev)->gen >= 6) {
> + } else if (INTEL_GEN(dev_priv) >= 6) {
> for (i = 0; i < dev_priv->num_fence_regs; i++)
> error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> }
> @@ -851,7 +850,7 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
> struct intel_engine_cs *to;
> enum intel_engine_id id;
>
> - if (!i915_semaphore_is_enabled(dev_priv->dev))
> + if (!i915_semaphore_is_enabled(dev_priv))
> return;
>
> if (!error->semaphore_obj)
> @@ -893,31 +892,29 @@ static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void i915_record_ring_state(struct drm_device *dev,
> +static void i915_record_ring_state(struct drm_i915_private *dev_priv,
> struct drm_i915_error_state *error,
> struct intel_engine_cs *engine,
> struct drm_i915_error_ring *ering)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (INTEL_INFO(dev)->gen >= 6) {
> + if (INTEL_GEN(dev_priv) >= 6) {
> ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
> ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
> - if (INTEL_INFO(dev)->gen >= 8)
> + if (INTEL_GEN(dev_priv) >= 8)
> gen8_record_semaphore_state(dev_priv, error, engine,
> ering);
> else
> gen6_record_semaphore_state(dev_priv, engine, ering);
> }
>
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
> ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
> ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
> ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
> ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
> ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
> ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
> }
> @@ -939,10 +936,10 @@ static void i915_record_ring_state(struct drm_device *dev,
> ering->tail = I915_READ_TAIL(engine);
> ering->ctl = I915_READ_CTL(engine);
>
> - if (I915_NEED_GFX_HWS(dev)) {
> + if (I915_NEED_GFX_HWS(dev_priv)) {
> i915_reg_t mmio;
>
> - if (IS_GEN7(dev)) {
> + if (IS_GEN7(dev_priv)) {
> switch (engine->id) {
> default:
> case RCS:
> @@ -958,7 +955,7 @@ static void i915_record_ring_state(struct drm_device *dev,
> mmio = VEBOX_HWS_PGA_GEN7;
> break;
> }
> - } else if (IS_GEN6(engine->dev)) {
> + } else if (IS_GEN6(engine->i915)) {
> mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
> } else {
> /* XXX: gen8 returns to sanity */
> @@ -971,18 +968,18 @@ static void i915_record_ring_state(struct drm_device *dev,
> ering->hangcheck_score = engine->hangcheck.score;
> ering->hangcheck_action = engine->hangcheck.action;
>
> - if (USES_PPGTT(dev)) {
> + if (USES_PPGTT(dev_priv)) {
> int i;
>
> ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> ering->vm_info.pp_dir_base =
> I915_READ(RING_PP_DIR_BASE_READ(engine));
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> ering->vm_info.pp_dir_base =
> I915_READ(RING_PP_DIR_BASE(engine));
> - else if (INTEL_INFO(dev)->gen >= 8)
> + else if (INTEL_GEN(dev_priv) >= 8)
> for (i = 0; i < 4; i++) {
> ering->vm_info.pdp[i] =
> I915_READ(GEN8_RING_PDP_UDW(engine, i));
> @@ -998,7 +995,7 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
> struct drm_i915_error_state *error,
> struct drm_i915_error_ring *ering)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct drm_i915_gem_object *obj;
>
> /* Currently render ring is the only HW context user */
> @@ -1016,10 +1013,9 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
> }
> }
>
> -static void i915_gem_record_rings(struct drm_device *dev,
> +static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
> struct drm_i915_error_state *error)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> struct i915_ggtt *ggtt = &dev_priv->ggtt;
> struct drm_i915_gem_request *request;
> int i, count;
> @@ -1030,12 +1026,12 @@ static void i915_gem_record_rings(struct drm_device *dev,
>
> error->ring[i].pid = -1;
>
> - if (engine->dev == NULL)
> + if (!intel_engine_initialized(engine))
> continue;
>
> error->ring[i].valid = true;
>
> - i915_record_ring_state(dev, error, engine, &error->ring[i]);
> + i915_record_ring_state(dev_priv, error, engine, &error->ring[i]);
>
> request = i915_gem_find_active_request(engine);
> if (request) {
> @@ -1301,15 +1297,14 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> error->eir = I915_READ(EIR);
> error->pgtbl_er = I915_READ(PGTBL_ER);
>
> - i915_get_extra_instdone(dev, error->extra_instdone);
> + i915_get_extra_instdone(dev_priv, error->extra_instdone);
> }
>
> -static void i915_error_capture_msg(struct drm_device *dev,
> +static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
> struct drm_i915_error_state *error,
> u32 engine_mask,
> const char *error_msg)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> u32 ecode;
> int ring_id = -1, len;
>
> @@ -1317,7 +1312,7 @@ static void i915_error_capture_msg(struct drm_device *dev,
>
> len = scnprintf(error->error_msg, sizeof(error->error_msg),
> "GPU HANG: ecode %d:%d:0x%08x",
> - INTEL_INFO(dev)->gen, ring_id, ecode);
> + INTEL_GEN(dev_priv), ring_id, ecode);
>
> if (ring_id != -1 && error->ring[ring_id].pid != -1)
> len += scnprintf(error->error_msg + len,
> @@ -1352,11 +1347,11 @@ static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
> * out a structure which becomes available in debugfs for user level tools
> * to pick up.
> */
> -void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
> +void i915_capture_error_state(struct drm_i915_private *dev_priv,
> + u32 engine_mask,
> const char *error_msg)
> {
> static bool warned;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct drm_i915_error_state *error;
> unsigned long flags;
>
> @@ -1372,15 +1367,15 @@ void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
> i915_capture_gen_state(dev_priv, error);
> i915_capture_reg_state(dev_priv, error);
> i915_gem_capture_buffers(dev_priv, error);
> - i915_gem_record_fences(dev, error);
> - i915_gem_record_rings(dev, error);
> + i915_gem_record_fences(dev_priv, error);
> + i915_gem_record_rings(dev_priv, error);
>
> do_gettimeofday(&error->time);
>
> - error->overlay = intel_overlay_capture_error_state(dev);
> - error->display = intel_display_capture_error_state(dev);
> + error->overlay = intel_overlay_capture_error_state(dev_priv);
> + error->display = intel_display_capture_error_state(dev_priv);
>
> - i915_error_capture_msg(dev, error, engine_mask, error_msg);
> + i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
> DRM_INFO("%s\n", error->error_msg);
>
> spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
> @@ -1400,7 +1395,7 @@ void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
> DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
> DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
> DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
> - DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
> + DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev_priv->dev->primary->index);
> warned = true;
> }
> }
> @@ -1450,17 +1445,17 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
> }
>
> /* NB: please notice the memset */
> -void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
> +void i915_get_extra_instdone(struct drm_i915_private *dev_priv,
> + uint32_t *instdone)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
>
> - if (IS_GEN2(dev) || IS_GEN3(dev))
> + if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
> instdone[0] = I915_READ(GEN2_INSTDONE);
> - else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
> + else if (IS_GEN4(dev_priv) || IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) {
> instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
> instdone[1] = I915_READ(GEN4_INSTDONE1);
> - } else if (INTEL_INFO(dev)->gen >= 7) {
> + } else if (INTEL_GEN(dev_priv) >= 7) {
> instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
> instdone[1] = I915_READ(GEN7_SC_INSTDONE);
> instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2f6fd33c07ba..8864ee19154f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2555,15 +2555,15 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
> * Fire an error uevent so userspace can see that a hang or error
> * was detected.
> */
> -static void i915_reset_and_wakeup(struct drm_device *dev)
> +static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
> char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
> char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
> char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
> int ret;
>
> - kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
> + kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
>
> /*
> * Note that there's only one work item which does gpu resets, so we
> @@ -2577,8 +2577,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> */
> if (i915_reset_in_progress(&dev_priv->gpu_error)) {
> DRM_DEBUG_DRIVER("resetting chip\n");
> - kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
> - reset_event);
> + kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
>
> /*
> * In most cases it's guaranteed that we get here with an RPM
> @@ -2589,7 +2588,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> */
> intel_runtime_pm_get(dev_priv);
>
> - intel_prepare_reset(dev);
> + intel_prepare_reset(dev_priv);
>
> /*
> * All state reset _must_ be completed before we update the
> @@ -2597,14 +2596,14 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> * pending state and not properly drop locks, resulting in
> * deadlocks with the reset work.
> */
> - ret = i915_reset(dev);
> + ret = i915_reset(dev_priv);
>
> - intel_finish_reset(dev);
> + intel_finish_reset(dev_priv);
>
> intel_runtime_pm_put(dev_priv);
>
> if (ret == 0)
> - kobject_uevent_env(&dev->primary->kdev->kobj,
> + kobject_uevent_env(kobj,
> KOBJ_CHANGE, reset_done_event);
>
> /*
> @@ -2615,9 +2614,8 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> }
> }
>
> -static void i915_report_and_clear_eir(struct drm_device *dev)
> +static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> uint32_t instdone[I915_NUM_INSTDONE_REG];
> u32 eir = I915_READ(EIR);
> int pipe, i;
> @@ -2627,9 +2625,9 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
>
> pr_err("render error detected, EIR: 0x%08x\n", eir);
>
> - i915_get_extra_instdone(dev, instdone);
> + i915_get_extra_instdone(dev_priv, instdone);
>
> - if (IS_G4X(dev)) {
> + if (IS_G4X(dev_priv)) {
> if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
> u32 ipeir = I915_READ(IPEIR_I965);
>
> @@ -2651,7 +2649,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
> }
> }
>
> - if (!IS_GEN2(dev)) {
> + if (!IS_GEN2(dev_priv)) {
> if (eir & I915_ERROR_PAGE_TABLE) {
> u32 pgtbl_err = I915_READ(PGTBL_ER);
> pr_err("page table error\n");
> @@ -2673,7 +2671,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
> pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
> for (i = 0; i < ARRAY_SIZE(instdone); i++)
> pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
> - if (INTEL_INFO(dev)->gen < 4) {
> + if (INTEL_GEN(dev_priv) < 4) {
> u32 ipeir = I915_READ(IPEIR);
>
> pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
> @@ -2717,10 +2715,10 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
> * so userspace knows something bad happened (should trigger collection
> * of a ring dump etc.).
> */
> -void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> +void i915_handle_error(struct drm_i915_private *dev_priv,
> + u32 engine_mask,
> const char *fmt, ...)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> va_list args;
> char error_msg[80];
>
> @@ -2728,8 +2726,8 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> vscnprintf(error_msg, sizeof(error_msg), fmt, args);
> va_end(args);
>
> - i915_capture_error_state(dev, engine_mask, error_msg);
> - i915_report_and_clear_eir(dev);
> + i915_capture_error_state(dev_priv, engine_mask, error_msg);
> + i915_report_and_clear_eir(dev_priv);
>
> if (engine_mask) {
> atomic_or(I915_RESET_IN_PROGRESS_FLAG,
> @@ -2751,7 +2749,7 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> i915_error_wake_up(dev_priv, false);
> }
>
> - i915_reset_and_wakeup(dev);
> + i915_reset_and_wakeup(dev_priv);
> }
>
> /* Called from drm generic code, passed 'crtc' which
> @@ -2869,9 +2867,9 @@ ring_idle(struct intel_engine_cs *engine, u32 seqno)
> }
>
> static bool
> -ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
> +ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr)
> {
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> return (ipehr >> 23) == 0x1c;
> } else {
> ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
> @@ -2884,10 +2882,10 @@ static struct intel_engine_cs *
> semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
> u64 offset)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct intel_engine_cs *signaller;
>
> - if (INTEL_INFO(dev_priv)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> for_each_engine(signaller, dev_priv) {
> if (engine == signaller)
> continue;
> @@ -2916,7 +2914,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
> static struct intel_engine_cs *
> semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u32 cmd, ipehr, head;
> u64 offset = 0;
> int i, backwards;
> @@ -2942,7 +2940,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
> return NULL;
>
> ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
> - if (!ipehr_is_semaphore_wait(engine->dev, ipehr))
> + if (!ipehr_is_semaphore_wait(engine->i915, ipehr))
> return NULL;
>
> /*
> @@ -2954,7 +2952,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
> * ringbuffer itself.
> */
> head = I915_READ_HEAD(engine) & HEAD_ADDR;
> - backwards = (INTEL_INFO(engine->dev)->gen >= 8) ? 5 : 4;
> + backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
>
> for (i = backwards; i; --i) {
> /*
> @@ -2976,7 +2974,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
> return NULL;
>
> *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
> - if (INTEL_INFO(engine->dev)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> offset = ioread32(engine->buffer->virtual_start + head + 12);
> offset <<= 32;
> offset = ioread32(engine->buffer->virtual_start + head + 8);
> @@ -2986,7 +2984,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
>
> static int semaphore_passed(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct intel_engine_cs *signaller;
> u32 seqno;
>
> @@ -3028,7 +3026,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
> if (engine->id != RCS)
> return true;
>
> - i915_get_extra_instdone(engine->dev, instdone);
> + i915_get_extra_instdone(engine->i915, instdone);
>
> /* There might be unstable subunit states even when
> * actual head is not moving. Filter out the unstable ones by
> @@ -3069,8 +3067,7 @@ head_stuck(struct intel_engine_cs *engine, u64 acthd)
> static enum intel_ring_hangcheck_action
> ring_stuck(struct intel_engine_cs *engine, u64 acthd)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> enum intel_ring_hangcheck_action ha;
> u32 tmp;
>
> @@ -3078,7 +3075,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
> if (ha != HANGCHECK_HUNG)
> return ha;
>
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> return HANGCHECK_HUNG;
>
> /* Is the chip hanging on a WAIT_FOR_EVENT?
> @@ -3088,19 +3085,19 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
> */
> tmp = I915_READ_CTL(engine);
> if (tmp & RING_WAIT) {
> - i915_handle_error(dev, 0,
> + i915_handle_error(dev_priv, 0,
> "Kicking stuck wait on %s",
> engine->name);
> I915_WRITE_CTL(engine, tmp);
> return HANGCHECK_KICK;
> }
>
> - if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
> + if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
> switch (semaphore_passed(engine)) {
> default:
> return HANGCHECK_HUNG;
> case 1:
> - i915_handle_error(dev, 0,
> + i915_handle_error(dev_priv, 0,
> "Kicking stuck semaphore on %s",
> engine->name);
> I915_WRITE_CTL(engine, tmp);
> @@ -3115,7 +3112,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
>
> static unsigned kick_waiters(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *i915 = to_i915(engine->dev);
> + struct drm_i915_private *i915 = engine->i915;
> unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
>
> if (engine->hangcheck.user_interrupts == user_interrupts &&
> @@ -3144,7 +3141,6 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> struct drm_i915_private *dev_priv =
> container_of(work, typeof(*dev_priv),
> gpu_error.hangcheck_work.work);
> - struct drm_device *dev = dev_priv->dev;
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> int busy_count = 0, rings_hung = 0;
> @@ -3272,22 +3268,22 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> }
>
> if (rings_hung) {
> - i915_handle_error(dev, rings_hung, "Engine(s) hung");
> + i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
> goto out;
> }
>
> if (busy_count)
> /* Reset timer case chip hangs without another request
> * being added */
> - i915_queue_hangcheck(dev);
> + i915_queue_hangcheck(dev_priv);
>
> out:
> ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
> }
>
> -void i915_queue_hangcheck(struct drm_device *dev)
> +void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
> {
> - struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
> + struct i915_gpu_error *e = &dev_priv->gpu_error;
>
> if (!i915.enable_hangcheck)
> return;
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index dc0def210097..20b2e4039792 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -462,7 +462,7 @@ TRACE_EVENT(i915_gem_ring_sync_to,
> ),
>
> TP_fast_assign(
> - __entry->dev = from->dev->primary->index;
> + __entry->dev = from->i915->dev->primary->index;
> __entry->sync_from = from->id;
> __entry->sync_to = to_req->engine->id;
> __entry->seqno = i915_gem_request_get_seqno(req);
> @@ -486,13 +486,11 @@ TRACE_EVENT(i915_gem_ring_dispatch,
> ),
>
> TP_fast_assign(
> - struct intel_engine_cs *engine =
> - i915_gem_request_get_engine(req);
> - __entry->dev = engine->dev->primary->index;
> - __entry->ring = engine->id;
> - __entry->seqno = i915_gem_request_get_seqno(req);
> + __entry->dev = req->i915->dev->primary->index;
> + __entry->ring = req->engine->id;
> + __entry->seqno = req->seqno;
> __entry->flags = flags;
> - i915_trace_irq_get(engine, req);
> + i915_trace_irq_get(req->engine, req);
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u, flags=%x",
> @@ -511,7 +509,7 @@ TRACE_EVENT(i915_gem_ring_flush,
> ),
>
> TP_fast_assign(
> - __entry->dev = req->engine->dev->primary->index;
> + __entry->dev = req->i915->dev->primary->index;
> __entry->ring = req->engine->id;
> __entry->invalidate = invalidate;
> __entry->flush = flush;
> @@ -533,11 +531,9 @@ DECLARE_EVENT_CLASS(i915_gem_request,
> ),
>
> TP_fast_assign(
> - struct intel_engine_cs *engine =
> - i915_gem_request_get_engine(req);
> - __entry->dev = engine->dev->primary->index;
> - __entry->ring = engine->id;
> - __entry->seqno = i915_gem_request_get_seqno(req);
> + __entry->dev = req->i915->dev->primary->index;
> + __entry->ring = req->engine->id;
> + __entry->seqno = req->seqno;
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u",
> @@ -560,7 +556,7 @@ TRACE_EVENT(i915_gem_request_notify,
> ),
>
> TP_fast_assign(
> - __entry->dev = engine->dev->primary->index;
> + __entry->dev = engine->i915->dev->primary->index;
> __entry->ring = engine->id;
> __entry->seqno = engine->get_seqno(engine);
> ),
> @@ -597,13 +593,11 @@ TRACE_EVENT(i915_gem_request_wait_begin,
> * less desirable.
> */
> TP_fast_assign(
> - struct intel_engine_cs *engine =
> - i915_gem_request_get_engine(req);
> - __entry->dev = engine->dev->primary->index;
> - __entry->ring = engine->id;
> - __entry->seqno = i915_gem_request_get_seqno(req);
> + __entry->dev = req->i915->dev->primary->index;
> + __entry->ring = req->engine->id;
> + __entry->seqno = req->seqno;
> __entry->blocking =
> - mutex_is_locked(&engine->dev->struct_mutex);
> + mutex_is_locked(&req->i915->dev->struct_mutex);
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u, blocking=%s",
> @@ -792,7 +786,7 @@ TRACE_EVENT(switch_mm,
> __entry->ring = engine->id;
> __entry->to = to;
> __entry->vm = to->ppgtt? &to->ppgtt->base : NULL;
> - __entry->dev = engine->dev->primary->index;
> + __entry->dev = engine->i915->dev->primary->index;
> ),
>
> TP_printk("dev=%u, ring=%u, ctx=%p, ctx_vm=%p",
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 45c218db86be..6e2e2b98d323 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3144,41 +3144,39 @@ static void intel_update_primary_planes(struct drm_device *dev)
> }
> }
>
> -void intel_prepare_reset(struct drm_device *dev)
> +void intel_prepare_reset(struct drm_i915_private *dev_priv)
> {
> /* no reset support for gen2 */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> return;
>
> /* reset doesn't touch the display */
> - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
> + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> return;
>
> - drm_modeset_lock_all(dev);
> + drm_modeset_lock_all(dev_priv->dev);
> /*
> * Disabling the crtcs gracefully seems nicer. Also the
> * g33 docs say we should at least disable all the planes.
> */
> - intel_display_suspend(dev);
> + intel_display_suspend(dev_priv->dev);
> }
>
> -void intel_finish_reset(struct drm_device *dev)
> +void intel_finish_reset(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> -
> /*
> * Flips in the rings will be nuked by the reset,
> * so complete all pending flips so that user space
> * will get its events and not get stuck.
> */
> - intel_complete_page_flips(dev);
> + intel_complete_page_flips(dev_priv->dev);
>
> /* no reset support for gen2 */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> return;
>
> /* reset doesn't touch the display */
> - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
> + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> /*
> * Flips in the rings have been nuked by the reset,
> * so update the base address of all primary
> @@ -3188,7 +3186,7 @@ void intel_finish_reset(struct drm_device *dev)
> * FIXME: Atomic will make this obsolete since we won't schedule
> * CS-based flips (which might get lost in gpu resets) any more.
> */
> - intel_update_primary_planes(dev);
> + intel_update_primary_planes(dev_priv->dev);
> return;
> }
>
> @@ -3199,18 +3197,18 @@ void intel_finish_reset(struct drm_device *dev)
> intel_runtime_pm_disable_interrupts(dev_priv);
> intel_runtime_pm_enable_interrupts(dev_priv);
>
> - intel_modeset_init_hw(dev);
> + intel_modeset_init_hw(dev_priv->dev);
>
> spin_lock_irq(&dev_priv->irq_lock);
> if (dev_priv->display.hpd_irq_setup)
> - dev_priv->display.hpd_irq_setup(dev);
> + dev_priv->display.hpd_irq_setup(dev_priv->dev);
> spin_unlock_irq(&dev_priv->irq_lock);
>
> - intel_display_resume(dev);
> + intel_display_resume(dev_priv->dev);
>
> intel_hpd_init(dev_priv);
>
> - drm_modeset_unlock_all(dev);
> + drm_modeset_unlock_all(dev_priv->dev);
> }
>
> static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
> @@ -11256,7 +11254,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
> if (engine == NULL)
> return true;
>
> - if (INTEL_INFO(engine->dev)->gen < 5)
> + if (INTEL_GEN(engine->i915) < 5)
> return false;
>
> if (i915.use_mmio_flip < 0)
> @@ -16185,9 +16183,8 @@ struct intel_display_error_state {
> };
>
> struct intel_display_error_state *
> -intel_display_capture_error_state(struct drm_device *dev)
> +intel_display_capture_error_state(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_display_error_state *error;
> int transcoders[] = {
> TRANSCODER_A,
> @@ -16197,14 +16194,14 @@ intel_display_capture_error_state(struct drm_device *dev)
> };
> int i;
>
> - if (INTEL_INFO(dev)->num_pipes == 0)
> + if (INTEL_INFO(dev_priv)->num_pipes == 0)
> return NULL;
>
> error = kzalloc(sizeof(*error), GFP_ATOMIC);
> if (error == NULL)
> return NULL;
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
>
> for_each_pipe(dev_priv, i) {
> @@ -16220,25 +16217,25 @@ intel_display_capture_error_state(struct drm_device *dev)
>
> error->plane[i].control = I915_READ(DSPCNTR(i));
> error->plane[i].stride = I915_READ(DSPSTRIDE(i));
> - if (INTEL_INFO(dev)->gen <= 3) {
> + if (INTEL_GEN(dev_priv) <= 3) {
> error->plane[i].size = I915_READ(DSPSIZE(i));
> error->plane[i].pos = I915_READ(DSPPOS(i));
> }
> - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
> + if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
> error->plane[i].addr = I915_READ(DSPADDR(i));
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> error->plane[i].surface = I915_READ(DSPSURF(i));
> error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
> }
>
> error->pipe[i].source = I915_READ(PIPESRC(i));
>
> - if (HAS_GMCH_DISPLAY(dev))
> + if (HAS_GMCH_DISPLAY(dev_priv))
> error->pipe[i].stat = I915_READ(PIPESTAT(i));
> }
>
> /* Note: this does not include DSI transcoders. */
> - error->num_transcoders = INTEL_INFO(dev)->num_pipes;
> + error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
> if (HAS_DDI(dev_priv))
> error->num_transcoders++; /* Account for eDP. */
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 51058522741a..66de61669884 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1226,8 +1226,8 @@ u32 intel_compute_tile_offset(int *x, int *y,
> const struct drm_framebuffer *fb, int plane,
> unsigned int pitch,
> unsigned int rotation);
> -void intel_prepare_reset(struct drm_device *dev);
> -void intel_finish_reset(struct drm_device *dev);
> +void intel_prepare_reset(struct drm_i915_private *dev_priv);
> +void intel_finish_reset(struct drm_i915_private *dev_priv);
> void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> void broxton_init_cdclk(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index d5a7cfec589b..4a527d3cf026 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -827,7 +827,7 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc)
> bool enable_by_default = IS_HASWELL(dev_priv) ||
> IS_BROADWELL(dev_priv);
>
> - if (intel_vgpu_active(dev_priv->dev)) {
> + if (intel_vgpu_active(dev_priv)) {
> fbc->no_fbc_reason = "VGPU is active";
> return false;
> }
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 8106316ce56f..62bea20283df 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -246,21 +246,22 @@ static int intel_lr_context_pin(struct intel_context *ctx,
> *
> * Return: 1 if Execlists is supported and has to be enabled.
> */
> -int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
> +int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
> {
> /* On platforms with execlist available, vGPU will only
> * support execlist mode, no ring buffer mode.
> */
> - if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
> + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
> return 1;
>
> - if (INTEL_INFO(dev)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return 1;
>
> if (enable_execlists == 0)
> return 0;
>
> - if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
> + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
> + USES_PPGTT(dev_priv) &&
> i915.use_mmio_flip >= 0)
> return 1;
>
> @@ -270,19 +271,19 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists
> static void
> logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> - if (IS_GEN8(dev) || IS_GEN9(dev))
> + if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
> engine->idle_lite_restore_wa = ~0;
>
> - engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
> + engine->disable_lite_restore_wa = (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
> (engine->id == VCS || engine->id == VCS2);
>
> engine->ctx_desc_template = GEN8_CTX_VALID;
> - engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
> + engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
> GEN8_CTX_ADDRESSING_MODE_SHIFT;
> - if (IS_GEN8(dev))
> + if (IS_GEN8(dev_priv))
> engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
> engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
>
> @@ -342,8 +343,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
> {
>
> struct intel_engine_cs *engine = rq0->engine;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = rq0->i915;
> uint64_t desc[2];
>
> if (rq1) {
> @@ -425,7 +425,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
> * If irqs are not active generate a warning as batches that finish
> * without the irqs may get lost and a GPU Hang may occur.
> */
> - WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
> + WARN_ON(!intel_irqs_enabled(engine->i915));
>
> /* Try to read in pairs */
> list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
> @@ -497,7 +497,7 @@ static u32
> get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
> u32 *context_id)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u32 status;
>
> read_pointer %= GEN8_CSB_ENTRIES;
> @@ -523,7 +523,7 @@ get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
> static void intel_lrc_irq_handler(unsigned long data)
> {
> struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u32 status_pointer;
> unsigned int read_pointer, write_pointer;
> u32 csb[GEN8_CSB_ENTRIES][2];
> @@ -884,7 +884,7 @@ void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
> struct drm_i915_gem_request *req, *tmp;
> LIST_HEAD(cancel_list);
>
> - WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
> + WARN_ON(!mutex_is_locked(&engine->i915->dev->struct_mutex));
>
> spin_lock_bh(&engine->execlist_lock);
> list_replace_init(&engine->execlist_queue, &cancel_list);
> @@ -898,7 +898,7 @@ void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
>
> void intel_logical_ring_stop(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
>
> if (!intel_engine_initialized(engine))
> @@ -964,7 +964,7 @@ static int intel_lr_context_pin(struct intel_context *ctx,
> lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
>
> ringbuf = ctx->engine[engine->id].ringbuf;
> - ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
> + ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
> if (ret)
> goto unpin_map;
>
> @@ -1019,9 +1019,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> int ret, i;
> struct intel_engine_cs *engine = req->engine;
> struct intel_ringbuffer *ringbuf = req->ringbuf;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct i915_workarounds *w = &dev_priv->workarounds;
> + struct i915_workarounds *w = &req->i915->workarounds;
>
> if (w->count == 0)
> return 0;
> @@ -1092,7 +1090,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
> * this batch updates GEN8_L3SQCREG4 with default value we need to
> * set this bit here to retain the WA during flush.
> */
> - if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
> + if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0))
> l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
>
> wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
> @@ -1181,7 +1179,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
> wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
>
> /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
> - if (IS_BROADWELL(engine->dev)) {
> + if (IS_BROADWELL(engine->i915)) {
> int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
> if (rc < 0)
> return rc;
> @@ -1253,12 +1251,11 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
> uint32_t *offset)
> {
> int ret;
> - struct drm_device *dev = engine->dev;
> uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>
> /* WaDisableCtxRestoreArbitration:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
> + IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
> wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
>
> /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
> @@ -1279,12 +1276,11 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
> uint32_t *const batch,
> uint32_t *offset)
> {
> - struct drm_device *dev = engine->dev;
> uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>
> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
> + IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
> wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
> wa_ctx_emit(batch, index,
> @@ -1293,7 +1289,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
> }
>
> /* WaClearTdlStateAckDirtyBits:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
> + if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
> wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
>
> wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
> @@ -1312,8 +1308,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
> }
>
> /* WaDisableCtxRestoreArbitration:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
> + IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
> wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
>
> wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
> @@ -1325,7 +1321,7 @@ static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
> {
> int ret;
>
> - engine->wa_ctx.obj = i915_gem_object_create(engine->dev,
> + engine->wa_ctx.obj = i915_gem_object_create(engine->i915->dev,
> PAGE_ALIGN(size));
> if (IS_ERR(engine->wa_ctx.obj)) {
> DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
> @@ -1365,9 +1361,9 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> WARN_ON(engine->id != RCS);
>
> /* update this when WA for higher Gen are added */
> - if (INTEL_INFO(engine->dev)->gen > 9) {
> + if (INTEL_GEN(engine->i915) > 9) {
> DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
> - INTEL_INFO(engine->dev)->gen);
> + INTEL_GEN(engine->i915));
> return 0;
> }
>
> @@ -1387,7 +1383,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> batch = kmap_atomic(page);
> offset = 0;
>
> - if (INTEL_INFO(engine->dev)->gen == 8) {
> + if (IS_GEN8(engine->i915)) {
> ret = gen8_init_indirectctx_bb(engine,
> &wa_ctx->indirect_ctx,
> batch,
> @@ -1401,7 +1397,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> &offset);
> if (ret)
> goto out;
> - } else if (INTEL_INFO(engine->dev)->gen == 9) {
> + } else if (IS_GEN9(engine->i915)) {
> ret = gen9_init_indirectctx_bb(engine,
> &wa_ctx->indirect_ctx,
> batch,
> @@ -1427,7 +1423,7 @@ out:
>
> static void lrc_init_hws(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> I915_WRITE(RING_HWS_PGA(engine->mmio_base),
> (u32)engine->status_page.gfx_addr);
> @@ -1436,8 +1432,7 @@ static void lrc_init_hws(struct intel_engine_cs *engine)
>
> static int gen8_init_common_ring(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned int next_context_status_buffer_hw;
>
> lrc_init_hws(engine);
> @@ -1484,8 +1479,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
>
> static int gen8_init_render_ring(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
>
> ret = gen8_init_common_ring(engine);
> @@ -1562,7 +1556,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
> if (req->ctx->ppgtt &&
> (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
> if (!USES_FULL_48BIT_PPGTT(req->i915) &&
> - !intel_vgpu_active(req->i915->dev)) {
> + !intel_vgpu_active(req->i915)) {
> ret = intel_logical_ring_emit_pdps(req);
> if (ret)
> return ret;
> @@ -1590,8 +1584,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
>
> static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1610,8 +1603,7 @@ static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
>
> static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1628,8 +1620,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
> {
> struct intel_ringbuffer *ringbuf = request->ringbuf;
> struct intel_engine_cs *engine = ringbuf->engine;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = request->i915;
> uint32_t cmd;
> int ret;
>
> @@ -1697,7 +1688,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
> * pipe control.
> */
> - if (IS_GEN9(engine->dev))
> + if (IS_GEN9(request->i915))
> vf_flush_wa = true;
> }
>
> @@ -1890,7 +1881,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
> if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
> tasklet_kill(&engine->irq_tasklet);
>
> - dev_priv = engine->dev->dev_private;
> + dev_priv = engine->i915;
>
> if (engine->buffer) {
> intel_logical_ring_stop(engine);
> @@ -1914,7 +1905,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
> engine->ctx_desc_template = 0;
>
> lrc_destroy_wa_ctx_obj(engine);
> - engine->dev = NULL;
> + engine->i915 = NULL;
> }
>
> static void
> @@ -1929,7 +1920,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> engine->emit_bb_start = gen8_emit_bb_start;
> engine->get_seqno = gen8_get_seqno;
> engine->set_seqno = gen8_set_seqno;
> - if (IS_BXT_REVID(engine->dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
> engine->irq_seqno_barrier = bxt_a_seqno_barrier;
> engine->set_seqno = bxt_a_set_seqno;
> }
> @@ -2023,7 +2014,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
> I915_WRITE_IMR(engine, ~0);
> POSTING_READ(RING_IMR(engine->mmio_base));
>
> - engine->dev = dev;
> + engine->i915 = dev_priv;
>
> /* Intentionally left blank. */
> engine->buffer = NULL;
> @@ -2056,7 +2047,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
> logical_ring_default_irqs(engine, info->irq_shift);
>
> intel_engine_init_hangcheck(engine);
> - i915_gem_batch_pool_init(engine->dev, &engine->batch_pool);
> + i915_gem_batch_pool_init(dev, &engine->batch_pool);
>
> return engine;
> }
> @@ -2064,7 +2055,7 @@ logical_ring_setup(struct drm_device *dev, enum intel_engine_id id)
> static int
> logical_ring_init(struct intel_engine_cs *engine)
> {
> - struct intel_context *dctx = to_i915(engine->dev)->kernel_context;
> + struct intel_context *dctx = engine->i915->kernel_context;
> int ret;
>
> ret = i915_cmd_parser_init_ring(engine);
> @@ -2224,7 +2215,7 @@ cleanup_render_ring:
> }
>
> static u32
> -make_rpcs(struct drm_device *dev)
> +make_rpcs(struct drm_i915_private *dev_priv)
> {
> u32 rpcs = 0;
>
> @@ -2232,7 +2223,7 @@ make_rpcs(struct drm_device *dev)
> * No explicit RPCS request is needed to ensure full
> * slice/subslice/EU enablement prior to Gen9.
> */
> - if (INTEL_INFO(dev)->gen < 9)
> + if (INTEL_GEN(dev_priv) < 9)
> return 0;
>
> /*
> @@ -2241,24 +2232,24 @@ make_rpcs(struct drm_device *dev)
> * must make an explicit request through RPCS for full
> * enablement.
> */
> - if (INTEL_INFO(dev)->has_slice_pg) {
> + if (INTEL_INFO(dev_priv)->has_slice_pg) {
> rpcs |= GEN8_RPCS_S_CNT_ENABLE;
> - rpcs |= INTEL_INFO(dev)->slice_total <<
> + rpcs |= INTEL_INFO(dev_priv)->slice_total <<
> GEN8_RPCS_S_CNT_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
>
> - if (INTEL_INFO(dev)->has_subslice_pg) {
> + if (INTEL_INFO(dev_priv)->has_subslice_pg) {
> rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
> - rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
> + rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice <<
> GEN8_RPCS_SS_CNT_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
>
> - if (INTEL_INFO(dev)->has_eu_pg) {
> - rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
> + if (INTEL_INFO(dev_priv)->has_eu_pg) {
> + rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
> GEN8_RPCS_EU_MIN_SHIFT;
> - rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
> + rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
> GEN8_RPCS_EU_MAX_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
> @@ -2270,9 +2261,9 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
> {
> u32 indirect_ctx_offset;
>
> - switch (INTEL_INFO(engine->dev)->gen) {
> + switch (INTEL_GEN(engine->i915)) {
> default:
> - MISSING_CASE(INTEL_INFO(engine->dev)->gen);
> + MISSING_CASE(INTEL_GEN(engine->i915));
> /* fall through */
> case 9:
> indirect_ctx_offset =
> @@ -2293,8 +2284,7 @@ populate_lr_context(struct intel_context *ctx,
> struct intel_engine_cs *engine,
> struct intel_ringbuffer *ringbuf)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = ctx->i915;
> struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
> void *vaddr;
> u32 *reg_state;
> @@ -2332,7 +2322,7 @@ populate_lr_context(struct intel_context *ctx,
> RING_CONTEXT_CONTROL(engine),
> _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
> CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
> - (HAS_RESOURCE_STREAMER(dev) ?
> + (HAS_RESOURCE_STREAMER(dev_priv) ?
> CTX_CTRL_RS_CTX_ENABLE : 0)));
> ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
> 0);
> @@ -2421,7 +2411,7 @@ populate_lr_context(struct intel_context *ctx,
> if (engine->id == RCS) {
> reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
> ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
> - make_rpcs(dev));
> + make_rpcs(dev_priv));
> }
>
> i915_gem_object_unpin_map(ctx_obj);
> @@ -2472,11 +2462,11 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> {
> int ret = 0;
>
> - WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
> + WARN_ON(INTEL_GEN(engine->i915) < 8);
>
> switch (engine->id) {
> case RCS:
> - if (INTEL_INFO(engine->dev)->gen >= 9)
> + if (INTEL_GEN(engine->i915) >= 9)
> ret = GEN9_LR_CONTEXT_RENDER_SIZE;
> else
> ret = GEN8_LR_CONTEXT_RENDER_SIZE;
> @@ -2508,7 +2498,6 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> static int execlists_context_deferred_alloc(struct intel_context *ctx,
> struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> struct drm_i915_gem_object *ctx_obj;
> uint32_t context_size;
> struct intel_ringbuffer *ringbuf;
> @@ -2522,7 +2511,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
> /* One extra page as the sharing data between driver and GuC */
> context_size += PAGE_SIZE * LRC_PPHWSP_PN;
>
> - ctx_obj = i915_gem_object_create(dev, context_size);
> + ctx_obj = i915_gem_object_create(ctx->i915->dev, context_size);
> if (IS_ERR(ctx_obj)) {
> DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
> return PTR_ERR(ctx_obj);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 229b8a974262..1afba0331dc6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -112,7 +112,8 @@ uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
> struct intel_engine_cs *engine);
>
> /* Execlists */
> -int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
> +int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
> + int enable_execlists);
> struct i915_execbuffer_params;
> int intel_execlists_submission(struct i915_execbuffer_params *params,
> struct drm_i915_gem_execbuffer2 *args,
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 6ba4bf7f2a89..b765c75f3fcd 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -189,7 +189,7 @@ static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
> */
> int intel_mocs_init_engine(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
> struct drm_i915_mocs_table table;
> unsigned int index;
>
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index 8570c60c6fc0..4a1e774ba8cc 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -1508,9 +1508,8 @@ static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
>
>
> struct intel_overlay_error_state *
> -intel_overlay_capture_error_state(struct drm_device *dev)
> +intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_overlay *overlay = dev_priv->overlay;
> struct intel_overlay_error_state *error;
> struct overlay_registers __iomem *regs;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 017c431f9363..ba097f2dd561 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6349,7 +6349,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> /* Powersaving is controlled by the host when inside a VM */
> - if (intel_vgpu_active(dev))
> + if (intel_vgpu_active(dev_priv))
> return;
>
> if (IS_IRONLAKE_M(dev)) {
> @@ -7405,8 +7405,7 @@ static void __intel_rps_boost_work(struct work_struct *work)
> struct drm_i915_gem_request *req = boost->req;
>
> if (!i915_gem_request_completed(req, true))
> - gen6_rps_boost(to_i915(req->engine->dev), NULL,
> - req->emitted_jiffies);
> + gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
>
> i915_gem_request_unreference(req);
> kfree(boost);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8f3eb3033da0..e17a682dd621 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -60,7 +60,7 @@ void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
>
> bool intel_engine_stopped(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
> }
>
> @@ -106,7 +106,6 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> u32 flush_domains)
> {
> struct intel_engine_cs *engine = req->engine;
> - struct drm_device *dev = engine->dev;
> u32 cmd;
> int ret;
>
> @@ -145,7 +144,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> cmd |= MI_EXE_FLUSH;
>
> if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
> - (IS_G4X(dev) || IS_GEN5(dev)))
> + (IS_G4X(req->i915) || IS_GEN5(req->i915)))
> cmd |= MI_INVALIDATE_ISP;
>
> ret = intel_ring_begin(req, 2);
> @@ -431,19 +430,19 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> static void ring_write_tail(struct intel_engine_cs *engine,
> u32 value)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> I915_WRITE_TAIL(engine, value);
> }
>
> u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u64 acthd;
>
> - if (INTEL_INFO(engine->dev)->gen >= 8)
> + if (INTEL_GEN(dev_priv) >= 8)
> acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
> RING_ACTHD_UDW(engine->mmio_base));
> - else if (INTEL_INFO(engine->dev)->gen >= 4)
> + else if (INTEL_GEN(dev_priv) >= 4)
> acthd = I915_READ(RING_ACTHD(engine->mmio_base));
> else
> acthd = I915_READ(ACTHD);
> @@ -453,25 +452,24 @@ u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
>
> static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u32 addr;
>
> addr = dev_priv->status_page_dmah->busaddr;
> - if (INTEL_INFO(engine->dev)->gen >= 4)
> + if (INTEL_GEN(dev_priv) >= 4)
> addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
> I915_WRITE(HWS_PGA, addr);
> }
>
> static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> i915_reg_t mmio;
>
> /* The ring status page addresses are no longer next to the rest of
> * the ring registers as of gen7.
> */
> - if (IS_GEN7(dev)) {
> + if (IS_GEN7(dev_priv)) {
> switch (engine->id) {
> case RCS:
> mmio = RENDER_HWS_PGA_GEN7;
> @@ -491,7 +489,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> mmio = VEBOX_HWS_PGA_GEN7;
> break;
> }
> - } else if (IS_GEN6(engine->dev)) {
> + } else if (IS_GEN6(dev_priv)) {
> mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
> } else {
> /* XXX: gen8 returns to sanity */
> @@ -508,7 +506,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> * arises: do we still need this and if so how should we go about
> * invalidating the TLB?
> */
> - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
> + if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8) {
> i915_reg_t reg = RING_INSTPM(engine->mmio_base);
>
> /* ring should be idle before issuing a sync flush*/
> @@ -526,9 +524,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>
> static bool stop_ring(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
>
> - if (!IS_GEN2(engine->dev)) {
> + if (!IS_GEN2(dev_priv)) {
> I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
> if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
> DRM_ERROR("%s : timed out trying to stop ring\n",
> @@ -546,7 +544,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
> I915_WRITE_HEAD(engine, 0);
> engine->write_tail(engine, 0);
>
> - if (!IS_GEN2(engine->dev)) {
> + if (!IS_GEN2(dev_priv)) {
> (void)I915_READ_CTL(engine);
> I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
> }
> @@ -561,8 +559,7 @@ void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
>
> static int init_ring_common(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct intel_ringbuffer *ringbuf = engine->buffer;
> struct drm_i915_gem_object *obj = ringbuf->obj;
> int ret = 0;
> @@ -592,7 +589,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
> }
> }
>
> - if (I915_NEED_GFX_HWS(dev))
> + if (I915_NEED_GFX_HWS(dev_priv))
> intel_ring_setup_status_page(engine);
> else
> ring_setup_phys_status_page(engine);
> @@ -649,12 +646,10 @@ out:
> void
> intel_fini_pipe_control(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> -
> if (engine->scratch.obj == NULL)
> return;
>
> - if (INTEL_INFO(dev)->gen >= 5) {
> + if (INTEL_GEN(engine->i915) >= 5) {
> kunmap(sg_page(engine->scratch.obj->pages->sgl));
> i915_gem_object_ggtt_unpin(engine->scratch.obj);
> }
> @@ -670,7 +665,7 @@ intel_init_pipe_control(struct intel_engine_cs *engine)
>
> WARN_ON(engine->scratch.obj);
>
> - engine->scratch.obj = i915_gem_object_create(engine->dev, 4096);
> + engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
> if (IS_ERR(engine->scratch.obj)) {
> DRM_ERROR("Failed to allocate seqno page\n");
> ret = PTR_ERR(engine->scratch.obj);
> @@ -708,11 +703,9 @@ err:
>
> static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
> {
> - int ret, i;
> struct intel_engine_cs *engine = req->engine;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct i915_workarounds *w = &dev_priv->workarounds;
> + struct i915_workarounds *w = &req->i915->workarounds;
> + int ret, i;
>
> if (w->count == 0)
> return 0;
> @@ -801,7 +794,7 @@ static int wa_add(struct drm_i915_private *dev_priv,
> static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
> i915_reg_t reg)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> struct i915_workarounds *wa = &dev_priv->workarounds;
> const uint32_t index = wa->hw_whitelist_count[engine->id];
>
> @@ -817,8 +810,7 @@ static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
>
> static int gen8_init_workarounds(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>
> @@ -869,9 +861,8 @@ static int gen8_init_workarounds(struct intel_engine_cs *engine)
>
> static int bdw_init_workarounds(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
>
> ret = gen8_init_workarounds(engine);
> if (ret)
> @@ -891,16 +882,15 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
> /* WaForceContextSaveRestoreNonCoherent:bdw */
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
> - (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
> + (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
>
> return 0;
> }
>
> static int chv_init_workarounds(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
>
> ret = gen8_init_workarounds(engine);
> if (ret)
> @@ -917,8 +907,7 @@ static int chv_init_workarounds(struct intel_engine_cs *engine)
>
> static int gen9_init_workarounds(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> uint32_t tmp;
> int ret;
>
> @@ -941,14 +930,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>
> /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> GEN9_DG_MIRROR_FIX_ENABLE);
>
> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> GEN9_RHWO_OPTIMIZATION_DISABLE);
> /*
> @@ -974,20 +963,20 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> GEN9_CCS_TLB_PREFETCH_ENABLE);
>
> /* WaDisableMaskBasedCammingInRCC:skl,bxt */
> - if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> PIXEL_MASK_CAMMING_DISABLE);
>
> /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
> tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
> - if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
> - IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_F0, REVID_FOREVER) ||
> + IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
> tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
>
> /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
> - if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
> + if (IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> @@ -1013,8 +1002,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>
> static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> u8 vals[3] = { 0, 0, 0 };
> unsigned int i;
>
> @@ -1055,9 +1043,8 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
>
> static int skl_init_workarounds(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
>
> ret = gen9_init_workarounds(engine);
> if (ret)
> @@ -1068,12 +1055,12 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
> * until D0 which is the default case so this is equivalent to
> * !WaDisablePerCtxtPreemptionGranularityControl:skl
> */
> - if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
> I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> }
>
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
> /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
> I915_WRITE(FF_SLICE_CS_CHICKEN2,
> _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
> @@ -1082,24 +1069,24 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
> /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
> * involving this register should also be added to WA batch as required.
> */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
> /* WaDisableLSQCROPERFforOCL:skl */
> I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
> GEN8_LQSC_RO_PERF_DIS);
>
> /* WaEnableGapsTsvCreditFix:skl */
> - if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
> I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> GEN9_GAPS_TSV_CREDIT_DISABLE));
> }
>
> /* WaDisablePowerCompilerClockGating:skl */
> - if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
> WA_SET_BIT_MASKED(HIZ_CHICKEN,
> BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
>
> /* This is tied to WaForceContextSaveRestoreNonCoherent */
> - if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
> + if (IS_SKL_REVID(dev_priv, 0, REVID_FOREVER)) {
> /*
> *Use Force Non-Coherent whenever executing a 3D context. This
> * is a workaround for a possible hang in the unlikely event
> @@ -1115,13 +1102,13 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
> }
>
> /* WaBarrierPerformanceFixDisable:skl */
> - if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
> + if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
> WA_SET_BIT_MASKED(HDC_CHICKEN0,
> HDC_FENCE_DEST_SLM_DISABLE |
> HDC_BARRIER_PERFORMANCE_DISABLE);
>
> /* WaDisableSbeCacheDispatchPortSharing:skl */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
> WA_SET_BIT_MASKED(
> GEN7_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> @@ -1136,9 +1123,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
>
> static int bxt_init_workarounds(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
>
> ret = gen9_init_workarounds(engine);
> if (ret)
> @@ -1146,11 +1132,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>
> /* WaStoreMultiplePTEenable:bxt */
> /* This is a requirement according to Hardware specification */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
>
> /* WaSetClckGatingDisableMedia:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
> ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
> }
> @@ -1160,7 +1146,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> STALL_DOP_GATING_DISABLE);
>
> /* WaDisableSbeCacheDispatchPortSharing:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
> WA_SET_BIT_MASKED(
> GEN7_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> @@ -1170,7 +1156,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
> /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
> /* WaDisableLSQCROPERFforOCL:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
> if (ret)
> return ret;
> @@ -1181,7 +1167,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> }
>
> /* WaProgramL3SqcReg1DefaultForPerf:bxt */
> - if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
> + if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
> I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
> L3_HIGH_PRIO_CREDITS(2));
>
> @@ -1190,24 +1176,23 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>
> int init_workarounds_ring(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> WARN_ON(engine->id != RCS);
>
> dev_priv->workarounds.count = 0;
> dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
>
> - if (IS_BROADWELL(dev))
> + if (IS_BROADWELL(dev_priv))
> return bdw_init_workarounds(engine);
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> return chv_init_workarounds(engine);
>
> - if (IS_SKYLAKE(dev))
> + if (IS_SKYLAKE(dev_priv))
> return skl_init_workarounds(engine);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> return bxt_init_workarounds(engine);
>
> return 0;
> @@ -1215,14 +1200,13 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
>
> static int init_render_ring(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret = init_ring_common(engine);
> if (ret)
> return ret;
>
> /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> - if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
> + if (INTEL_GEN(dev_priv) >= 4 && INTEL_GEN(dev_priv) < 7)
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
>
> /* We need to disable the AsyncFlip performance optimisations in order
> @@ -1231,22 +1215,22 @@ static int init_render_ring(struct intel_engine_cs *engine)
> *
> * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
> */
> - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
> + if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
>
> /* Required for the hardware to program scanline values for waiting */
> /* WaEnableFlushTlbInvalidationMode:snb */
> - if (INTEL_INFO(dev)->gen == 6)
> + if (IS_GEN6(dev_priv))
> I915_WRITE(GFX_MODE,
> _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
>
> /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> - if (IS_GEN7(dev))
> + if (IS_GEN7(dev_priv))
> I915_WRITE(GFX_MODE_GEN7,
> _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
> _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
>
> - if (IS_GEN6(dev)) {
> + if (IS_GEN6(dev_priv)) {
> /* From the Sandybridge PRM, volume 1 part 3, page 24:
> * "If this bit is set, STCunit will have LRA as replacement
> * policy. [...] This bit must be reset. LRA replacement
> @@ -1256,19 +1240,18 @@ static int init_render_ring(struct intel_engine_cs *engine)
> _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
> }
>
> - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
> + if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
> I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>
> - if (HAS_L3_DPF(dev))
> - I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
> + if (HAS_L3_DPF(dev_priv))
> + I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
>
> return init_workarounds_ring(engine);
> }
>
> static void render_ring_cleanup(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> if (dev_priv->semaphore_obj) {
> i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
> @@ -1284,13 +1267,12 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
> {
> #define MBOX_UPDATE_DWORDS 8
> struct intel_engine_cs *signaller = signaller_req->engine;
> - struct drm_device *dev = signaller->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> enum intel_engine_id id;
> int ret, num_rings;
>
> - num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
> #undef MBOX_UPDATE_DWORDS
>
> @@ -1326,13 +1308,12 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> {
> #define MBOX_UPDATE_DWORDS 6
> struct intel_engine_cs *signaller = signaller_req->engine;
> - struct drm_device *dev = signaller->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> enum intel_engine_id id;
> int ret, num_rings;
>
> - num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
> #undef MBOX_UPDATE_DWORDS
>
> @@ -1365,14 +1346,13 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> unsigned int num_dwords)
> {
> struct intel_engine_cs *signaller = signaller_req->engine;
> - struct drm_device *dev = signaller->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *useless;
> enum intel_engine_id id;
> int ret, num_rings;
>
> #define MBOX_UPDATE_DWORDS 3
> - num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
> #undef MBOX_UPDATE_DWORDS
>
> @@ -1460,10 +1440,9 @@ gen8_render_add_request(struct drm_i915_gem_request *req)
> return 0;
> }
>
> -static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
> +static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
> u32 seqno)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> return dev_priv->last_seqno < seqno;
> }
>
> @@ -1481,7 +1460,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
> u32 seqno)
> {
> struct intel_engine_cs *waiter = waiter_req->engine;
> - struct drm_i915_private *dev_priv = waiter->dev->dev_private;
> + struct drm_i915_private *dev_priv = waiter_req->i915;
> struct i915_hw_ppgtt *ppgtt;
> int ret;
>
> @@ -1535,7 +1514,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
> return ret;
>
> /* If seqno wrap happened, omit the wait with no-ops */
> - if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
> + if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
> intel_ring_emit(waiter, dw1 | wait_mbox);
> intel_ring_emit(waiter, seqno);
> intel_ring_emit(waiter, 0);
> @@ -1616,7 +1595,7 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> static void
> gen6_seqno_barrier(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> /* Workaround to force correct ordering between irq and seqno writes on
> * ivb (and maybe also on snb) by reading from a CS register (like
> @@ -1665,8 +1644,7 @@ pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
> static bool
> gen5_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1683,8 +1661,7 @@ gen5_ring_get_irq(struct intel_engine_cs *engine)
> static void
> gen5_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1696,8 +1673,7 @@ gen5_ring_put_irq(struct intel_engine_cs *engine)
> static bool
> i9xx_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (!intel_irqs_enabled(dev_priv))
> @@ -1717,8 +1693,7 @@ i9xx_ring_get_irq(struct intel_engine_cs *engine)
> static void
> i9xx_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1733,8 +1708,7 @@ i9xx_ring_put_irq(struct intel_engine_cs *engine)
> static bool
> i8xx_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (!intel_irqs_enabled(dev_priv))
> @@ -1754,8 +1728,7 @@ i8xx_ring_get_irq(struct intel_engine_cs *engine)
> static void
> i8xx_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1808,8 +1781,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
> static bool
> gen6_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1817,10 +1789,10 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> if (engine->irq_refcount++ == 0) {
> - if (HAS_L3_DPF(dev) && engine->id == RCS)
> + if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
> I915_WRITE_IMR(engine,
> ~(engine->irq_enable_mask |
> - GT_PARITY_ERROR(dev)));
> + GT_PARITY_ERROR(dev_priv)));
> else
> I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
> gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
> @@ -1833,14 +1805,13 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
> static void
> gen6_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> if (--engine->irq_refcount == 0) {
> - if (HAS_L3_DPF(dev) && engine->id == RCS)
> - I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
> + if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
> + I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
> else
> I915_WRITE_IMR(engine, ~0);
> gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
> @@ -1851,8 +1822,7 @@ gen6_ring_put_irq(struct intel_engine_cs *engine)
> static bool
> hsw_vebox_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1871,8 +1841,7 @@ hsw_vebox_get_irq(struct intel_engine_cs *engine)
> static void
> hsw_vebox_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> @@ -1886,8 +1855,7 @@ hsw_vebox_put_irq(struct intel_engine_cs *engine)
> static bool
> gen8_ring_get_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> @@ -1895,7 +1863,7 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> if (engine->irq_refcount++ == 0) {
> - if (HAS_L3_DPF(dev) && engine->id == RCS) {
> + if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
> I915_WRITE_IMR(engine,
> ~(engine->irq_enable_mask |
> GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
> @@ -1912,13 +1880,12 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
> static void
> gen8_ring_put_irq(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = engine->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> if (--engine->irq_refcount == 0) {
> - if (HAS_L3_DPF(dev) && engine->id == RCS) {
> + if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
> I915_WRITE_IMR(engine,
> ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
> } else {
> @@ -2040,12 +2007,12 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
>
> static void cleanup_phys_status_page(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
>
> if (!dev_priv->status_page_dmah)
> return;
>
> - drm_pci_free(engine->dev, dev_priv->status_page_dmah);
> + drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
> engine->status_page.page_addr = NULL;
> }
>
> @@ -2071,7 +2038,7 @@ static int init_status_page(struct intel_engine_cs *engine)
> unsigned flags;
> int ret;
>
> - obj = i915_gem_object_create(engine->dev, 4096);
> + obj = i915_gem_object_create(engine->i915->dev, 4096);
> if (IS_ERR(obj)) {
> DRM_ERROR("Failed to allocate status page\n");
> return PTR_ERR(obj);
> @@ -2082,7 +2049,7 @@ static int init_status_page(struct intel_engine_cs *engine)
> goto err_unref;
>
> flags = 0;
> - if (!HAS_LLC(engine->dev))
> + if (!HAS_LLC(engine->i915))
> /* On g33, we cannot place HWS above 256MiB, so
> * restrict its pinning to the low mappable arena.
> * Though this restriction is not documented for
> @@ -2116,11 +2083,11 @@ err_unref:
>
> static int init_phys_status_page(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> if (!dev_priv->status_page_dmah) {
> dev_priv->status_page_dmah =
> - drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
> + drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
> if (!dev_priv->status_page_dmah)
> return -ENOMEM;
> }
> @@ -2146,10 +2113,9 @@ void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
> ringbuf->vma = NULL;
> }
>
> -int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
> +int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
> struct intel_ringbuffer *ringbuf)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_i915_gem_object *obj = ringbuf->obj;
> /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
> unsigned flags = PIN_OFFSET_BIAS | 4096;
> @@ -2248,13 +2214,13 @@ intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
> * of the buffer.
> */
> ring->effective_size = size;
> - if (IS_I830(engine->dev) || IS_845G(engine->dev))
> + if (IS_I830(engine->i915) || IS_845G(engine->i915))
> ring->effective_size -= 2 * CACHELINE_BYTES;
>
> ring->last_retired_head = -1;
> intel_ring_update_space(ring);
>
> - ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
> + ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
> if (ret) {
> DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
> engine->name, ret);
> @@ -2277,12 +2243,13 @@ intel_ringbuffer_free(struct intel_ringbuffer *ring)
> static int intel_init_ring_buffer(struct drm_device *dev,
> struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_ringbuffer *ringbuf;
> int ret;
>
> WARN_ON(engine->buffer);
>
> - engine->dev = dev;
> + engine->i915 = dev_priv;
> INIT_LIST_HEAD(&engine->active_list);
> INIT_LIST_HEAD(&engine->request_list);
> INIT_LIST_HEAD(&engine->execlist_queue);
> @@ -2300,7 +2267,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
> }
> engine->buffer = ringbuf;
>
> - if (I915_NEED_GFX_HWS(dev)) {
> + if (I915_NEED_GFX_HWS(dev_priv)) {
> ret = init_status_page(engine);
> if (ret)
> goto error;
> @@ -2311,7 +2278,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
> goto error;
> }
>
> - ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
> + ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
> if (ret) {
> DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
> engine->name, ret);
> @@ -2337,11 +2304,11 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
> if (!intel_engine_initialized(engine))
> return;
>
> - dev_priv = to_i915(engine->dev);
> + dev_priv = engine->i915;
>
> if (engine->buffer) {
> intel_stop_engine(engine);
> - WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
> + WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
>
> intel_unpin_ringbuffer_obj(engine->buffer);
> intel_ringbuffer_free(engine->buffer);
> @@ -2351,7 +2318,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
> if (engine->cleanup)
> engine->cleanup(engine);
>
> - if (I915_NEED_GFX_HWS(engine->dev)) {
> + if (I915_NEED_GFX_HWS(dev_priv)) {
> cleanup_status_page(engine);
> } else {
> WARN_ON(engine->id != RCS);
> @@ -2360,7 +2327,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
>
> i915_cmd_parser_fini_ring(engine);
> i915_gem_batch_pool_fini(&engine->batch_pool);
> - engine->dev = NULL;
> + engine->i915 = NULL;
> }
>
> int intel_engine_idle(struct intel_engine_cs *engine)
> @@ -2526,7 +2493,7 @@ int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
>
> void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
> {
> - struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + struct drm_i915_private *dev_priv = engine->i915;
>
> /* Our semaphore implementation is strictly monotonic (i.e. we proceed
> * so long as the semaphore value in the register/page is greater
> @@ -2562,7 +2529,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
> static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
> u32 value)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> /* Every tail move must follow the sequence below */
>
> @@ -2604,7 +2571,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
> return ret;
>
> cmd = MI_FLUSH_DW;
> - if (INTEL_INFO(engine->dev)->gen >= 8)
> + if (INTEL_GEN(req->i915) >= 8)
> cmd += 1;
>
> /* We always require a command barrier so that subsequent
> @@ -2626,7 +2593,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
> intel_ring_emit(engine, cmd);
> intel_ring_emit(engine,
> I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
> - if (INTEL_INFO(engine->dev)->gen >= 8) {
> + if (INTEL_GEN(req->i915) >= 8) {
> intel_ring_emit(engine, 0); /* upper addr */
> intel_ring_emit(engine, 0); /* value */
> } else {
> @@ -2717,7 +2684,6 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate, u32 flush)
> {
> struct intel_engine_cs *engine = req->engine;
> - struct drm_device *dev = engine->dev;
> uint32_t cmd;
> int ret;
>
> @@ -2726,7 +2692,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
> return ret;
>
> cmd = MI_FLUSH_DW;
> - if (INTEL_INFO(dev)->gen >= 8)
> + if (INTEL_GEN(req->i915) >= 8)
> cmd += 1;
>
> /* We always require a command barrier so that subsequent
> @@ -2747,7 +2713,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
> intel_ring_emit(engine, cmd);
> intel_ring_emit(engine,
> I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(req->i915) >= 8) {
> intel_ring_emit(engine, 0); /* upper addr */
> intel_ring_emit(engine, 0); /* value */
> } else {
> @@ -2772,8 +2738,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->hw_id = 0;
> engine->mmio_base = RENDER_RING_BASE;
>
> - if (INTEL_INFO(dev)->gen >= 8) {
> - if (i915_semaphore_is_enabled(dev)) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> obj = i915_gem_object_create(dev, 4096);
> if (IS_ERR(obj)) {
> DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
> @@ -2798,17 +2764,17 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> engine->get_seqno = ring_get_seqno;
> engine->set_seqno = ring_set_seqno;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> WARN_ON(!dev_priv->semaphore_obj);
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_rcs_signal;
> GEN8_RING_SEMAPHORE_INIT(engine);
> }
> - } else if (INTEL_INFO(dev)->gen >= 6) {
> + } else if (INTEL_GEN(dev_priv) >= 6) {
> engine->init_context = intel_rcs_ctx_init;
> engine->add_request = gen6_add_request;
> engine->flush = gen7_render_ring_flush;
> - if (INTEL_INFO(dev)->gen == 6)
> + if (IS_GEN6(dev_priv))
> engine->flush = gen6_render_ring_flush;
> engine->irq_get = gen6_ring_get_irq;
> engine->irq_put = gen6_ring_put_irq;
> @@ -2816,7 +2782,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->irq_seqno_barrier = gen6_seqno_barrier;
> engine->get_seqno = ring_get_seqno;
> engine->set_seqno = ring_set_seqno;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen6_ring_sync;
> engine->semaphore.signal = gen6_signal;
> /*
> @@ -2837,7 +2803,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
> engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
> }
> - } else if (IS_GEN5(dev)) {
> + } else if (IS_GEN5(dev_priv)) {
> engine->add_request = pc_render_add_request;
> engine->flush = gen4_render_ring_flush;
> engine->get_seqno = pc_render_get_seqno;
> @@ -2848,13 +2814,13 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> } else {
> engine->add_request = i9xx_add_request;
> - if (INTEL_INFO(dev)->gen < 4)
> + if (INTEL_GEN(dev_priv) < 4)
> engine->flush = gen2_render_ring_flush;
> else
> engine->flush = gen4_render_ring_flush;
> engine->get_seqno = ring_get_seqno;
> engine->set_seqno = ring_set_seqno;
> - if (IS_GEN2(dev)) {
> + if (IS_GEN2(dev_priv)) {
> engine->irq_get = i8xx_ring_get_irq;
> engine->irq_put = i8xx_ring_put_irq;
> } else {
> @@ -2865,15 +2831,15 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> }
> engine->write_tail = ring_write_tail;
>
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
> engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
> - else if (IS_GEN8(dev))
> + else if (IS_GEN8(dev_priv))
> engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
> - else if (INTEL_INFO(dev)->gen >= 6)
> + else if (INTEL_GEN(dev_priv) >= 6)
> engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> - else if (INTEL_INFO(dev)->gen >= 4)
> + else if (INTEL_GEN(dev_priv) >= 4)
> engine->dispatch_execbuffer = i965_dispatch_execbuffer;
> - else if (IS_I830(dev) || IS_845G(dev))
> + else if (IS_I830(dev_priv) || IS_845G(dev_priv))
> engine->dispatch_execbuffer = i830_dispatch_execbuffer;
> else
> engine->dispatch_execbuffer = i915_dispatch_execbuffer;
> @@ -2881,7 +2847,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->cleanup = render_ring_cleanup;
>
> /* Workaround batchbuffer to combat CS tlb bug. */
> - if (HAS_BROKEN_CS_TLB(dev)) {
> + if (HAS_BROKEN_CS_TLB(dev_priv)) {
> obj = i915_gem_object_create(dev, I830_WA_SIZE);
> if (IS_ERR(obj)) {
> DRM_ERROR("Failed to allocate batch bo\n");
> @@ -2903,7 +2869,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> if (ret)
> return ret;
>
> - if (INTEL_INFO(dev)->gen >= 5) {
> + if (INTEL_GEN(dev_priv) >= 5) {
> ret = intel_init_pipe_control(engine);
> if (ret)
> return ret;
> @@ -2923,24 +2889,24 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> engine->hw_id = 1;
>
> engine->write_tail = ring_write_tail;
> - if (INTEL_INFO(dev)->gen >= 6) {
> + if (INTEL_GEN(dev_priv) >= 6) {
> engine->mmio_base = GEN6_BSD_RING_BASE;
> /* gen6 bsd needs a special wa for tail updates */
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> engine->write_tail = gen6_bsd_ring_write_tail;
> engine->flush = gen6_bsd_ring_flush;
> engine->add_request = gen6_add_request;
> engine->irq_seqno_barrier = gen6_seqno_barrier;
> engine->get_seqno = ring_get_seqno;
> engine->set_seqno = ring_set_seqno;
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> engine->irq_enable_mask =
> GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
> engine->irq_get = gen8_ring_get_irq;
> engine->irq_put = gen8_ring_put_irq;
> engine->dispatch_execbuffer =
> gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT(engine);
> @@ -2951,7 +2917,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> engine->irq_put = gen6_ring_put_irq;
> engine->dispatch_execbuffer =
> gen6_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen6_ring_sync;
> engine->semaphore.signal = gen6_signal;
> engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
> @@ -2972,7 +2938,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> engine->add_request = i9xx_add_request;
> engine->get_seqno = ring_get_seqno;
> engine->set_seqno = ring_set_seqno;
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> engine->irq_get = gen5_ring_get_irq;
> engine->irq_put = gen5_ring_put_irq;
> @@ -3014,7 +2980,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
> engine->irq_put = gen8_ring_put_irq;
> engine->dispatch_execbuffer =
> gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT(engine);
> @@ -3041,13 +3007,13 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> engine->irq_seqno_barrier = gen6_seqno_barrier;
> engine->get_seqno = ring_get_seqno;
> engine->set_seqno = ring_set_seqno;
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> engine->irq_enable_mask =
> GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
> engine->irq_get = gen8_ring_get_irq;
> engine->irq_put = gen8_ring_put_irq;
> engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT(engine);
> @@ -3057,7 +3023,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> engine->irq_get = gen6_ring_get_irq;
> engine->irq_put = gen6_ring_put_irq;
> engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.signal = gen6_signal;
> engine->semaphore.sync_to = gen6_ring_sync;
> /*
> @@ -3102,13 +3068,13 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> engine->get_seqno = ring_get_seqno;
> engine->set_seqno = ring_set_seqno;
>
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_GEN(dev_priv) >= 8) {
> engine->irq_enable_mask =
> GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
> engine->irq_get = gen8_ring_get_irq;
> engine->irq_put = gen8_ring_put_irq;
> engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen8_ring_sync;
> engine->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT(engine);
> @@ -3118,7 +3084,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> engine->irq_get = hsw_vebox_get_irq;
> engine->irq_put = hsw_vebox_put_irq;
> engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen6_ring_sync;
> engine->semaphore.signal = gen6_signal;
> engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 723ff6160fbb..929e7b4af2a4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -141,7 +141,8 @@ struct i915_ctx_workarounds {
> struct drm_i915_gem_object *obj;
> };
>
> -struct intel_engine_cs {
> +struct intel_engine_cs {
> + struct drm_i915_private *i915;
> const char *name;
> enum intel_engine_id {
> RCS = 0,
> @@ -156,7 +157,6 @@ struct intel_engine_cs {
> unsigned int hw_id;
> unsigned int guc_id; /* XXX same as hw_id? */
> u32 mmio_base;
> - struct drm_device *dev;
> struct intel_ringbuffer *buffer;
> struct list_head buffers;
>
> @@ -350,7 +350,7 @@ struct intel_engine_cs {
> static inline bool
> intel_engine_initialized(struct intel_engine_cs *engine)
> {
> - return engine->dev != NULL;
> + return engine->i915 != NULL;
> }
>
> static inline unsigned
> @@ -425,7 +425,7 @@ intel_write_status_page(struct intel_engine_cs *engine,
>
> struct intel_ringbuffer *
> intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
> -int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
> +int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
> struct intel_ringbuffer *ringbuf);
> void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
> void intel_ringbuffer_free(struct intel_ringbuffer *ring);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 4f1dfe616856..4ea2bf2c2a4a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1381,7 +1381,7 @@ void intel_uncore_init(struct drm_device *dev)
> break;
> }
>
> - if (intel_vgpu_active(dev)) {
> + if (intel_vgpu_active(dev_priv)) {
> ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
> ASSIGN_READ_MMIO_VFUNCS(vgpu);
> }
> @@ -1663,8 +1663,8 @@ static int wait_for_register_fw(struct drm_i915_private *dev_priv,
>
> static int gen8_request_engine_reset(struct intel_engine_cs *engine)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> int ret;
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
>
> I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
> _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
> @@ -1682,7 +1682,7 @@ static int gen8_request_engine_reset(struct intel_engine_cs *engine)
>
> static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->dev->dev_private;
> + struct drm_i915_private *dev_priv = engine->i915;
>
> I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
> _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
> @@ -1802,10 +1802,10 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
> {
> enum forcewake_domains fw_domains;
>
> - if (intel_vgpu_active(dev_priv->dev))
> + if (intel_vgpu_active(dev_priv))
> return 0;
>
> - switch (INTEL_INFO(dev_priv)->gen) {
> + switch (INTEL_GEN(dev_priv)) {
> case 9:
> fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg));
> break;
> @@ -1842,10 +1842,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
> {
> enum forcewake_domains fw_domains;
>
> - if (intel_vgpu_active(dev_priv->dev))
> + if (intel_vgpu_active(dev_priv))
> return 0;
>
> - switch (INTEL_INFO(dev_priv)->gen) {
> + switch (INTEL_GEN(dev_priv)) {
> case 9:
> fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
> break;
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2016-05-05 12:54 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-05-05 9:15 [PATCH 01/19] drm: Restore double clflush on the last partial cacheline Chris Wilson
2016-05-05 9:15 ` [PATCH 02/19] drm/i915/execlists: Refactor common engine setup Chris Wilson
2016-05-05 10:18 ` Tvrtko Ursulin
2016-05-05 10:33 ` Chris Wilson
2016-05-05 11:17 ` Tvrtko Ursulin
2016-05-05 11:55 ` Tvrtko Ursulin
2016-05-05 9:15 ` [PATCH 03/19] drm/i915: Store a i915 backpointer from engine, and use it Chris Wilson
2016-05-05 11:15 ` Tvrtko Ursulin
2016-05-05 11:26 ` Chris Wilson
2016-05-05 11:37 ` [PATCH v2] " Chris Wilson
2016-05-05 12:54 ` Tvrtko Ursulin
2016-05-05 9:15 ` [PATCH 04/19] drm/i915/shrinker: Flush active on objects before counting Chris Wilson
2016-05-05 9:15 ` [PATCH 05/19] drm/i915: Delay queuing hangcheck to wait-request Chris Wilson
2016-05-05 9:15 ` [PATCH 06/19] drm/i915: Remove the dedicated hangcheck workqueue Chris Wilson
2016-05-05 9:15 ` [PATCH 07/19] drm/i915: Make queueing the hangcheck work inline Chris Wilson
2016-05-05 9:15 ` [PATCH 08/19] drm/i915: Slaughter the thundering i915_wait_request herd Chris Wilson
2016-05-05 9:15 ` [PATCH 09/19] drm/i915: Remove the lazy_coherency parameter from request-completed? Chris Wilson
2016-05-05 9:15 ` [PATCH 10/19] drm/i915: Use HWS for seqno tracking everywhere Chris Wilson
2016-05-05 9:16 ` [PATCH 11/19] drm/i915: Add a delay between interrupt and inspecting the final seqno (ilk) Chris Wilson
2016-05-05 9:16 ` [PATCH 12/19] drm/i915: Check the CPU cached value of seqno after waking the waiter Chris Wilson
2016-05-05 9:16 ` [PATCH 13/19] drm/i915: Only apply one barrier after a breadcrumb interrupt is posted Chris Wilson
2016-05-05 9:16 ` [PATCH 14/19] drm/i915: Stop setting wraparound seqno on initialisation Chris Wilson
2016-05-05 9:16 ` [PATCH 15/19] drm/i915: Only query timestamp when measuring elapsed time Chris Wilson
2016-05-05 9:16 ` [PATCH 16/19] drm/i915: Convert trace-irq to the breadcrumb waiter Chris Wilson
2016-05-05 9:16 ` [PATCH 17/19] drm/i915: Move the get/put irq locking into the caller Chris Wilson
2016-05-05 9:16 ` [PATCH 18/19] drm/i915: Simplify enabling user-interrupts with L3-remapping Chris Wilson
2016-05-05 9:16 ` [PATCH 19/19] drm/i915: Remove debug noise on detecting fault-injection of missed interrupts Chris Wilson
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