From: Jon Hunter <jonathanh@nvidia.com>
To: Laxman Dewangan <ldewangan@nvidia.com>,
thierry.reding@gmail.com, airlied@linux.ie,
swarren@wwwdotorg.org
Cc: gnurou@gmail.com, dri-devel@lists.freedesktop.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V6 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage
Date: Fri, 20 May 2016 15:11:10 +0100 [thread overview]
Message-ID: <573F1AFE.3080906@nvidia.com> (raw)
In-Reply-To: <573F125A.20102@nvidia.com>
On 20/05/16 14:34, Laxman Dewangan wrote:
>
> On Friday 20 May 2016 07:02 PM, Jon Hunter wrote:
>> On 20/05/16 12:59, Laxman Dewangan wrote:
>>> +/* tegra_io_pads_config_info: Tegra IO pads bit config info.
>>> + * @dpd_config_bit: DPD configuration bit position. -1 if not
>>> supported.
>>> + * @voltage_config_bit: Voltage configuration bit position. -1 if
>>> not supported.
>>> + * @soc_mask: Bitwise OR of SoC masks if IO pads supported on that SoC.
>>> + */
>> Comment coding style :-(
>
> I saw this style multiple places and so intentionally left here.
> If comment is inside the code then
> /*
> * first-line comment
> * second line
> */
>
> but for function, it can have in single line.
>
> Anyhow, I will correct in next cycle.
Actually, this should be in kernel-doc format [0].
Jon
[0] Documentation/kernel-doc-nano-HOWTO.txt
WARNING: multiple messages have this Message-ID (diff)
From: Jon Hunter <jonathanh@nvidia.com>
To: Laxman Dewangan <ldewangan@nvidia.com>,
<thierry.reding@gmail.com>, <airlied@linux.ie>,
<swarren@wwwdotorg.org>
Cc: <gnurou@gmail.com>, <dri-devel@lists.freedesktop.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V6 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage
Date: Fri, 20 May 2016 15:11:10 +0100 [thread overview]
Message-ID: <573F1AFE.3080906@nvidia.com> (raw)
In-Reply-To: <573F125A.20102@nvidia.com>
On 20/05/16 14:34, Laxman Dewangan wrote:
>
> On Friday 20 May 2016 07:02 PM, Jon Hunter wrote:
>> On 20/05/16 12:59, Laxman Dewangan wrote:
>>> +/* tegra_io_pads_config_info: Tegra IO pads bit config info.
>>> + * @dpd_config_bit: DPD configuration bit position. -1 if not
>>> supported.
>>> + * @voltage_config_bit: Voltage configuration bit position. -1 if
>>> not supported.
>>> + * @soc_mask: Bitwise OR of SoC masks if IO pads supported on that SoC.
>>> + */
>> Comment coding style :-(
>
> I saw this style multiple places and so intentionally left here.
> If comment is inside the code then
> /*
> * first-line comment
> * second line
> */
>
> but for function, it can have in single line.
>
> Anyhow, I will correct in next cycle.
Actually, this should be in kernel-doc format [0].
Jon
[0] Documentation/kernel-doc-nano-HOWTO.txt
next prev parent reply other threads:[~2016-05-20 14:11 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-20 11:59 [PATCH V6 0/3] soc/tegra: Add support for IO pads power and voltage control Laxman Dewangan
2016-05-20 11:59 ` Laxman Dewangan
2016-05-20 11:59 ` [PATCH V6 1/3] soc/tegra: pmc: Use BIT macro for register field definition Laxman Dewangan
2016-05-20 11:59 ` Laxman Dewangan
[not found] ` <1463745564-19297-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-05-20 11:59 ` [PATCH V6 2/3] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl() Laxman Dewangan
2016-05-20 11:59 ` Laxman Dewangan
2016-05-20 11:59 ` [PATCH V6 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Laxman Dewangan
2016-05-20 11:59 ` Laxman Dewangan
2016-05-20 13:32 ` Jon Hunter
2016-05-20 13:32 ` Jon Hunter
[not found] ` <573F11F5.7010702-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-05-20 13:34 ` Laxman Dewangan
2016-05-20 13:34 ` Laxman Dewangan
[not found] ` <573F125A.20102-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-05-20 14:06 ` Jon Hunter
2016-05-20 14:06 ` Jon Hunter
2016-05-20 14:11 ` Jon Hunter [this message]
2016-05-20 14:11 ` Jon Hunter
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