[PATCH 1/6] drm/amdgpu/si: stop dma engines on hw fini and suspend

[PATCH 1/6] drm/amdgpu/si: stop dma engines on hw fini and suspend

[Alex Deucher]

Fixes failure on suspend due to rings not being marked
as not ready.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dma.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 873dd49..2aa6517 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -134,6 +134,23 @@ static void si_dma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0, 0));
 }
 
+static void si_dma_stop(struct amdgpu_device *adev)
+{
+	struct amdgpu_ring *ring;
+	u32 rb_cntl;
+	unsigned i;
+
+	for (i = 0; i < 2; i++) {
+		ring = &adev->sdma.instance[i].ring;
+		/* dma0 */
+		rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]);
+		rb_cntl &= ~DMA_RB_ENABLE;
+		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
+
+		ring->ready = false;
+	}
+}
+
 static int si_dma_gfx_resume(struct amdgpu_device *adev)
 {
 	struct amdgpu_ring *ring;
@@ -612,6 +629,10 @@ static int si_dma_hw_init(void *handle)
 
 static int si_dma_hw_fini(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+	si_dma_stop(adev);
+
 	return 0;
 }
 
-- 
2.5.5

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[PATCH 2/6] drm/amdgpu/si: simplify si_dma_start

[Alex Deucher]

Remove the wrapper that was a left over from porting the code
into amdgpu.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dma.c | 19 +------------------
 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 2aa6517..03c11a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -151,7 +151,7 @@ static void si_dma_stop(struct amdgpu_device *adev)
 	}
 }
 
-static int si_dma_gfx_resume(struct amdgpu_device *adev)
+static int si_dma_start(struct amdgpu_device *adev)
 {
 	struct amdgpu_ring *ring;
 	u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz, reg_offset;
@@ -215,23 +215,6 @@ static int si_dma_gfx_resume(struct amdgpu_device *adev)
 }
 
 /**
- * si_dma_start - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the DMA engines and enable them (VI).
- * Returns 0 for success, error for failure.
- */
-static int si_dma_start(struct amdgpu_device *adev)
-{
-	int r;
-
-	r = si_dma_gfx_resume(adev);
-
-	return r;
-}
-
-/**
  * si_dma_ring_test_ring - simple async dma engine test
  *
  * @ring: amdgpu_ring structure holding ring information
-- 
2.5.5

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[PATCH 3/6] drm/amdgpu/si: replace some hardcoded 2s with dma num_instances

[Alex Deucher]

Fix up a few cases that were previously missed.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dma.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 03c11a1..7e65b64 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -140,7 +140,7 @@ static void si_dma_stop(struct amdgpu_device *adev)
 	u32 rb_cntl;
 	unsigned i;
 
-	for (i = 0; i < 2; i++) {
+	for (i = 0; i < adev->sdma.num_instances; i++) {
 		ring = &adev->sdma.instance[i].ring;
 		/* dma0 */
 		rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]);
@@ -158,7 +158,7 @@ static int si_dma_start(struct amdgpu_device *adev)
 	int i, r;
 	uint64_t rptr_addr;
 
-	for (i = 0; i < 2; i++) {
+	for (i = 0; i < adev->sdma.num_instances; i++) {
 		ring = &adev->sdma.instance[i].ring;
 		reg_offset = sdma_offsets[i];
 
@@ -755,13 +755,12 @@ static int si_dma_set_clockgating_state(void *handle,
 	u32 orig, data, offset;
 	int i;
 	bool enable;
-
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	enable = (state == AMD_CG_STATE_GATE) ? true : false;
 
 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
-		for (i = 0; i < 2; i++) {
+		for (i = 0; i < adev->sdma.num_instances; i++) {
 			if (i == 0)
 				offset = DMA0_REGISTER_OFFSET;
 			else
@@ -773,7 +772,7 @@ static int si_dma_set_clockgating_state(void *handle,
 			WREG32(DMA_CLK_CTRL + offset, 0x00000100);
 		}
 	} else {
-		for (i = 0; i < 2; i++) {
+		for (i = 0; i < adev->sdma.num_instances; i++) {
 			if (i == 0)
 				offset = DMA0_REGISTER_OFFSET;
 			else
-- 
2.5.5

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[PATCH 4/6] drm/amdgpu/si: use dma instance offset array directly

[Alex Deucher]

No need for a local variable.  Also, fix a few registers
that did not have the per instance offset properly added.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dma.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 7e65b64..4dad157 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -154,16 +154,15 @@ static void si_dma_stop(struct amdgpu_device *adev)
 static int si_dma_start(struct amdgpu_device *adev)
 {
 	struct amdgpu_ring *ring;
-	u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz, reg_offset;
+	u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz;
 	int i, r;
 	uint64_t rptr_addr;
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
 		ring = &adev->sdma.instance[i].ring;
-		reg_offset = sdma_offsets[i];
 
-		WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
-		WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
+		WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
+		WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 
 		/* Set ring buffer size in dwords */
 		rb_bufsz = order_base_2(ring->ring_size / 4);
@@ -171,36 +170,36 @@ static int si_dma_start(struct amdgpu_device *adev)
 #ifdef __BIG_ENDIAN
 		rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
 #endif
-		WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
+		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
 
 		/* Initialize the ring buffer's read and write pointers */
-		WREG32(DMA_RB_RPTR + reg_offset, 0);
-		WREG32(DMA_RB_WPTR + reg_offset, 0);
+		WREG32(DMA_RB_RPTR + sdma_offsets[i], 0);
+		WREG32(DMA_RB_WPTR + sdma_offsets[i], 0);
 
 		rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
 
-		WREG32(DMA_RB_RPTR_ADDR_LO, lower_32_bits(rptr_addr));
-		WREG32(DMA_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
+		WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr));
+		WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF);
 
 		rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
 
-		WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
+		WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 
 		/* enable DMA IBs */
 		ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
 #ifdef __BIG_ENDIAN
 		ib_cntl |= DMA_IB_SWAP_ENABLE;
 #endif
-		WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
+		WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl);
 
-		dma_cntl = RREG32(DMA_CNTL + reg_offset);
+		dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]);
 		dma_cntl &= ~CTXEMPTY_INT_ENABLE;
-		WREG32(DMA_CNTL + reg_offset, dma_cntl);
+		WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl);
 
 		ring->wptr = 0;
-		WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
+		WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 
-		WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
+		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE);
 
 		ring->ready = true;
 
-- 
2.5.5

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[PATCH 5/6] drm/amdgpu/si: reduce dma ring size

[Alex Deucher]

This was already done for other asics.  We don't need
a very big ring with the scheduler.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 4dad157..5dc10a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -573,7 +573,7 @@ static int si_dma_sw_init(void *handle)
 		ring->ring_obj = NULL;
 		ring->use_doorbell = false;
 		sprintf(ring->name, "sdma%d", i);
-		r = amdgpu_ring_init(adev, ring, 64 * 1024,
+		r = amdgpu_ring_init(adev, ring, 1024,
 				     DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), 0xf,
 				     &adev->sdma.trap_irq,
 				     (i == 0) ?
-- 
2.5.5

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[PATCH 6/6] drm/amdgpu/si: reduce gfx ring size

[Alex Deucher]

This was already done for other asics.  We don't need
a very big ring with the scheduler.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index a8cf04f..b9093a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2805,7 +2805,7 @@ static int gfx_v6_0_sw_init(void *handle)
 		ring = &adev->gfx.gfx_ring[i];
 		ring->ring_obj = NULL;
 		sprintf(ring->name, "gfx");
-		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
+		r = amdgpu_ring_init(adev, ring, 1024,
 				     0x80000000, 0xf,
 				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
 				     AMDGPU_RING_TYPE_GFX);
-- 
2.5.5

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Re: [PATCH 1/6] drm/amdgpu/si: stop dma engines on hw fini and suspend

[Christian König]

Am 20.05.2016 um 23:50 schrieb Alex Deucher:
> Fixes failure on suspend due to rings not being marked
> as not ready.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

For this series: Reviewed-by: Christian König <christian.koenig@amd.com>

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/si_dma.c | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 873dd49..2aa6517 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -134,6 +134,23 @@ static void si_dma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
>   	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0, 0));
>   }
>   
> +static void si_dma_stop(struct amdgpu_device *adev)
> +{
> +	struct amdgpu_ring *ring;
> +	u32 rb_cntl;
> +	unsigned i;
> +
> +	for (i = 0; i < 2; i++) {
> +		ring = &adev->sdma.instance[i].ring;
> +		/* dma0 */
> +		rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]);
> +		rb_cntl &= ~DMA_RB_ENABLE;
> +		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
> +
> +		ring->ready = false;
> +	}
> +}
> +
>   static int si_dma_gfx_resume(struct amdgpu_device *adev)
>   {
>   	struct amdgpu_ring *ring;
> @@ -612,6 +629,10 @@ static int si_dma_hw_init(void *handle)
>   
>   static int si_dma_hw_fini(void *handle)
>   {
> +	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +
> +	si_dma_stop(adev);
> +
>   	return 0;
>   }
>   

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