R8A7795 FDP1 clock parentage

R8A7795 FDP1 clock parentage

[Kieran Bingham]

Hi Morimoto-san,

I have added an initial patch to support the FDP1 in the clock
framework, but I have not been able to correctly identify the actual
clock parent.

For now I have assumed that it is R8A7795_CLK_S2D1.

Could you please confirm this selection, or help identify the true
parent please?
--
Regards

Kieran

Re: R8A7795 FDP1 clock parentage

[Kuninori Morimoto]

Hi Kieran

> I have added an initial patch to support the FDP1 in the clock
> framework, but I have not been able to correctly identify the actual
> clock parent.
> 
> For now I have assumed that it is R8A7795_CLK_S2D1.
> 
> Could you please confirm this selection, or help identify the true
> parent please?

OK, please wait

Re: R8A7795 FDP1 clock parentage

[Kieran Bingham]

On 25/05/16 09:49, Kuninori Morimoto wrote:
> 
> Hi Kieran
> 
>> I have added an initial patch to support the FDP1 in the clock
>> framework, but I have not been able to correctly identify the actual
>> clock parent.
>>
>> For now I have assumed that it is R8A7795_CLK_S2D1.
>>
>> Could you please confirm this selection, or help identify the true
>> parent please?
> 
> OK, please wait

Thanks,

Just to add to this request, could you ask the HW engineers to confirm
the clock parents for the FCPF (0,1,2) as well please?

They too are currently listed as R8A7795_CLK_S2D1, however now that I am
trying to enable the FCPF and read registers from it - the VCR is
returning as 0x00 (I expect 0x0101) and then I'm getting
 "Bad mode in Error handler detected, code 0xbf000002 -- SError"

My suspicion is that my clock has not been enabled correctly :)

Thanks again for your help
-- 
Regards

Kieran Bingham

Re: R8A7795 FDP1 clock parentage

[Kuninori Morimoto]

Hi Kieran

> Just to add to this request, could you ask the HW engineers to confirm
> the clock parents for the FCPF (0,1,2) as well please?
> 
> They too are currently listed as R8A7795_CLK_S2D1, however now that I am
> trying to enable the FCPF and read registers from it - the VCR is
> returning as 0x00 (I expect 0x0101) and then I'm getting
>  "Bad mode in Error handler detected, code 0xbf000002 -- SError"
> 
> My suspicion is that my clock has not been enabled correctly :)

About FCP, I had same request from Laurent, and its answer was this thread.

http://thread.gmane.org/gmane.linux.kernel.renesas-soc/662/focus=1304

# I think this "parent clock" settings itself is not super critical
# (= it works anyway with wrong settings)
# it seems other issues ?

Best regards
---
Kuninori Morimoto

Re: R8A7795 FDP1 clock parentage

[Kuninori Morimoto]

Hi Kieran

> > Just to add to this request, could you ask the HW engineers to confirm
> > the clock parents for the FCPF (0,1,2) as well please?
> > 
> > They too are currently listed as R8A7795_CLK_S2D1, however now that I am
> > trying to enable the FCPF and read registers from it - the VCR is
> > returning as 0x00 (I expect 0x0101) and then I'm getting
> >  "Bad mode in Error handler detected, code 0xbf000002 -- SError"
> > 
> > My suspicion is that my clock has not been enabled correctly :)
> 
> About FCP, I had same request from Laurent, and its answer was this thread.
> 
> http://thread.gmane.org/gmane.linux.kernel.renesas-soc/662/focus=1304
> 
> # I think this "parent clock" settings itself is not super critical
> # (= it works anyway with wrong settings)
> # it seems other issues ?

I got information from HW team.
About H3 ES1 FDP1 parent clock is "S2D1"

Re: R8A7795 FDP1 clock parentage

[Kieran Bingham]

Hi Morimoto-san,

On 30/05/16 07:32, Kuninori Morimoto wrote:
>>> Just to add to this request, could you ask the HW engineers to confirm
>>> the clock parents for the FCPF (0,1,2) as well please?
>>>
>>> They too are currently listed as R8A7795_CLK_S2D1, however now that I am
>>> trying to enable the FCPF and read registers from it - the VCR is
>>> returning as 0x00 (I expect 0x0101) and then I'm getting
>>>  "Bad mode in Error handler detected, code 0xbf000002 -- SError"
>>>
>>> My suspicion is that my clock has not been enabled correctly :)
>>
>> About FCP, I had same request from Laurent, and its answer was this thread.
>>
>> http://thread.gmane.org/gmane.linux.kernel.renesas-soc/662/focus=1304

Thank you for that reference. It was helpful!

>> # I think this "parent clock" settings itself is not super critical
>> # (= it works anyway with wrong settings)
>> # it seems other issues ?

You were right :) - It was the power-domain. It's resolved now and
working. Thank you for your help.

> I got information from HW team.
> About H3 ES1 FDP1 parent clock is "S2D1"

Perfect, thanks for confirming this. Now the patch is unblocked from
submission.

-- 
Regards

Kieran Bingham