From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config
Date: Thu, 26 May 2016 18:12:04 +0200 [thread overview]
Message-ID: <57472054.3040207@denx.de> (raw)
In-Reply-To: <20160526155850.25412-3-paul.burton@imgtec.com>
On 05/26/2016 05:58 PM, Paul Burton wrote:
> Allow L1 Icache & L1 Dcache line size to be specified separately, since
> there's no architectural mandate that they be the same. The
> [id]cache_line_size functions are tidied up to take advantage of the
> fact that the Kconfig entries are always present to simply check them
> for zero rather than needing to #ifdef on their presence.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
>
> arch/mips/Kconfig | 6 +++++-
> arch/mips/lib/cache.c | 22 +++++++---------------
> arch/mips/lib/cache_init.S | 4 ++--
> board/dbau1x00/Kconfig | 5 ++++-
> board/micronas/vct/Kconfig | 5 ++++-
> board/pb1x00/Kconfig | 5 ++++-
> board/qca/ap121/Kconfig | 5 ++++-
> board/qca/ap143/Kconfig | 5 ++++-
> board/qemu-mips/Kconfig | 5 ++++-
> board/tplink/wdr4300/Kconfig | 5 ++++-
> 10 files changed, 42 insertions(+), 25 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 13f1164..8af8799 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -247,11 +247,15 @@ config SYS_DCACHE_SIZE
> hex
> default 0
>
> +config SYS_DCACHE_LINE_SIZE
> + hex
> + default 0
> +
> config SYS_ICACHE_SIZE
> hex
> default 0
>
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
Be careful here, CONFIG_SYS_CACHELINE_SIZE is established all over the
u-boot, so this might cause build breakage. You should keep some
compatibility CONFIG_SYS_CACHELINE_SIZE entry and set it to default to
SYS_DCACHE_LINE_SIZE , since it's mostly used for DMA anyway.
> hex
> default 0
>
> diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
> index 7695325..2bb91c6 100644
> --- a/arch/mips/lib/cache.c
> +++ b/arch/mips/lib/cache.c
> @@ -9,23 +9,13 @@
> #include <asm/cacheops.h>
> #include <asm/mipsregs.h>
>
> -#if CONFIG_SYS_CACHELINE_SIZE != 0
> -
> static inline unsigned long icache_line_size(void)
> {
> - return CONFIG_SYS_CACHELINE_SIZE;
> -}
> -
> -static inline unsigned long dcache_line_size(void)
> -{
> - return CONFIG_SYS_CACHELINE_SIZE;
> -}
> + unsigned long conf1, il;
>
> -#else /* !CONFIG_SYS_CACHELINE_SIZE */
> + if (CONFIG_SYS_ICACHE_LINE_SIZE != 0)
> + return CONFIG_SYS_ICACHE_LINE_SIZE;
>
> -static inline unsigned long icache_line_size(void)
> -{
> - unsigned long conf1, il;
> conf1 = read_c0_config1();
> il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
> if (!il)
> @@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
> static inline unsigned long dcache_line_size(void)
> {
> unsigned long conf1, dl;
> +
> + if (CONFIG_SYS_DCACHE_LINE_SIZE != 0)
> + return CONFIG_SYS_DCACHE_LINE_SIZE;
> +
> conf1 = read_c0_config1();
> dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
> if (!dl)
> @@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void)
> return 2 << dl;
> }
>
> -#endif /* !CONFIG_SYS_CACHELINE_SIZE */
> -
> void flush_cache(ulong start_addr, ulong size)
> {
> unsigned long ilsize = icache_line_size();
> diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
> index e4a44ff..41cb3a6 100644
> --- a/arch/mips/lib/cache_init.S
> +++ b/arch/mips/lib/cache_init.S
> @@ -101,14 +101,14 @@
> LEAF(mips_cache_reset)
> #if CONFIG_SYS_ICACHE_SIZE != 0
> li t2, CONFIG_SYS_ICACHE_SIZE
> - li t8, CONFIG_SYS_CACHELINE_SIZE
> + li t8, CONFIG_SYS_ICACHE_LINE_SIZE
> #else
> l1_info t2, t8, MIPS_CONF1_IA_SHF
> #endif
>
> #if CONFIG_SYS_DCACHE_SIZE != 0
> li t3, CONFIG_SYS_DCACHE_SIZE
> - li t9, CONFIG_SYS_CACHELINE_SIZE
> + li t9, CONFIG_SYS_DCACHE_LINE_SIZE
> #else
> l1_info t3, t9, MIPS_CONF1_DA_SHF
> #endif
> diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
> index 1715a28..448176d 100644
> --- a/board/dbau1x00/Kconfig
> +++ b/board/dbau1x00/Kconfig
> @@ -15,10 +15,13 @@ config SYS_TEXT_BASE
> config SYS_DCACHE_SIZE
> default 16384
>
> +config SYS_DCACHE_LINE_SIZE
> + default 32
> +
> config SYS_ICACHE_SIZE
> default 16384
>
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
> default 32
>
> menu "dbau1x00 board options"
> diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
> index 5bb6f03..df7c029 100644
> --- a/board/micronas/vct/Kconfig
> +++ b/board/micronas/vct/Kconfig
> @@ -15,10 +15,13 @@ config SYS_TEXT_BASE
> config SYS_DCACHE_SIZE
> default 16384
>
> +config SYS_DCACHE_LINE_SIZE
> + default 32
> +
> config SYS_ICACHE_SIZE
> default 16384
>
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
> default 32
>
> menu "vct board options"
> diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
> index 27b2ef0..ef8905d 100644
> --- a/board/pb1x00/Kconfig
> +++ b/board/pb1x00/Kconfig
> @@ -15,10 +15,13 @@ config SYS_TEXT_BASE
> config SYS_DCACHE_SIZE
> default 16384
>
> +config SYS_DCACHE_LINE_SIZE
> + default 32
> +
> config SYS_ICACHE_SIZE
> default 16384
>
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
> default 32
>
> endif
> diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
> index 1ace0e5..09a06d8 100644
> --- a/board/qca/ap121/Kconfig
> +++ b/board/qca/ap121/Kconfig
> @@ -15,10 +15,13 @@ config SYS_TEXT_BASE
> config SYS_DCACHE_SIZE
> default 0x8000
>
> +config SYS_DCACHE_LINE_SIZE
> + default 32
> +
> config SYS_ICACHE_SIZE
> default 0x10000
>
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
> default 32
>
> endif
> diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
> index ac73782..f3d658d 100644
> --- a/board/qca/ap143/Kconfig
> +++ b/board/qca/ap143/Kconfig
> @@ -15,10 +15,13 @@ config SYS_TEXT_BASE
> config SYS_DCACHE_SIZE
> default 0x8000
>
> +config SYS_DCACHE_LINE_SIZE
> + default 32
> +
> config SYS_ICACHE_SIZE
> default 0x10000
>
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
> default 32
>
> endif
> diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
> index 66957e7..e696a12 100644
> --- a/board/qemu-mips/Kconfig
> +++ b/board/qemu-mips/Kconfig
> @@ -14,10 +14,13 @@ config SYS_TEXT_BASE
> config SYS_DCACHE_SIZE
> default 16384
>
> +config SYS_DCACHE_LINE_SIZE
> + default 32
> +
> config SYS_ICACHE_SIZE
> default 16384
>
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
> default 32
>
> endif
> diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
> index bbec2e5..86afd76 100644
> --- a/board/tplink/wdr4300/Kconfig
> +++ b/board/tplink/wdr4300/Kconfig
> @@ -18,10 +18,13 @@ config SYS_TEXT_BASE
> config SYS_DCACHE_SIZE
> default 0x8000
>
> +config SYS_DCACHE_LINE_SIZE
> + default 32
> +
> config SYS_ICACHE_SIZE
> default 0x10000
>
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
> default 32
>
> endif
>
--
Best regards,
Marek Vasut
next prev parent reply other threads:[~2016-05-26 16:12 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-26 15:58 [U-Boot] [PATCH 0/3] MIPS cache cleanups Paul Burton
2016-05-26 15:58 ` [U-Boot] [PATCH 1/3] MIPS: Move cache sizes to Kconfig Paul Burton
2016-05-26 16:10 ` Marek Vasut
2016-05-27 10:36 ` Paul Burton
2016-05-27 14:32 ` Marek Vasut
2016-05-27 14:34 ` Paul Burton
2016-05-27 14:40 ` Marek Vasut
2016-05-27 14:54 ` Paul Burton
2016-05-28 12:18 ` Marek Vasut
2016-05-27 15:43 ` Daniel Schwierzeck
2016-05-28 12:03 ` Marek Vasut
2016-05-31 16:21 ` Zubair Lutfullah Kakakhel
2016-05-31 8:00 ` Daniel Schwierzeck
2016-05-26 15:58 ` [U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config Paul Burton
2016-05-26 16:12 ` Marek Vasut [this message]
2016-05-27 11:21 ` Daniel Schwierzeck
2016-05-31 8:01 ` Daniel Schwierzeck
2016-05-26 15:58 ` [U-Boot] [PATCH 3/3] MIPS: Abstract cache op loops with a macro Paul Burton
2016-05-26 16:13 ` Marek Vasut
2016-05-27 10:30 ` Paul Burton
2016-05-27 14:36 ` Marek Vasut
2016-05-27 14:48 ` Paul Burton
2016-05-28 12:27 ` Marek Vasut
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