[U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config

[Daniel Schwierzeck <daniel.schwierzeck@gmail.com>]

Am 26.05.2016 um 18:12 schrieb Marek Vasut:
> On 05/26/2016 05:58 PM, Paul Burton wrote:
>> Allow L1 Icache & L1 Dcache line size to be specified separately, since
>> there's no architectural mandate that they be the same. The
>> [id]cache_line_size functions are tidied up to take advantage of the
>> fact that the Kconfig entries are always present to simply check them
>> for zero rather than needing to #ifdef on their presence.
>>
>> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
>> ---
>>
>>  arch/mips/Kconfig            |  6 +++++-
>>  arch/mips/lib/cache.c        | 22 +++++++---------------
>>  arch/mips/lib/cache_init.S   |  4 ++--
>>  board/dbau1x00/Kconfig       |  5 ++++-
>>  board/micronas/vct/Kconfig   |  5 ++++-
>>  board/pb1x00/Kconfig         |  5 ++++-
>>  board/qca/ap121/Kconfig      |  5 ++++-
>>  board/qca/ap143/Kconfig      |  5 ++++-
>>  board/qemu-mips/Kconfig      |  5 ++++-
>>  board/tplink/wdr4300/Kconfig |  5 ++++-
>>  10 files changed, 42 insertions(+), 25 deletions(-)
>>
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index 13f1164..8af8799 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -247,11 +247,15 @@ config SYS_DCACHE_SIZE
>>  	hex
>>  	default 0
>>  
>> +config SYS_DCACHE_LINE_SIZE
>> +	hex
>> +	default 0
>> +
>>  config SYS_ICACHE_SIZE
>>  	hex
>>  	default 0
>>  
>> -config SYS_CACHELINE_SIZE
>> +config SYS_ICACHE_LINE_SIZE
> 
> Be careful here, CONFIG_SYS_CACHELINE_SIZE is established all over the
> u-boot, so this might cause build breakage. You should keep some
> compatibility CONFIG_SYS_CACHELINE_SIZE entry and set it to default to
> SYS_DCACHE_LINE_SIZE , since it's mostly used for DMA anyway.

Marek is right. Some USB drivers still use CONFIG_SYS_CACHELINE_SIZE
instead of ARCH_DMA_MINALIGN so CONFIG_SYS_CACHELINE_SIZE needs to be
kept as Kconfig symbol.

-- 
- Daniel

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