[Qemu-devel] [PATCH v2 00/12] tcg: Add fence opcode

[Qemu-devel] [PATCH v2 00/12] tcg: Add fence opcode

[Richard Henderson]

This is a reorg of Pranith's first patch set, correcting a few
mistakes and adding backend support for all of the other hosts.

In addition, I added front-end support for Alpha, since I didn't
actually have any armv7 images handy to test the backends.

Be warned: Only x86, ppc, aarch64, and tci have been compile
tested so far.


r~


Richard Henderson (12):
  Introduce TCGOpcode for fence instruction
  tcg/i386: Add support for fence
  tcg/aarch64: Add support for fence
  tcg/arm: Add support for fence
  tcg/ia64: Add support for fence
  tcg/mips: Add support for fence
  tcg/ppc: Add support for fence
  tcg/s390: Add support for fence
  tcg/sparc: Add support for fence
  tcg/tci: Add support for fence
  target-arm: Add frontend support for fence gen in ARMv7
  target-alpha: Generate fence opcodes

 target-alpha/translate.c     |  4 ++--
 target-arm/translate.c       |  7 +++++--
 tcg/aarch64/tcg-target.inc.c |  7 +++++++
 tcg/arm/tcg-target.inc.c     | 12 ++++++++++++
 tcg/i386/tcg-target.inc.c    | 35 +++++++++++++++++++++++++++++++++++
 tcg/ia64/tcg-target.inc.c    |  5 +++++
 tcg/mips/tcg-target.inc.c    |  6 ++++++
 tcg/ppc/tcg-target.inc.c     |  8 ++++++++
 tcg/s390/tcg-target.inc.c    |  9 +++++++++
 tcg/sparc/tcg-target.inc.c   |  8 ++++++++
 tcg/tcg-op.c                 |  6 ++++++
 tcg/tcg-op.h                 |  2 ++
 tcg/tcg-opc.h                |  2 ++
 tcg/tci/tcg-target.inc.c     |  3 +++
 tci.c                        |  3 +++
 15 files changed, 113 insertions(+), 4 deletions(-)

-- 
2.5.5

[Qemu-devel] [PATCH v2 01/12] Introduce TCGOpcode for fence instruction

[Richard Henderson]

This commit introduces the TCGOpcode for fence instruction.

Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Message-Id: <20160524171856.1000-2-bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.c  | 6 ++++++
 tcg/tcg-op.h  | 2 ++
 tcg/tcg-opc.h | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 54c0277..2a7af95 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -146,6 +146,12 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
     tcg_emit_op(ctx, opc, pi);
 }
 
+void tcg_gen_fence(void)
+{
+    /* ??? Enable only when MTTCG is enabled.  */
+    tcg_gen_op1(&tcg_ctx, INDEX_op_fence, 0);
+}
+
 /* 32 bit ops */
 
 void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index f217e80..2293720 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -261,6 +261,8 @@ static inline void tcg_gen_br(TCGLabel *l)
     tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
 }
 
+void tcg_gen_fence(void);
+
 /* Helper calls. */
 
 /* 32 bit ops */
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 6d0410c..b772d90 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END)
 # define IMPL64  TCG_OPF_64BIT
 #endif
 
+DEF(fence, 0, 0, 0, TCG_OPF_SIDE_EFFECTS)
+
 DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
 DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
 DEF(setcond_i32, 1, 2, 1, 0)
-- 
2.5.5

[Qemu-devel] [PATCH v2 02/12] tcg/i386: Add support for fence

[Richard Henderson]

Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Message-Id: <20160524171856.1000-3-bobby.prani@gmail.com>
[rth: Check for sse2, fallback to locked memory op otherwise.]
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/i386/tcg-target.inc.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 317484c..d3f2d73 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -121,6 +121,16 @@ static bool have_cmov;
 # define have_cmov 0
 #endif
 
+/* For 32-bit, we are going to attempt to determine at runtime whether
+   sse2 support is available.  */
+#if TCG_TARGET_REG_BITS == 64 || defined(__SSE2__)
+# define have_sse2 1
+#elif defined(CONFIG_CPUID_H) && defined(bit_SSE2)
+static bool have_sse2;
+#else
+# define have_sse2 0
+#endif
+
 /* If bit_MOVBE is defined in cpuid.h (added in GCC version 4.6), we are
    going to attempt to determine at runtime whether movbe is available.  */
 #if defined(CONFIG_CPUID_H) && defined(bit_MOVBE)
@@ -686,6 +696,21 @@ static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
     }
 }
 
+static inline void tcg_out_fence(TCGContext *s)
+{
+    if (have_sse2) {
+        /* mfence */
+        tcg_out8(s, 0x0f);
+        tcg_out8(s, 0xae);
+        tcg_out8(s, 0xf0);
+    } else {
+        /* lock orl $0,0(%esp) */
+        tcg_out8(s, 0xf0);
+        tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0);
+        tcg_out8(s, 0);
+    }
+}
+
 static inline void tcg_out_push(TCGContext *s, int reg)
 {
     tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0);
@@ -2120,6 +2145,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         }
         break;
 
+    case INDEX_op_fence:
+        tcg_out_fence(s);
+        break;
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
@@ -2185,6 +2213,8 @@ static const TCGTargetOpDef x86_op_defs[] = {
     { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
     { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
 
+    { INDEX_op_fence, { } },
+
 #if TCG_TARGET_REG_BITS == 32
     { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
     { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
@@ -2362,6 +2392,11 @@ static void tcg_target_init(TCGContext *s)
            available, we'll use a small forward branch.  */
         have_cmov = (d & bit_CMOV) != 0;
 #endif
+#ifndef have_sse2
+        /* Likewise, almost all hardware supports SSE2, but we do
+           have a locked memory operation to use as a substitute.  */
+        have_sse2 = (d & bit_SSE2) != 0;
+#endif
 #ifndef have_movbe
         /* MOVBE is only available on Intel Atom and Haswell CPUs, so we
            need to probe for it.  */
-- 
2.5.5

[Qemu-devel] [PATCH v2 03/12] tcg/aarch64: Add support for fence

[Richard Henderson]

Cc: Claudio Fontana <claudio.fontana@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/aarch64/tcg-target.inc.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 1447f7c..839569d 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -372,6 +372,9 @@ typedef enum {
     I3510_EOR       = 0x4a000000,
     I3510_EON       = 0x4a200000,
     I3510_ANDS      = 0x6a000000,
+
+    /* System instrutions.  */
+    DMB_ISH         = 0xd5033bbf,
 } AArch64Insn;
 
 static inline uint32_t tcg_in32(TCGContext *s)
@@ -1637,6 +1640,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
         break;
 
+    case INDEX_op_fence:
+        tcg_out32(s, DMB_ISH);
+        break;
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
@@ -1761,6 +1767,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
     { INDEX_op_muluh_i64, { "r", "r", "r" } },
     { INDEX_op_mulsh_i64, { "r", "r", "r" } },
 
+    { INDEX_op_fence, { } },
     { -1 },
 };
 
-- 
2.5.5

[Qemu-devel] [PATCH v2 04/12] tcg/arm: Add support for fence

[Richard Henderson]

Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.inc.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index f9f54c6..951d110 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -313,6 +313,10 @@ typedef enum {
     INSN_LDRD_REG  = 0x000000d0,
     INSN_STRD_IMM  = 0x004000f0,
     INSN_STRD_REG  = 0x000000f0,
+
+    INSN_DMB_ISH   = 0x5bf07ff5,
+    INSN_DMB_MCR   = 0xba0f07ee,
+
 } ARMInsn;
 
 #define SHIFT_IMM_LSL(im)	(((im) << 7) | 0x00)
@@ -1923,6 +1927,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
         break;
 
+    case INDEX_op_fence:
+        if (use_armv7_instructions) {
+            tcg_out32(s, INSN_DMB_ISH);
+        } else if (use_armv6_instructions) {
+            tcg_out32(s, INSN_DMB_MCR);
+        }
+        break;
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
@@ -1997,6 +2008,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
 
+    { INDEX_op_fence, { } },
     { -1 },
 };
 
-- 
2.5.5

[Qemu-devel] [PATCH v2 05/12] tcg/ia64: Add support for fence

[Richard Henderson]

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ia64/tcg-target.inc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c
index 395223e..6bbc6dc5 100644
--- a/tcg/ia64/tcg-target.inc.c
+++ b/tcg/ia64/tcg-target.inc.c
@@ -247,6 +247,7 @@ enum {
     OPC_LD4_M3                = 0x0a080000000ull,
     OPC_LD8_M1                = 0x080c0000000ull,
     OPC_LD8_M3                = 0x0a0c0000000ull,
+    OPC_MF_M24                = 0x00110000000ull,
     OPC_MUX1_I3               = 0x0eca0000000ull,
     OPC_NOP_B9                = 0x04008000000ull,
     OPC_NOP_F16               = 0x00008000000ull,
@@ -2213,6 +2214,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_qemu_st(s, args);
         break;
 
+    case INDEX_op_fence:
+        tcg_out_bundle(s, mmI, OPC_MF_M24, INSN_NOP_M, INSN_NOP_I);
+        break;
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
@@ -2326,6 +2330,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
     { INDEX_op_qemu_st_i32, { "SZ", "r" } },
     { INDEX_op_qemu_st_i64, { "SZ", "r" } },
 
+    { INDEX_op_fence, { } },
     { -1 },
 };
 
-- 
2.5.5

[Qemu-devel] [PATCH v2 06/12] tcg/mips: Add support for fence

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/mips/tcg-target.inc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 50e98ea..cad1d4d 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -292,6 +292,7 @@ typedef enum {
     OPC_JALR     = OPC_SPECIAL | 0x09,
     OPC_MOVZ     = OPC_SPECIAL | 0x0A,
     OPC_MOVN     = OPC_SPECIAL | 0x0B,
+    OPC_SYNC     = OPC_SPECIAL | 0x0F,
     OPC_MFHI     = OPC_SPECIAL | 0x10,
     OPC_MFLO     = OPC_SPECIAL | 0x12,
     OPC_MULT     = OPC_SPECIAL | 0x18,
@@ -1636,6 +1637,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
                         const_args[4], const_args[5], true);
         break;
 
+    case INDEX_op_fence:
+        tcg_out32(s, OPC_SYNC);
+        break;
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
@@ -1716,6 +1720,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
     { INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } },
     { INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } },
 #endif
+
+    { INDEX_op_fence, { } },
     { -1 },
 };
 
-- 
2.5.5

[Qemu-devel] [PATCH v2 07/12] tcg/ppc: Add support for fence

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc/tcg-target.inc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index da10052..ea576f9 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -469,6 +469,9 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
 #define STHX   XO31(407)
 #define STWX   XO31(151)
 
+#define HWSYNC XO31(598)
+#define LWSYNC (HWSYNC | (1u << 21))
+
 #define SPR(a, b) ((((a)<<5)|(b))<<11)
 #define LR     SPR(8, 0)
 #define CTR    SPR(9, 0)
@@ -2439,6 +2442,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
         tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
         break;
 
+    case INDEX_op_fence:
+        /* ??? Do we want SEQ_CST or ACQ_REL memory model.  */
+        tcg_out32(s, HWSYNC);
+        break;
     case INDEX_op_mov_i32:   /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32:  /* Always emitted via tcg_out_movi.  */
@@ -2586,6 +2593,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
 #endif
 
+    { INDEX_op_fence, { } },
     { -1 },
 };
 
-- 
2.5.5

[Qemu-devel] [PATCH v2 08/12] tcg/s390: Add support for fence

[Richard Henderson]

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/s390/tcg-target.inc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index e0a60e6..4c63621 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -343,6 +343,7 @@ static tcg_insn_unit *tb_ret_addr;
 #define FACILITY_EXT_IMM	(1ULL << (63 - 21))
 #define FACILITY_GEN_INST_EXT	(1ULL << (63 - 34))
 #define FACILITY_LOAD_ON_COND   (1ULL << (63 - 45))
+#define FACILITY_FAST_BCR_SER   FACILITY_LOAD_ON_COND
 
 static uint64_t facilities;
 
@@ -2165,6 +2166,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tgen_deposit(s, args[0], args[2], args[3], args[4]);
         break;
 
+    case INDEX_op_fence:
+        /* The host memory model is quite strong, we simply need to
+           serialize the instruction stream.  */
+        tcg_out_insn(s, RR, BCR,
+		     facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
@@ -2286,6 +2294,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
     { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
     { INDEX_op_deposit_i64, { "r", "0", "r" } },
 
+    { INDEX_op_fence, { } },
     { -1 },
 };
 
-- 
2.5.5

[Qemu-devel] [PATCH v2 09/12] tcg/sparc: Add support for fence

[Richard Henderson]

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.inc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 9938a50..16d8d8f 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -249,6 +249,8 @@ static const int tcg_target_call_oarg_regs[] = {
 #define STWA       (INSN_OP(3) | INSN_OP3(0x14))
 #define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
 
+#define MEMBAR     (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
+
 #ifndef ASI_PRIMARY_LITTLE
 #define ASI_PRIMARY_LITTLE 0x88
 #endif
@@ -1450,6 +1452,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 	tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
 	break;
 
+    case INDEX_op_fence:
+        /* membar #LoadLoad|#LoadStore|#StoreStore|#StoreLoad */
+        tcg_out32(s, MEMBAR | 15);
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
@@ -1551,6 +1558,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_qemu_st_i32, { "sZ", "A" } },
     { INDEX_op_qemu_st_i64, { "SZ", "A" } },
 
+    { INDEX_op_fence, { } },
     { -1 },
 };
 
-- 
2.5.5

[Qemu-devel] [PATCH v2 10/12] tcg/tci: Add support for fence

[Richard Henderson]

Cc: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tci/tcg-target.inc.c | 3 +++
 tci.c                    | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
index fa74d52..bf65416 100644
--- a/tcg/tci/tcg-target.inc.c
+++ b/tcg/tci/tcg-target.inc.c
@@ -255,6 +255,7 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
     { INDEX_op_bswap32_i32, { R, R } },
 #endif
 
+    { INDEX_op_fence, { } },
     { -1 },
 };
 
@@ -800,6 +801,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
         }
         tcg_out_i(s, *args++);
         break;
+    case INDEX_op_fence:
+        break;
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
diff --git a/tci.c b/tci.c
index b488c0d..53b3f71 100644
--- a/tci.c
+++ b/tci.c
@@ -1236,6 +1236,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
                 tcg_abort();
             }
             break;
+        case INDEX_op_fence:
+            smp_mb();
+            break;
         default:
             TODO();
             break;
-- 
2.5.5

[Qemu-devel] [PATCH v2 11/12] target-arm: Add frontend support for fence gen in ARMv7

[Richard Henderson]

Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Message-Id: <20160524171856.1000-4-bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/translate.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index e525f1e..0f71800 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8052,9 +8052,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                 gen_clrex(s);
                 return;
             case 4: /* dsb */
+                ARCH(7);
+                return;
             case 5: /* dmb */
                 ARCH(7);
-                /* We don't emulate caches so these are a no-op.  */
+                tcg_gen_fence();
                 return;
             case 6: /* isb */
                 /* We need to break the TB after this insn to execute
@@ -10402,8 +10404,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                             gen_clrex(s);
                             break;
                         case 4: /* dsb */
+                            break;
                         case 5: /* dmb */
-                            /* These execute as NOPs.  */
+                            tcg_gen_fence();
                             break;
                         case 6: /* isb */
                             /* We need to break the TB after this insn
-- 
2.5.5

[Qemu-devel] [PATCH v2 12/12] target-alpha: Generate fence opcodes

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 76dab15..2dbcb82 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2334,11 +2334,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             break;
         case 0x4000:
             /* MB */
-            /* No-op */
+            tcg_gen_fence();
             break;
         case 0x4400:
             /* WMB */
-            /* No-op */
+            tcg_gen_fence();
             break;
         case 0x8000:
             /* FETCH */
-- 
2.5.5

Re: [Qemu-devel] [PATCH v2 00/12] tcg: Add fence opcode

[Pranith Kumar]

On Thu, May 26, 2016 at 9:00 PM, Richard Henderson <rth@twiddle.net> wrote:
> This is a reorg of Pranith's first patch set, correcting a few
> mistakes and adding backend support for all of the other hosts.
>
> In addition, I added front-end support for Alpha, since I didn't
> actually have any armv7 images handy to test the backends.
>

Thanks Richard for fixing this up for other archs. You saved me a ton of work :)

I'll rebase my work on top of this patch series.

Regards,
-- 
Pranith

Re: [Qemu-devel] [PATCH v2 03/12] tcg/aarch64: Add support for fence

[Claudio Fontana]

Hi Richard,


On Friday, 27 May 2016, Richard Henderson <rth@twiddle.net> wrote:

> Cc: Claudio Fontana <claudio.fontana@gmail.com <javascript:;>>
> Signed-off-by: Richard Henderson <rth@twiddle.net <javascript:;>>
> ---
>  tcg/aarch64/tcg-target.inc.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
> index 1447f7c..839569d 100644
> --- a/tcg/aarch64/tcg-target.inc.c
> +++ b/tcg/aarch64/tcg-target.inc.c
> @@ -372,6 +372,9 @@ typedef enum {
>      I3510_EOR       = 0x4a000000,
>      I3510_EON       = 0x4a200000,
>      I3510_ANDS      = 0x6a000000,
> +
> +    /* System instrutions.  */


typo here, "instructions"

Ciao, C.


> +    DMB_ISH         = 0xd5033bbf,
>  } AArch64Insn;
>
>  static inline uint32_t tcg_in32(TCGContext *s)
> @@ -1637,6 +1640,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
>          tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
>          break;
>
> +    case INDEX_op_fence:
> +        tcg_out32(s, DMB_ISH);
> +        break;
>      case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
>      case INDEX_op_mov_i64:
>      case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
> @@ -1761,6 +1767,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
>      { INDEX_op_muluh_i64, { "r", "r", "r" } },
>      { INDEX_op_mulsh_i64, { "r", "r", "r" } },
>
> +    { INDEX_op_fence, { } },
>      { -1 },
>  };
>
> --
> 2.5.5
>
>

--

Re: [Qemu-devel] [PATCH v2 01/12] Introduce TCGOpcode for fence instruction

[Sergey Fedorov]

On 27/05/16 04:00, Richard Henderson wrote:
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 6d0410c..b772d90 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END)
>  # define IMPL64  TCG_OPF_64BIT
>  #endif
>  
> +DEF(fence, 0, 0, 0, TCG_OPF_SIDE_EFFECTS)
> +

I still think this TCG op needs to have a constant argument of a barrier
type. So that we can distinguish between full, read and write memory
barriers.

Regards,
Sergey

>  DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
>  DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
>  DEF(setcond_i32, 1, 2, 1, 0)

Re: [Qemu-devel] [PATCH v2 10/12] tcg/tci: Add support for fence

[Sergey Fedorov]

On 27/05/16 04:00, Richard Henderson wrote:
> diff --git a/tci.c b/tci.c
> index b488c0d..53b3f71 100644
> --- a/tci.c
> +++ b/tci.c
> @@ -1236,6 +1236,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
>                  tcg_abort();
>              }
>              break;
> +        case INDEX_op_fence:
> +            smp_mb();
> +            break;
>          default:
>              TODO();
>              break;

A bit of bike-shedding. While there's no common ISA term for "memory
barrier" (also known as a "membar", "memory fence", etc.), we already
refer to it as a "memory barrier" (or "mb") in include/qemu/atomic.h and
docs/atomics.txt. Why don't be consistent and avoid introducing yet
another term for the same thing?

Kind regards,
Sergey

Re: [Qemu-devel] [PATCH v2 01/12] Introduce TCGOpcode for fence instruction

[Lluís Vilanova]

Richard Henderson writes:

> This commit introduces the TCGOpcode for fence instruction.
[...]

I think this patch sould also document the opcpde in "tcg/README".


Cheers,
  Lluis

Re: [Qemu-devel] [PATCH v2 01/12] Introduce TCGOpcode for fence instruction

[Peter Maydell]

On 27 May 2016 at 11:56, Lluís Vilanova <vilanova@ac.upc.edu> wrote:
> Richard Henderson writes:
>
>> This commit introduces the TCGOpcode for fence instruction.
> [...]
>
> I think this patch sould also document the opcpde in "tcg/README".

Yes, please. I have no idea what this thing is for, and neither
this patch nor the readme give me any clue...

thanks
-- PMM

Re: [Qemu-devel] [PATCH v2 01/12] Introduce TCGOpcode for fence instruction

[Pranith Kumar]

Sergey Fedorov writes:

> On 27/05/16 04:00, Richard Henderson wrote:
>> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
>> index 6d0410c..b772d90 100644
>> --- a/tcg/tcg-opc.h
>> +++ b/tcg/tcg-opc.h
>> @@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END)
>>  # define IMPL64  TCG_OPF_64BIT
>>  #endif
>>  
>> +DEF(fence, 0, 0, 0, TCG_OPF_SIDE_EFFECTS)
>> +
>
> I still think this TCG op needs to have a constant argument of a barrier
> type. So that we can distinguish between full, read and write memory
> barriers.
>

Yes, I have a version with this fixed. I will post my patches(v3) with this
changed.

Thanks,
-- 
Pranith

Re: [Qemu-devel] [PATCH v2 10/12] tcg/tci: Add support for fence

[Pranith Kumar]

Hi Sergey,

Sergey Fedorov writes:

> On 27/05/16 04:00, Richard Henderson wrote:
>> diff --git a/tci.c b/tci.c
>> index b488c0d..53b3f71 100644
>> --- a/tci.c
>> +++ b/tci.c
>> @@ -1236,6 +1236,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
>>                  tcg_abort();
>>              }
>>              break;
>> +        case INDEX_op_fence:
>> +            smp_mb();
>> +            break;
>>          default:
>>              TODO();
>>              break;
>
> A bit of bike-shedding. While there's no common ISA term for "memory
> barrier" (also known as a "membar", "memory fence", etc.), we already
> refer to it as a "memory barrier" (or "mb") in include/qemu/atomic.h and
> docs/atomics.txt. Why don't be consistent and avoid introducing yet
> another term for the same thing?
>

Fair point. Do you think tcg_out_mb() is better then?

Thanks,
-- 
Pranith

Re: [Qemu-devel] [PATCH v2 10/12] tcg/tci: Add support for fence

[Sergey Fedorov]

On 27/05/16 17:17, Pranith Kumar wrote:
> Hi Sergey,
>
> Sergey Fedorov writes:
>
>> On 27/05/16 04:00, Richard Henderson wrote:
>>> diff --git a/tci.c b/tci.c
>>> index b488c0d..53b3f71 100644
>>> --- a/tci.c
>>> +++ b/tci.c
>>> @@ -1236,6 +1236,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
>>>                  tcg_abort();
>>>              }
>>>              break;
>>> +        case INDEX_op_fence:
>>> +            smp_mb();
>>> +            break;
>>>          default:
>>>              TODO();
>>>              break;
>> A bit of bike-shedding. While there's no common ISA term for "memory
>> barrier" (also known as a "membar", "memory fence", etc.), we already
>> refer to it as a "memory barrier" (or "mb") in include/qemu/atomic.h and
>> docs/atomics.txt. Why don't be consistent and avoid introducing yet
>> another term for the same thing?
>>
> Fair point. Do you think tcg_out_mb() is better then?

Yes, if used together with 'INDEX_op_mb', of course.

Kind regards,
Sergey

Re: [Qemu-devel] [PATCH v2 10/12] tcg/tci: Add support for fence

[Pranith Kumar]

On Fri, May 27, 2016 at 10:20 AM, Sergey Fedorov <serge.fdrv@gmail.com> wrote:
>>>> +        case INDEX_op_fence:
>>>> +            smp_mb();
>>>> +            break;
>>>>          default:
>>>>              TODO();
>>>>              break;
>>> A bit of bike-shedding. While there's no common ISA term for "memory
>>> barrier" (also known as a "membar", "memory fence", etc.), we already
>>> refer to it as a "memory barrier" (or "mb") in include/qemu/atomic.h and
>>> docs/atomics.txt. Why don't be consistent and avoid introducing yet
>>> another term for the same thing?
>>>
>> Fair point. Do you think tcg_out_mb() is better then?
>
> Yes, if used together with 'INDEX_op_mb', of course.
>

OK. I'll make the change. Thanks for the feedback!

-- 
Pranith

Re: [Qemu-devel] [PATCH v2 06/12] tcg/mips: Add support for fence

[Aurelien Jarno]

On 2016-05-26 18:00, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/mips/tcg-target.inc.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
> index 50e98ea..cad1d4d 100644
> --- a/tcg/mips/tcg-target.inc.c
> +++ b/tcg/mips/tcg-target.inc.c
> @@ -292,6 +292,7 @@ typedef enum {
>      OPC_JALR     = OPC_SPECIAL | 0x09,
>      OPC_MOVZ     = OPC_SPECIAL | 0x0A,
>      OPC_MOVN     = OPC_SPECIAL | 0x0B,
> +    OPC_SYNC     = OPC_SPECIAL | 0x0F,
>      OPC_MFHI     = OPC_SPECIAL | 0x10,
>      OPC_MFLO     = OPC_SPECIAL | 0x12,
>      OPC_MULT     = OPC_SPECIAL | 0x18,
> @@ -1636,6 +1637,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>                          const_args[4], const_args[5], true);
>          break;
>  
> +    case INDEX_op_fence:
> +        tcg_out32(s, OPC_SYNC);
> +        break;
>      case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
>      case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
>      case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
> @@ -1716,6 +1720,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
>      { INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } },
>      { INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } },
>  #endif
> +
> +    { INDEX_op_fence, { } },
>      { -1 },
>  };

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

Also compiled tested, but we don't really have a way to test that so
far.


-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net