All of lore.kernel.org
 help / color / mirror / Atom feed
From: k.kozlowski@samsung.com (Krzysztof Kozlowski)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger
Date: Tue, 07 Jun 2016 09:08:14 +0200	[thread overview]
Message-ID: <575672DE.4060504@samsung.com> (raw)
In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com>

On 06/06/2016 07:56 PM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
> 
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
> 
> The respective maintainers are of course welcome to prove me wrong.
> 
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi    | 8 ++++----
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi          | 8 ++++----
>  arch/arm64/boot/dts/apm/apm-storm.dtsi               | 8 ++++----
>  arch/arm64/boot/dts/broadcom/ns2.dtsi                | 8 ++++----
>  arch/arm64/boot/dts/cavium/thunder-88xx.dtsi         | 8 ++++----
>  arch/arm64/boot/dts/exynos/exynos7.dtsi              | 8 ++++----
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi       | 8 ++++----
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 8 ++++----
>  arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
>  arch/arm64/boot/dts/xilinx/zynqmp.dtsi               | 8 ++++----
>  10 files changed, 40 insertions(+), 40 deletions(-)
> 

(...)

> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index ca663df..1628315 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -473,10 +473,10 @@
>  
>  		timer {
>  			compatible = "arm,armv8-timer";
> -			interrupts = <1 13 0xff01>,
> -				     <1 14 0xff01>,
> -				     <1 11 0xff01>,
> -				     <1 10 0xff01>;
> +			interrupts = <1 13 0xff08>,
> +				     <1 14 0xff08>,
> +				     <1 11 0xff08>,
> +				     <1 10 0xff08>;
>  		};
>  
>  		pmu_system_controller: system-controller at 105c0000 {

Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

I got a conflicting patch in my tree so it would be nice if your fix
went to current release cycle:
https://git.kernel.org/cgit/linux/kernel/git/krzk/linux.git/commit/?h=next/dt64&id=8b77005c40376816885b100bcd358887d29e323f

Best regards,
Krzysztof

WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <k.kozlowski@samsung.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Cc: "Dinh Nguyen" <dinguyen@opensource.altera.com>,
	"Carlo Caione" <carlo@caione.org>,
	"Kevin Hilman" <khilman@baylibre.com>,
	"Duc Dang" <dhdang@apm.com>,
	"Florian Fainelli" <f.fainelli@gmail.com>,
	"Ray Jui" <rjui@broadcom.com>,
	"Scott Branden" <sbranden@broadcom.com>,
	"Kukjin Kim" <kgene@kernel.org>,
	"Jason Cooper" <jason@lakedaemon.net>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Gregory Clement" <gregory.clement@free-electrons.com>,
	"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
	"Masahiro Yamada" <yamada.masahiro@socionext.com>,
	"Michal Simek" <michal.simek@xilinx.com>,
	"Sören Brinkmann" <soren.brinkmann@xilinx.com>,
	"Tirumalesh Chalamarla" <tchalamarla@cavium.com>,
	"Jan Glauber" <jglauber@cavium.com>,
	"Hou Zhiqiang" <B48286@freescale.com>,
	"Wenbin Song" <Wenbin.Song@freescale.com>,
	"Yuan Yao" <yao.yuan@nxp.com>, "Liu Gang" <Gang.Liu@nxp.com>,
	"Mingkai Hu" <Mingkai.Hu@freescale.com>
Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger
Date: Tue, 07 Jun 2016 09:08:14 +0200	[thread overview]
Message-ID: <575672DE.4060504@samsung.com> (raw)
In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com>

On 06/06/2016 07:56 PM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
> 
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
> 
> The respective maintainers are of course welcome to prove me wrong.
> 
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi    | 8 ++++----
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi          | 8 ++++----
>  arch/arm64/boot/dts/apm/apm-storm.dtsi               | 8 ++++----
>  arch/arm64/boot/dts/broadcom/ns2.dtsi                | 8 ++++----
>  arch/arm64/boot/dts/cavium/thunder-88xx.dtsi         | 8 ++++----
>  arch/arm64/boot/dts/exynos/exynos7.dtsi              | 8 ++++----
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi       | 8 ++++----
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 8 ++++----
>  arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
>  arch/arm64/boot/dts/xilinx/zynqmp.dtsi               | 8 ++++----
>  10 files changed, 40 insertions(+), 40 deletions(-)
> 

(...)

> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index ca663df..1628315 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -473,10 +473,10 @@
>  
>  		timer {
>  			compatible = "arm,armv8-timer";
> -			interrupts = <1 13 0xff01>,
> -				     <1 14 0xff01>,
> -				     <1 11 0xff01>,
> -				     <1 10 0xff01>;
> +			interrupts = <1 13 0xff08>,
> +				     <1 14 0xff08>,
> +				     <1 11 0xff08>,
> +				     <1 10 0xff08>;
>  		};
>  
>  		pmu_system_controller: system-controller@105c0000 {

Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

I got a conflicting patch in my tree so it would be nice if your fix
went to current release cycle:
https://git.kernel.org/cgit/linux/kernel/git/krzk/linux.git/commit/?h=next/dt64&id=8b77005c40376816885b100bcd358887d29e323f

Best regards,
Krzysztof

WARNING: multiple messages have this Message-ID (diff)
From: k.kozlowski@samsung.com (Krzysztof Kozlowski)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger
Date: Tue, 07 Jun 2016 09:08:14 +0200	[thread overview]
Message-ID: <575672DE.4060504@samsung.com> (raw)
In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com>

On 06/06/2016 07:56 PM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
> 
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
> 
> The respective maintainers are of course welcome to prove me wrong.
> 
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi    | 8 ++++----
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi          | 8 ++++----
>  arch/arm64/boot/dts/apm/apm-storm.dtsi               | 8 ++++----
>  arch/arm64/boot/dts/broadcom/ns2.dtsi                | 8 ++++----
>  arch/arm64/boot/dts/cavium/thunder-88xx.dtsi         | 8 ++++----
>  arch/arm64/boot/dts/exynos/exynos7.dtsi              | 8 ++++----
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi       | 8 ++++----
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 8 ++++----
>  arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
>  arch/arm64/boot/dts/xilinx/zynqmp.dtsi               | 8 ++++----
>  10 files changed, 40 insertions(+), 40 deletions(-)
> 

(...)

> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index ca663df..1628315 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -473,10 +473,10 @@
>  
>  		timer {
>  			compatible = "arm,armv8-timer";
> -			interrupts = <1 13 0xff01>,
> -				     <1 14 0xff01>,
> -				     <1 11 0xff01>,
> -				     <1 10 0xff01>;
> +			interrupts = <1 13 0xff08>,
> +				     <1 14 0xff08>,
> +				     <1 11 0xff08>,
> +				     <1 10 0xff08>;
>  		};
>  
>  		pmu_system_controller: system-controller at 105c0000 {

Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

I got a conflicting patch in my tree so it would be nice if your fix
went to current release cycle:
https://git.kernel.org/cgit/linux/kernel/git/krzk/linux.git/commit/?h=next/dt64&id=8b77005c40376816885b100bcd358887d29e323f

Best regards,
Krzysztof

WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <k.kozlowski@samsung.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Cc: "Dinh Nguyen" <dinguyen@opensource.altera.com>,
	"Carlo Caione" <carlo@caione.org>,
	"Kevin Hilman" <khilman@baylibre.com>,
	"Duc Dang" <dhdang@apm.com>,
	"Florian Fainelli" <f.fainelli@gmail.com>,
	"Ray Jui" <rjui@broadcom.com>,
	"Scott Branden" <sbranden@broadcom.com>,
	"Kukjin Kim" <kgene@kernel.org>,
	"Jason Cooper" <jason@lakedaemon.net>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Gregory Clement" <gregory.clement@free-electrons.com>,
	"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
	"Masahiro Yamada" <yamada.masahiro@socionext.com>,
	"Michal Simek" <michal.simek@xilinx.com>,
	"Sören Brinkmann" <soren.brinkmann@xilinx.com>,
	"Tirumalesh Chalamarla" <tchalamarla@cavium.com>,
	"Jan Glauber" <jglauber@cavium.com>,
	"Hou Zhiqiang" <B48286@freescale.com>,
	"Wenbin Song" <Wenbin.Song@freescale.com>,
	"Yuan Yao" <yao.yuan@nxp.com>, "Liu Gang" <Gang.Liu@nxp.com>,
	"Mingkai Hu" <Mingkai.Hu@freescale.com>,
	"Rajesh Bhagat" <rajesh.bhagat@freescale.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
	bcm-kernel-feedback-list@broadcom.com,
	linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger
Date: Tue, 07 Jun 2016 09:08:14 +0200	[thread overview]
Message-ID: <575672DE.4060504@samsung.com> (raw)
In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com>

On 06/06/2016 07:56 PM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
> 
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
> 
> The respective maintainers are of course welcome to prove me wrong.
> 
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi    | 8 ++++----
>  arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi          | 8 ++++----
>  arch/arm64/boot/dts/apm/apm-storm.dtsi               | 8 ++++----
>  arch/arm64/boot/dts/broadcom/ns2.dtsi                | 8 ++++----
>  arch/arm64/boot/dts/cavium/thunder-88xx.dtsi         | 8 ++++----
>  arch/arm64/boot/dts/exynos/exynos7.dtsi              | 8 ++++----
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi       | 8 ++++----
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 8 ++++----
>  arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
>  arch/arm64/boot/dts/xilinx/zynqmp.dtsi               | 8 ++++----
>  10 files changed, 40 insertions(+), 40 deletions(-)
> 

(...)

> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index ca663df..1628315 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -473,10 +473,10 @@
>  
>  		timer {
>  			compatible = "arm,armv8-timer";
> -			interrupts = <1 13 0xff01>,
> -				     <1 14 0xff01>,
> -				     <1 11 0xff01>,
> -				     <1 10 0xff01>;
> +			interrupts = <1 13 0xff08>,
> +				     <1 14 0xff08>,
> +				     <1 11 0xff08>,
> +				     <1 10 0xff08>;
>  		};
>  
>  		pmu_system_controller: system-controller@105c0000 {

Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

I got a conflicting patch in my tree so it would be nice if your fix
went to current release cycle:
https://git.kernel.org/cgit/linux/kernel/git/krzk/linux.git/commit/?h=next/dt64&id=8b77005c40376816885b100bcd358887d29e323f

Best regards,
Krzysztof

  reply	other threads:[~2016-06-07  7:08 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-06 17:56 [PATCH v3 0/2] arm/arm64: Fix architected timer interrupt trigger Marc Zyngier
2016-06-06 17:56 ` Marc Zyngier
2016-06-06 17:56 ` Marc Zyngier
2016-06-06 17:56 ` Marc Zyngier
2016-06-06 17:56 ` [PATCH v3 1/2] clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-09 21:10   ` David Daney
2016-06-09 21:10     ` David Daney
2016-06-09 21:10     ` David Daney
2016-06-09 21:10     ` David Daney
2016-06-10  7:29     ` Marc Zyngier
2016-06-10  7:29       ` Marc Zyngier
2016-06-10  7:29       ` Marc Zyngier
2016-06-10  7:29       ` Marc Zyngier
2016-06-10 17:39       ` David Daney
2016-06-10 17:39         ` David Daney
2016-06-10 17:39         ` David Daney
2016-06-10 17:39         ` David Daney
2016-06-11  9:41         ` Marc Zyngier
2016-06-11  9:41           ` Marc Zyngier
2016-06-11  9:41           ` Marc Zyngier
2016-06-11  9:41           ` Marc Zyngier
     [not found]           ` <CANe6Qb_sx8_rRHZG1PR=A+cgxqYTzreZ0rD01X-gtEDb=h1cVQ@mail.gmail.com>
2016-06-12 10:12             ` Marc Zyngier
2016-06-12 10:12               ` Marc Zyngier
2016-06-12 10:12               ` Marc Zyngier
2016-06-12 10:12               ` Marc Zyngier
2016-06-10 21:51       ` Duc Dang
2016-07-05  4:37         ` Duc Dang
2016-07-05  4:37         ` Duc Dang
2016-06-10 21:51         ` Duc Dang
2016-06-06 17:56 ` [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-07  7:08   ` Krzysztof Kozlowski [this message]
2016-06-07  7:08     ` Krzysztof Kozlowski
2016-06-07  7:08     ` Krzysztof Kozlowski
2016-06-07  7:08     ` Krzysztof Kozlowski
2016-06-07  7:19   ` Michal Simek
2016-06-07  7:19     ` Michal Simek
2016-06-07  7:19     ` Michal Simek
2016-06-07  7:19     ` Michal Simek
2016-06-09 15:05   ` Dinh Nguyen
2016-06-09 15:05     ` Dinh Nguyen
2016-06-09 15:05     ` Dinh Nguyen
2016-06-09 15:05     ` Dinh Nguyen
2016-06-09 15:23   ` Carlo Caione
2016-06-09 15:23     ` Carlo Caione
2016-06-09 15:23     ` Carlo Caione
2016-06-09 15:23     ` Carlo Caione
2016-06-09 18:11   ` David Daney
2016-06-09 18:11     ` David Daney
2016-06-09 18:11     ` David Daney
2016-06-09 18:11     ` David Daney
2016-06-09 21:06     ` David Daney
2016-06-09 21:06       ` David Daney
2016-06-09 21:06       ` David Daney
2016-06-09 21:06       ` David Daney
2016-06-10  7:23       ` Marc Zyngier
2016-06-10  7:23         ` Marc Zyngier
2016-06-10  7:23         ` Marc Zyngier
2016-06-10  7:23         ` Marc Zyngier
2016-06-10 16:50         ` David Daney
2016-06-10 16:50           ` David Daney
2016-06-10 16:50           ` David Daney
2016-06-10 16:50           ` David Daney
2016-06-10 16:56           ` Marc Zyngier
2016-06-10 16:56             ` Marc Zyngier
2016-06-10 16:56             ` Marc Zyngier
2016-06-10 16:56             ` Marc Zyngier
2016-06-10 17:32             ` David Daney
2016-06-10 17:32               ` David Daney
2016-06-10 17:32               ` David Daney
2016-06-10 17:32               ` David Daney
2016-06-11 10:04               ` Marc Zyngier
2016-06-11 10:04                 ` Marc Zyngier
2016-06-11 10:04                 ` Marc Zyngier
2016-06-11 10:04                 ` Marc Zyngier
2016-06-10 21:48   ` Duc Dang
2016-07-05  4:37     ` Duc Dang
2016-07-05  4:37     ` Duc Dang
2016-06-10 21:48     ` Duc Dang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=575672DE.4060504@samsung.com \
    --to=k.kozlowski@samsung.com \
    --cc=linus-amlogic@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.