* [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate @ 2016-06-09 14:49 tim.gore 2016-06-09 15:15 ` ✗ Ro.CI.BAT: warning for drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate (rev2) Patchwork 2016-06-10 6:30 ` [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate Arun Siluvery 0 siblings, 2 replies; 6+ messages in thread From: tim.gore @ 2016-06-09 14:49 UTC (permalink / raw) To: intel-gfx From: Tim Gore <tim.gore@intel.com> This patch enables a workaround for a mid thread preemption issue where a hardware timing problem can prevent the context restore from happening, leading to a hang. v2: move to gen9_init_workarounds (Arun) Signed-off-by: Tim Gore <tim.gore@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 81d1896..2a6fc62 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1810,6 +1810,10 @@ enum skl_disp_power_wells { #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) +/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ +#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) +#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) + /* WaClearTdlStateAckDirtyBits */ #define GEN8_STATE_ACK _MMIO(0x20F0) #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index cf8d0bf..7c756ac 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1022,6 +1022,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) if (ret) return ret; + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ + I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); + return 0; } -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Ro.CI.BAT: warning for drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate (rev2) 2016-06-09 14:49 [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate tim.gore @ 2016-06-09 15:15 ` Patchwork 2016-06-10 6:30 ` [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate Arun Siluvery 1 sibling, 0 replies; 6+ messages in thread From: Patchwork @ 2016-06-09 15:15 UTC (permalink / raw) To: tim.gore; +Cc: intel-gfx == Series Details == Series: drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate (rev2) URL : https://patchwork.freedesktop.org/series/8487/ State : warning == Summary == Series 8487v2 drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate http://patchwork.freedesktop.org/api/1.0/series/8487/revisions/2/mbox Test gem_exec_flush: Subgroup basic-batch-kernel-default-cmd: fail -> PASS (ro-byt-n2820) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: pass -> DMESG-WARN (fi-snb-i7-2600) Subgroup suspend-read-crc-pipe-c: skip -> DMESG-WARN (ro-bdw-i5-5250u) fi-bdw-i7-5557u total:213 pass:201 dwarn:0 dfail:0 fail:0 skip:12 fi-skl-i5-6260u total:213 pass:202 dwarn:0 dfail:0 fail:0 skip:11 fi-skl-i7-6700k total:213 pass:188 dwarn:0 dfail:0 fail:0 skip:25 fi-snb-i7-2600 total:213 pass:173 dwarn:1 dfail:0 fail:0 skip:39 ro-bdw-i5-5250u total:213 pass:197 dwarn:4 dfail:0 fail:0 skip:12 ro-bdw-i7-5600u total:213 pass:185 dwarn:0 dfail:0 fail:0 skip:28 ro-bsw-n3050 total:213 pass:172 dwarn:0 dfail:0 fail:2 skip:39 ro-byt-n2820 total:213 pass:174 dwarn:0 dfail:0 fail:2 skip:37 ro-hsw-i7-4770r total:213 pass:190 dwarn:0 dfail:0 fail:0 skip:23 ro-ilk1-i5-650 total:208 pass:150 dwarn:0 dfail:0 fail:1 skip:57 ro-ivb-i7-3770 total:213 pass:181 dwarn:0 dfail:0 fail:0 skip:32 ro-ivb2-i7-3770 total:213 pass:185 dwarn:0 dfail:0 fail:0 skip:28 ro-snb-i7-2620M total:213 pass:174 dwarn:0 dfail:0 fail:1 skip:38 fi-hsw-i7-4770k failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1149/ 487a126 drm-intel-nightly: 2016y-06m-09d-10h-05m-55s UTC integration manifest 6755d5e drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate 2016-06-09 14:49 [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate tim.gore 2016-06-09 15:15 ` ✗ Ro.CI.BAT: warning for drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate (rev2) Patchwork @ 2016-06-10 6:30 ` Arun Siluvery 2016-06-10 6:46 ` Gore, Tim 1 sibling, 1 reply; 6+ messages in thread From: Arun Siluvery @ 2016-06-10 6:30 UTC (permalink / raw) To: tim.gore, intel-gfx On 09/06/2016 20:19, tim.gore@intel.com wrote: > From: Tim Gore <tim.gore@intel.com> > > This patch enables a workaround for a mid thread preemption > issue where a hardware timing problem can prevent the > context restore from happening, leading to a hang. > > v2: move to gen9_init_workarounds (Arun) > > Signed-off-by: Tim Gore <tim.gore@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 81d1896..2a6fc62 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1810,6 +1810,10 @@ enum skl_disp_power_wells { > #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) > #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) > > +/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ > +#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) > +#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) > + > /* WaClearTdlStateAckDirtyBits */ > #define GEN8_STATE_ACK _MMIO(0x20F0) > #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index cf8d0bf..7c756ac 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1022,6 +1022,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > if (ret) > return ret; > > + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ > + I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); > + WA_SET_BIT_MASKED(GEN9_CSFE_CHICKEN1_RCS, GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); Please correct the spelling. We should try to keep WA regs in some order although it is not true for some of the existing ones but we should try to follow this rule for the new ones; HW whitelist registers are normally kept at the end. I think the correct place for this one is at the beginning of this function to maintain increasing order. regards Arun > return 0; > } > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate 2016-06-10 6:30 ` [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate Arun Siluvery @ 2016-06-10 6:46 ` Gore, Tim 2016-06-10 8:38 ` Arun Siluvery 0 siblings, 1 reply; 6+ messages in thread From: Gore, Tim @ 2016-06-10 6:46 UTC (permalink / raw) To: Arun Siluvery, intel-gfx@lists.freedesktop.org Tim Gore Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ > -----Original Message----- > From: Arun Siluvery [mailto:arun.siluvery@linux.intel.com] > Sent: Friday, June 10, 2016 7:30 AM > To: Gore, Tim; intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH v2] drm/i915/gen9: implement > WaConextSwitchWithConcurrentTLBInvalidate > > On 09/06/2016 20:19, tim.gore@intel.com wrote: > > From: Tim Gore <tim.gore@intel.com> > > > > This patch enables a workaround for a mid thread preemption issue > > where a hardware timing problem can prevent the context restore from > > happening, leading to a hang. > > > > v2: move to gen9_init_workarounds (Arun) > > > > Signed-off-by: Tim Gore <tim.gore@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ > > 2 files changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 81d1896..2a6fc62 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1810,6 +1810,10 @@ enum skl_disp_power_wells { > > #define GEN9_IZ_HASHING_MASK(slice) (0x3 << > ((slice) * 2)) > > #define GEN9_IZ_HASHING(slice, val) ((val) << > ((slice) * 2)) > > > > +/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ > > +#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) > > +#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) > > + > > /* WaClearTdlStateAckDirtyBits */ > > #define GEN8_STATE_ACK _MMIO(0x20F0) > > #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > > b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index cf8d0bf..7c756ac 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -1022,6 +1022,9 @@ static int gen9_init_workarounds(struct > intel_engine_cs *engine) > > if (ret) > > return ret; > > > > + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ > > + I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, > > > +_MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE) > ); > > + > WA_SET_BIT_MASKED(GEN9_CSFE_CHICKEN1_RCS, > GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); > > Please correct the spelling. > We should try to keep WA regs in some order although it is not true for some > of the existing ones but we should try to follow this rule for the new ones; > HW whitelist registers are normally kept at the end. > I think the correct place for this one is at the beginning of this function to > maintain increasing order. > > regards > Arun > > Which spelling do you want corrected? Tim > > return 0; > > } > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate 2016-06-10 6:46 ` Gore, Tim @ 2016-06-10 8:38 ` Arun Siluvery 2016-06-10 8:51 ` Gore, Tim 0 siblings, 1 reply; 6+ messages in thread From: Arun Siluvery @ 2016-06-10 8:38 UTC (permalink / raw) To: Gore, Tim, intel-gfx@lists.freedesktop.org On 10/06/2016 12:16, Gore, Tim wrote: > > > Tim Gore > Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ > > >> -----Original Message----- >> From: Arun Siluvery [mailto:arun.siluvery@linux.intel.com] >> Sent: Friday, June 10, 2016 7:30 AM >> To: Gore, Tim; intel-gfx@lists.freedesktop.org >> Subject: Re: [PATCH v2] drm/i915/gen9: implement >> WaConextSwitchWithConcurrentTLBInvalidate >> >> On 09/06/2016 20:19, tim.gore@intel.com wrote: >>> From: Tim Gore <tim.gore@intel.com> >>> >>> This patch enables a workaround for a mid thread preemption issue >>> where a hardware timing problem can prevent the context restore from >>> happening, leading to a hang. >>> >>> v2: move to gen9_init_workarounds (Arun) >>> >>> Signed-off-by: Tim Gore <tim.gore@intel.com> >>> --- >>> drivers/gpu/drm/i915/i915_reg.h | 4 ++++ >>> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ >>> 2 files changed, 7 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h >>> b/drivers/gpu/drm/i915/i915_reg.h index 81d1896..2a6fc62 100644 >>> --- a/drivers/gpu/drm/i915/i915_reg.h >>> +++ b/drivers/gpu/drm/i915/i915_reg.h >>> @@ -1810,6 +1810,10 @@ enum skl_disp_power_wells { >>> #define GEN9_IZ_HASHING_MASK(slice) (0x3 << >> ((slice) * 2)) >>> #define GEN9_IZ_HASHING(slice, val) ((val) << >> ((slice) * 2)) >>> >>> +/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ >>> +#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) >>> +#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) >>> + >>> /* WaClearTdlStateAckDirtyBits */ >>> #define GEN8_STATE_ACK _MMIO(0x20F0) >>> #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) >>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c >>> b/drivers/gpu/drm/i915/intel_ringbuffer.c >>> index cf8d0bf..7c756ac 100644 >>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >>> @@ -1022,6 +1022,9 @@ static int gen9_init_workarounds(struct >> intel_engine_cs *engine) >>> if (ret) >>> return ret; >>> >>> + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ >>> + I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, >>> >> +_MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE) >> ); >>> + >> WA_SET_BIT_MASKED(GEN9_CSFE_CHICKEN1_RCS, >> GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); >> >> Please correct the spelling. >> We should try to keep WA regs in some order although it is not true for some >> of the existing ones but we should try to follow this rule for the new ones; >> HW whitelist registers are normally kept at the end. >> I think the correct place for this one is at the beginning of this function to >> maintain increasing order. >> >> regards >> Arun >> >> > Which spelling do you want corrected? WaConextSwitchWithConcurrentTLBInvalidate - two occurrences. regards Arun > > Tim >>> return 0; >>> } >>> >>> > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate 2016-06-10 8:38 ` Arun Siluvery @ 2016-06-10 8:51 ` Gore, Tim 0 siblings, 0 replies; 6+ messages in thread From: Gore, Tim @ 2016-06-10 8:51 UTC (permalink / raw) To: Arun Siluvery, intel-gfx@lists.freedesktop.org Tim Gore Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ > -----Original Message----- > From: Arun Siluvery [mailto:arun.siluvery@linux.intel.com] > Sent: Friday, June 10, 2016 9:38 AM > To: Gore, Tim; intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH v2] drm/i915/gen9: implement > WaConextSwitchWithConcurrentTLBInvalidate > > On 10/06/2016 12:16, Gore, Tim wrote: > > > > > > Tim Gore > > Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon > > SN3 1RJ > > > > > >> -----Original Message----- > >> From: Arun Siluvery [mailto:arun.siluvery@linux.intel.com] > >> Sent: Friday, June 10, 2016 7:30 AM > >> To: Gore, Tim; intel-gfx@lists.freedesktop.org > >> Subject: Re: [PATCH v2] drm/i915/gen9: implement > >> WaConextSwitchWithConcurrentTLBInvalidate > >> > >> On 09/06/2016 20:19, tim.gore@intel.com wrote: > >>> From: Tim Gore <tim.gore@intel.com> > >>> > >>> This patch enables a workaround for a mid thread preemption issue > >>> where a hardware timing problem can prevent the context restore from > >>> happening, leading to a hang. > >>> > >>> v2: move to gen9_init_workarounds (Arun) > >>> > >>> Signed-off-by: Tim Gore <tim.gore@intel.com> > >>> --- > >>> drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > >>> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ > >>> 2 files changed, 7 insertions(+) > >>> > >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h > >>> b/drivers/gpu/drm/i915/i915_reg.h index 81d1896..2a6fc62 100644 > >>> --- a/drivers/gpu/drm/i915/i915_reg.h > >>> +++ b/drivers/gpu/drm/i915/i915_reg.h > >>> @@ -1810,6 +1810,10 @@ enum skl_disp_power_wells { > >>> #define GEN9_IZ_HASHING_MASK(slice) (0x3 > << > >> ((slice) * 2)) > >>> #define GEN9_IZ_HASHING(slice, val) ((val) << > >> ((slice) * 2)) > >>> > >>> +/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ > >>> +#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) > >>> +#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) > >>> + > >>> /* WaClearTdlStateAckDirtyBits */ > >>> #define GEN8_STATE_ACK _MMIO(0x20F0) > >>> #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) > >>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > >>> b/drivers/gpu/drm/i915/intel_ringbuffer.c > >>> index cf8d0bf..7c756ac 100644 > >>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > >>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > >>> @@ -1022,6 +1022,9 @@ static int gen9_init_workarounds(struct > >> intel_engine_cs *engine) > >>> if (ret) > >>> return ret; > >>> > >>> + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ > >>> + I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, > >>> > >> > +_MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE) > >> ); > >>> + > >> WA_SET_BIT_MASKED(GEN9_CSFE_CHICKEN1_RCS, > >> GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); > >> > >> Please correct the spelling. > >> We should try to keep WA regs in some order although it is not true > >> for some of the existing ones but we should try to follow this rule > >> for the new ones; HW whitelist registers are normally kept at the end. > >> I think the correct place for this one is at the beginning of this > >> function to maintain increasing order. > >> > >> regards > >> Arun > >> > >> > > Which spelling do you want corrected? > > WaConextSwitchWithConcurrentTLBInvalidate - two occurrences. > > regards > Arun > As per my previous replies to Jani and you, WaConextSwitchWithConcurrentTLBInvalidate is copied directly from the documentation (bug report etc) and also from another implementation of this workaround. Actually, to be precise the spec has "WAConextSwitchWithConcurrentTLBInvalidate" (capitalised WA), but the bug report and other implementation use "WaConextSwitchWithConcurrentTLBInvalidate". I am not really comfortable with using a different spelling here, even if it is "correct". Seems like it could lead to confusion or at least trip up some script. Tim > > > > Tim > >>> return 0; > >>> } > >>> > >>> > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-06-10 8:51 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-06-09 14:49 [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate tim.gore 2016-06-09 15:15 ` ✗ Ro.CI.BAT: warning for drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate (rev2) Patchwork 2016-06-10 6:30 ` [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate Arun Siluvery 2016-06-10 6:46 ` Gore, Tim 2016-06-10 8:38 ` Arun Siluvery 2016-06-10 8:51 ` Gore, Tim
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