From: vladimir.murzin@arm.com (Vladimir Murzin)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: V7M: Add dsb before jumping in handler mode
Date: Wed, 15 Jun 2016 16:36:19 +0100 [thread overview]
Message-ID: <576175F3.5080306@arm.com> (raw)
In-Reply-To: <1465827171-15847-1-git-send-email-alexandre.torgue@st.com>
On 13/06/16 15:12, Alexandre TORGUE wrote:
> According to ARM AN321 (section 4.12):
>
> "If the vector table is in writable memory such as SRAM, either relocated
> by VTOR or a device dependent memory remapping mechanism, then
> architecturally a memory barrier instruction is required after the vector
> table entry is updated, and if the exception is to be activated
> immediately"
>
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
> diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
> index 7229d8d..2ddc435 100644
> --- a/arch/arm/mm/proc-v7m.S
> +++ b/arch/arm/mm/proc-v7m.S
> @@ -104,6 +104,7 @@ __v7m_setup:
> badr r1, 1f
> ldr r5, [r12, #11 * 4] @ read the SVC vector entry
> str r1, [r12, #11 * 4] @ write the temporary SVC vector entry
> + dsb
> mov r6, lr @ save LR
> ldr sp, =init_thread_union + THREAD_START_SP
> cpsie i
>
WARNING: multiple messages have this Message-ID (diff)
From: Vladimir Murzin <vladimir.murzin@arm.com>
To: Alexandre TORGUE <alexandre.torgue@st.com>,
Russell King <linux@armlinux.org.uk>,
Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
u.kleine-koenig@pengutronix.de,
Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: V7M: Add dsb before jumping in handler mode
Date: Wed, 15 Jun 2016 16:36:19 +0100 [thread overview]
Message-ID: <576175F3.5080306@arm.com> (raw)
In-Reply-To: <1465827171-15847-1-git-send-email-alexandre.torgue@st.com>
On 13/06/16 15:12, Alexandre TORGUE wrote:
> According to ARM AN321 (section 4.12):
>
> "If the vector table is in writable memory such as SRAM, either relocated
> by VTOR or a device dependent memory remapping mechanism, then
> architecturally a memory barrier instruction is required after the vector
> table entry is updated, and if the exception is to be activated
> immediately"
>
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
> diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
> index 7229d8d..2ddc435 100644
> --- a/arch/arm/mm/proc-v7m.S
> +++ b/arch/arm/mm/proc-v7m.S
> @@ -104,6 +104,7 @@ __v7m_setup:
> badr r1, 1f
> ldr r5, [r12, #11 * 4] @ read the SVC vector entry
> str r1, [r12, #11 * 4] @ write the temporary SVC vector entry
> + dsb
> mov r6, lr @ save LR
> ldr sp, =init_thread_union + THREAD_START_SP
> cpsie i
>
next prev parent reply other threads:[~2016-06-15 15:36 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-13 14:12 [PATCH] ARM: V7M: Add dsb before jumping in handler mode Alexandre TORGUE
2016-06-13 14:12 ` Alexandre TORGUE
2016-06-15 15:36 ` Vladimir Murzin [this message]
2016-06-15 15:36 ` Vladimir Murzin
2016-08-17 15:28 ` Vladimir Murzin
2016-08-17 15:28 ` Vladimir Murzin
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