From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Andrew Jones <drjones@redhat.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
Patch Tracking <patches@linaro.org>,
Shlomo Pongratz <shlomo.pongratz@huawei.com>,
Shlomo Pongratz <shlomopongratz@gmail.com>,
Pavel Fedin <p.fedin@samsung.com>,
Shannon Zhao <shannon.zhao@linaro.org>,
Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v3 00/20] GICv3 emulation
Date: Thu, 16 Jun 2016 10:17:52 +0800 [thread overview]
Message-ID: <57620C50.7060904@huawei.com> (raw)
In-Reply-To: <CAFEAcA_jZ9YVybZnkvU+LcUPXmB3b2iU67Sf8D4a8sJXpOgG2A@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1103 bytes --]
On 2016/6/15 18:10, Peter Maydell wrote:
> On 15 June 2016 at 11:06, Peter Maydell <peter.maydell@linaro.org> wrote:
>> > On 15 June 2016 at 10:20, Andrew Jones <drjones@redhat.com> wrote:
>>> >> There may be a bug in the freebsd kernel. Maybe they need the equivalent
>>> >> of Linux's 7c9b973061 "irqchip/gic-v3: Configure all interrupts as
>>> >> non-secure Group-1". You could add the hack back that was in the initial
>>> >> posting of this series to see if that "fixes" things.
>> >
>> > I agree it's possible this is a freebsd bug, but the hack patch
>> > won't help here because we're booting via EFI.
> A quick scan through http://fxr.watson.org/fxr/source/arm64/arm64/gic_v3.c
> doesn't seem to show it setting the IGROUPR registers anywhere,
> so it probably is a guest bug. (You can use "-d 'trace:gicv3*'" to
> enable the tracepoints for the GIC which would let you check whether
> the guest ever tries to write to the group config registers.)
I use "-d 'trace:gicv3*'" as you said. Attachment is the trace log. Look
like it doesn't write to GICD_IGROUPR registers.
Thanks,
--
Shannon
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: gicv3_trace.txt --]
[-- Type: text/plain; charset="gb18030"; name="gicv3_trace.txt", Size: 32894 bytes --]
3145@1466069678.305134:gicv3_dist_read GICv3 distributor read: offset 0x4 data 0x3780007 size 4 secure 0
3145@1466069678.305423:gicv3_dist_read GICv3 distributor read: offset 0x0 data 0x50 size 4 secure 0
3145@1466069678.305498:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.305506:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.305511:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.305516:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.305521:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.305526:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.305530:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.305534:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.305538:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.305542:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.305546:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.305550:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.305555:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.305558:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.305562:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.305566:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.305570:gicv3_dist_write GICv3 distributor write: offset 0x0 data 0x50 size 4 secure 0
3145@1466069678.307067:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069678.307078:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069678.307456:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.307467:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.307472:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10180 data 0x1 size 4 secure 0
3145@1466069678.307792:gicv3_dist_read GICv3 distributor read: offset 0x400 data 0x0 size 4 secure 0
3145@1466069678.307868:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.307874:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.307878:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.307882:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.307886:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.307890:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.307894:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.307897:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.307901:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.307905:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.307908:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.307912:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.307916:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.307920:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.307923:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.307927:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.307931:gicv3_dist_write GICv3 distributor write: offset 0x400 data 0x80 size 4 secure 0
3145@1466069678.308089:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069678.308096:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069678.308105:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308111:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308115:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10180 data 0x2 size 4 secure 0
3145@1466069678.308124:gicv3_dist_read GICv3 distributor read: offset 0x400 data 0x0 size 4 secure 0
3145@1466069678.308133:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308138:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308142:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308146:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308150:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308153:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308157:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308161:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308165:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308169:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308172:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308176:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308179:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308183:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308187:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308191:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308195:gicv3_dist_write GICv3 distributor write: offset 0x400 data 0x8000 size 4 secure 0
3145@1466069678.308208:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069678.308213:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069678.308223:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308228:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308231:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10180 data 0x4 size 4 secure 0
3145@1466069678.308240:gicv3_dist_read GICv3 distributor read: offset 0x400 data 0x0 size 4 secure 0
3145@1466069678.308249:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308254:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308258:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308261:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308265:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308269:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308273:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308277:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308280:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308284:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308288:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308292:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308295:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308299:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308303:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308306:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308310:gicv3_dist_write GICv3 distributor write: offset 0x400 data 0x800000 size 4 secure 0
3145@1466069678.308323:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069678.308329:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069678.308338:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308343:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308346:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10180 data 0x8 size 4 secure 0
3145@1466069678.308355:gicv3_dist_read GICv3 distributor read: offset 0x400 data 0x0 size 4 secure 0
3145@1466069678.308364:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308368:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308372:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308376:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308380:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308383:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308387:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308391:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308395:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308398:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308402:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308406:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308409:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308413:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308417:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308420:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308424:gicv3_dist_write GICv3 distributor write: offset 0x400 data 0x80000000 size 4 secure 0
3145@1466069678.308437:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069678.308442:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069678.308451:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308456:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308460:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10180 data 0x10 size 4 secure 0
3145@1466069678.308468:gicv3_dist_read GICv3 distributor read: offset 0x404 data 0x0 size 4 secure 0
3145@1466069678.308477:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308482:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308485:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308490:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308493:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308497:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308501:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308504:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308508:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308512:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308515:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308519:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308523:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308527:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308530:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308534:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308537:gicv3_dist_write GICv3 distributor write: offset 0x404 data 0x80 size 4 secure 0
3145@1466069678.308550:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069678.308556:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069678.308565:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308569:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308573:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10180 data 0x20 size 4 secure 0
3145@1466069678.308582:gicv3_dist_read GICv3 distributor read: offset 0x404 data 0x0 size 4 secure 0
3145@1466069678.308591:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308595:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308599:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308603:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308607:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308611:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308614:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308618:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308621:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308625:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308629:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308633:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308636:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308640:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308644:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308648:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308651:gicv3_dist_write GICv3 distributor write: offset 0x404 data 0x8000 size 4 secure 0
3145@1466069678.308664:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069678.308670:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069678.308679:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308684:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308687:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10180 data 0x40 size 4 secure 0
3145@1466069678.308696:gicv3_dist_read GICv3 distributor read: offset 0x404 data 0x0 size 4 secure 0
3145@1466069678.308705:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308710:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308714:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308717:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.308721:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.308725:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 03145@1466069678.319249:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319278:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319283:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319287:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319291:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319294:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319298:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319302:gicv3_dist_write GICv3 distributor write: offset 0x47c data 0x80000000 size 4 secure 0
3145@1466069678.319317:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069678.319322:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069678.319331:gicv3_redist_badwrite GICv3 redistributor 0 write: offset 0x10190 data 0x1 size 4 secure 0: error
3145@1466069678.319341:gicv3_dist_read GICv3 distributor read: offset 0x480 data 0x0 size 4 secure 0
3145@1466069678.319349:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319354:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319358:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319361:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319365:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319369:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319372:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319376:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319379:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319383:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319386:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319390:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319393:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319397:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319401:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319404:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319408:gicv3_dist_write GICv3 distributor write: offset 0x480 data 0x80 size 4 secure 0
3145@1466069678.319420:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069678.319426:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069678.319434:gicv3_redist_badwrite GICv3 redistributor 0 write: offset 0x10190 data 0x2 size 4 secure 0: error
3145@1466069678.319443:gicv3_dist_read GICv3 distributor read: offset 0x480 data 0x8000 size 4 secure 0
3145@1466069678.319452:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319456:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319460:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319464:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319467:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319471:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319474:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319478:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.319482:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.319485:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 03145@1466069678.331274:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331279:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331283:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331290:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331294:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331298:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331302:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331305:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331309:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331313:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331316:gicv3_dist_write GICv3 distributor write: offset 0x6140 data 0x80000000 size 4 secure 0
3145@1466069678.331326:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331330:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331334:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331338:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331341:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331345:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331349:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331352:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331356:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331360:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331363:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331367:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331370:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331374:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331378:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331381:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331385:gicv3_dist_write GICv3 distributor write: offset 0x6148 data 0x80000000 size 4 secure 0
3145@1466069678.331393:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331397:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331401:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331405:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331408:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331412:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331416:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331419:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331423:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331427:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331430:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331434:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331438:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331441:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331445:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331448:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331452:gicv3_dist_write GICv3 distributor write: offset 0x6150 data 0x80000000 size 4 secure 0
3145@1466069678.331460:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331464:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331468:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331471:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331475:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331479:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331482:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331486:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331489:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331493:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331496:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331500:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331503:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331507:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331510:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331514:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331518:gicv3_dist_write GICv3 distributor write: offset 0x6158 data 0x80000000 size 4 secure 0
3145@1466069678.331525:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331530:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331533:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331537:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331540:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331544:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331548:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331551:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331555:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331558:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331562:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331565:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331569:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331572:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331576:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331579:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331583:gicv3_dist_write GICv3 distributor write: offset 0x6160 data 0x80000000 size 4 secure 0
3145@1466069678.331591:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331595:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331599:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331602:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.331606:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.331609:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 03145@1466069678.343357:gicv3_dist_read GICv3 distributor read: offset 0x0 data 0x50 size 4 secure 0
3145@1466069678.343375:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069678.343380:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.343384:gicv3_cpuif_update GICv3 CPU i/f 1 HPPI update: irq 0 group 0 prio 255
3145@1466069678.343388:gicv3_cpuif_set_irqs GICv3 CPU i/f 1 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.343392:gicv3_cpuif_update GICv3 CPU i/f 2 HPPI update: irq 0 group 0 prio 255
3145@1466069678.343396:gicv3_cpuif_set_irqs GICv3 CPU i/f 2 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.343399:gicv3_cpuif_update GICv3 CPU i/f 3 HPPI update: irq 0 group 0 prio 255
3145@1466069678.343403:gicv3_cpuif_set_irqs GICv3 CPU i/f 3 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.343407:gicv3_cpuif_update GICv3 CPU i/f 4 HPPI update: irq 0 group 0 prio 255
3145@1466069678.343411:gicv3_cpuif_set_irqs GICv3 CPU i/f 4 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.343414:gicv3_cpuif_update GICv3 CPU i/f 5 HPPI update: irq 0 group 0 prio 255
3145@1466069678.343418:gicv3_cpuif_set_irqs GICv3 CPU i/f 5 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.343421:gicv3_cpuif_update GICv3 CPU i/f 6 HPPI update: irq 0 group 0 prio 255
3145@1466069678.343425:gicv3_cpuif_set_irqs GICv3 CPU i/f 6 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.343429:gicv3_cpuif_update GICv3 CPU i/f 7 HPPI update: irq 0 group 0 prio 255
3145@1466069678.343432:gicv3_cpuif_set_irqs GICv3 CPU i/f 7 HPPI update: setting FIQ 0 IRQ 0
3145@1466069678.343436:gicv3_dist_write GICv3 distributor write: offset 0x0 data 0x52 size 4 secure 0
3145@1466069679.735047:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069679.735069:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069679.735273:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069679.735282:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069679.735288:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10100 data 0x8000000 size 4 secure 0
3145@1466069679.735771:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069679.735779:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069679.735789:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069679.735795:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069679.735799:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10100 data 0x4000000 size 4 secure 0
3145@1466069679.736103:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069679.736110:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069679.736120:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069679.736126:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069679.736130:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10100 data 0x20000000 size 4 secure 0
3145@1466069679.736429:gicv3_redist_read GICv3 redistributor 0 read: offset 0x8 data 0x1000000 size 4 secure 0
3145@1466069679.736437:gicv3_redist_read GICv3 redistributor 0 read: offset 0xc data 0x0 size 4 secure 0
3145@1466069679.736446:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069679.736452:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
3145@1466069679.736455:gicv3_redist_write GICv3 redistributor 0 write: offset 0x10100 data 0x40000000 size 4 secure 0
3145@1466069679.747805:gicv3_redist_set_irq GICv3 redistributor 0 interrupt 27 level changed to 1
3145@1466069679.747820:gicv3_cpuif_update GICv3 CPU i/f 0 HPPI update: irq 0 group 0 prio 255
3145@1466069679.747825:gicv3_cpuif_set_irqs GICv3 CPU i/f 0 HPPI update: setting FIQ 0 IRQ 0
next prev parent reply other threads:[~2016-06-16 2:18 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-14 14:38 [Qemu-devel] [PATCH v3 00/20] GICv3 emulation Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 01/20] migration: Define VMSTATE_UINT64_2DARRAY Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 02/20] bitops.h: Implement half-shuffle and half-unshuffle ops Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 03/20] target-arm: Define new arm_is_el3_or_mon() function Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 04/20] target-arm: Provide hook to tell GICv3 about changes of security state Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 05/20] target-arm: Add mp-affinity property for ARM CPU class Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 06/20] hw/intc/arm_gicv3: Add state information Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 07/20] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 08/20] hw/intc/arm_gicv3: Add vmstate descriptors Peter Maydell
2016-06-15 2:30 ` Shannon Zhao
2016-06-16 2:12 ` Shannon Zhao
2016-06-16 14:23 ` Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 09/20] hw/intc/arm_gicv3: ARM GICv3 device framework Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 10/20] hw/intc/arm_gicv3: Implement functions to identify next pending irq Peter Maydell
2016-06-15 2:35 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 11/20] hw/intc/arm_gicv3: Implement GICv3 distributor registers Peter Maydell
2016-06-15 2:36 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 12/20] hw/intc/arm_gicv3: Implement GICv3 redistributor registers Peter Maydell
2016-06-15 2:42 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 13/20] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 14/20] hw/intc/arm_gicv3: Implement gicv3_set_irq() Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 15/20] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers Peter Maydell
2016-06-15 2:45 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 16/20] hw/intc/arm_gicv3: Implement gicv3_cpuif_update() Peter Maydell
2016-06-15 2:47 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 17/20] hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 18/20] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers Peter Maydell
2016-06-15 3:15 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 19/20] target-arm/machine.c: Allow user to request GICv3 emulation Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 20/20] target-arm/monitor.c: Advertise emulated GICv3 in capabilities Peter Maydell
2016-06-15 2:52 ` [Qemu-devel] [PATCH v3 00/20] GICv3 emulation Shannon Zhao
2016-06-15 8:53 ` Shannon Zhao
2016-06-15 9:20 ` Andrew Jones
2016-06-15 10:06 ` Peter Maydell
2016-06-15 10:10 ` Peter Maydell
2016-06-15 14:02 ` Shannon Zhao
2016-06-15 14:06 ` Peter Maydell
2016-06-16 2:17 ` Shannon Zhao [this message]
2016-06-22 18:09 ` Ed Maste
2016-06-22 20:53 ` Peter Maydell
2016-06-22 21:45 ` Ed Maste
2016-06-22 21:56 ` Peter Maydell
2016-06-23 1:42 ` Shannon Zhao
2016-06-23 11:36 ` Laszlo Ersek
2016-06-23 12:07 ` Andrew Jones
2016-06-23 14:18 ` Ed Maste
2016-06-23 14:52 ` Laszlo Ersek
2016-06-23 20:03 ` Ard Biesheuvel
2016-06-23 20:33 ` Peter Maydell
2016-06-24 8:16 ` Ard Biesheuvel
2016-06-21 14:45 ` Andrew Jones
2016-06-21 14:55 ` Peter Maydell
2016-06-21 15:12 ` Andrew Jones
2016-06-21 17:15 ` Andrew Jones
2016-06-21 17:17 ` Peter Maydell
2016-06-21 17:18 ` Andrew Jones
2016-06-21 17:21 ` Peter Maydell
2016-06-21 19:45 ` Laszlo Ersek
2016-06-21 19:53 ` Peter Maydell
2016-06-22 1:42 ` Shannon Zhao
2016-06-22 7:43 ` Andrew Jones
2016-06-22 8:27 ` Shannon Zhao
2016-06-22 9:09 ` Andrew Jones
2016-06-22 15:23 ` Laszlo Ersek
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=57620C50.7060904@huawei.com \
--to=zhaoshenglong@huawei.com \
--cc=christoffer.dall@linaro.org \
--cc=drjones@redhat.com \
--cc=p.fedin@samsung.com \
--cc=patches@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=shannon.zhao@linaro.org \
--cc=shlomo.pongratz@huawei.com \
--cc=shlomopongratz@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.