From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Andrew Jones <drjones@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Laszlo Ersek <lersek@redhat.com>,
Patch Tracking <patches@linaro.org>,
Shlomo Pongratz <shlomo.pongratz@huawei.com>,
Shlomo Pongratz <shlomopongratz@gmail.com>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Pavel Fedin <p.fedin@samsung.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Shannon Zhao <shannon.zhao@linaro.org>,
Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v3 00/20] GICv3 emulation
Date: Wed, 22 Jun 2016 16:27:35 +0800 [thread overview]
Message-ID: <576A4BF7.4050501@huawei.com> (raw)
In-Reply-To: <20160622074342.navvazli3ekal3sf@hawk.localdomain>
On 2016/6/22 15:43, Andrew Jones wrote:
> On Wed, Jun 22, 2016 at 09:42:29AM +0800, Shannon Zhao wrote:
>> >
>> >
>> > On 2016/6/22 3:53, Peter Maydell wrote:
>>> > > On 21 June 2016 at 20:45, Laszlo Ersek <lersek@redhat.com> wrote:
>>>>> > >> > On 06/21/16 19:21, Peter Maydell wrote:
>>>>>>> > >>> >> and add a note I forgot to mention: my primary hypothesis is that
>>>>>>> > >>> >> the problem here is "guest does not write to the GICD_IGROUPR and
>>>>>>> > >>> >> GICR_IGROUPR registers to program the interrupts it's using as
>>>>>>> > >>> >> group 1, but still expects to get IRQs rather than FIQs".
>>>>> > >> >
>>>>> > >> > ... and it (or whatever else is the root cause) seems to manifest in
>>>>> > >> > either the Stall() UEFI boot service, or in UEFI timer events. (This
>>>>> > >> > seems to follow from the last debug log entry from Shannon:
>>>>> > >> >
>>>>> > >> > [Bds]BdsWait(3)..Zzzz...
>>>>> > >> > )
>>>>> > >> >
>>>>> > >> > ... Just to make it clear: does it reproduce with KVM? Or is that
>>>>> > >> > untested perhaps (due to lack of GICv3 hardware e.g.)?
>>> > > Upthread Shannon said it worked with KVM enabled. Note that
>>> > > KVM's GICv3 emulation is incorrect in that it does not support
>>> > > interrupt groups, so all interrupt groups are Group 1 and
>>> > > generate IRQ even if the guest doesn't do anything to
>>> > > configure them.
>> > It does work with KVM enabled. It also works with UEFI and the upstream
>> > linux kernel while it doesn't work with UEFI and a FreeBSD guest since
>> > the FreeBSD doesn't correctly set the IGROUPR, I think.
> Doesn't appear to be FreeBSD specific, as I'm using a Linux kernel and
> can reproduce. Besides, it doesn't even make it to grub.
>
>> >
>> > I can't find the commit ID of the UEFI I use but I used the upsream
>> > codes of June 15.
>> > Andrew, I suggest you use the QEMU mainline which includes the GICv3
>> > emulation and the guest kernel with the commit 7c9b973061.
> Yeah, I hadn't noticed that gicv3 made it to mainline. I've switched
> to that now. My guest kernel does have 7c9b973061 (I backported it to
> the RHELSA kernel)
I just used a new UEFI binary which is built on 8f88f02 and the upstream
linux kernel. It boots as well.
Could you try the upstream linux kernel?
Thanks,
--
Shannon
next prev parent reply other threads:[~2016-06-22 8:28 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-14 14:38 [Qemu-devel] [PATCH v3 00/20] GICv3 emulation Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 01/20] migration: Define VMSTATE_UINT64_2DARRAY Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 02/20] bitops.h: Implement half-shuffle and half-unshuffle ops Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 03/20] target-arm: Define new arm_is_el3_or_mon() function Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 04/20] target-arm: Provide hook to tell GICv3 about changes of security state Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 05/20] target-arm: Add mp-affinity property for ARM CPU class Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 06/20] hw/intc/arm_gicv3: Add state information Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 07/20] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 08/20] hw/intc/arm_gicv3: Add vmstate descriptors Peter Maydell
2016-06-15 2:30 ` Shannon Zhao
2016-06-16 2:12 ` Shannon Zhao
2016-06-16 14:23 ` Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 09/20] hw/intc/arm_gicv3: ARM GICv3 device framework Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 10/20] hw/intc/arm_gicv3: Implement functions to identify next pending irq Peter Maydell
2016-06-15 2:35 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 11/20] hw/intc/arm_gicv3: Implement GICv3 distributor registers Peter Maydell
2016-06-15 2:36 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 12/20] hw/intc/arm_gicv3: Implement GICv3 redistributor registers Peter Maydell
2016-06-15 2:42 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 13/20] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 14/20] hw/intc/arm_gicv3: Implement gicv3_set_irq() Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 15/20] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers Peter Maydell
2016-06-15 2:45 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 16/20] hw/intc/arm_gicv3: Implement gicv3_cpuif_update() Peter Maydell
2016-06-15 2:47 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 17/20] hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 18/20] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers Peter Maydell
2016-06-15 3:15 ` Shannon Zhao
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 19/20] target-arm/machine.c: Allow user to request GICv3 emulation Peter Maydell
2016-06-14 14:38 ` [Qemu-devel] [PATCH v3 20/20] target-arm/monitor.c: Advertise emulated GICv3 in capabilities Peter Maydell
2016-06-15 2:52 ` [Qemu-devel] [PATCH v3 00/20] GICv3 emulation Shannon Zhao
2016-06-15 8:53 ` Shannon Zhao
2016-06-15 9:20 ` Andrew Jones
2016-06-15 10:06 ` Peter Maydell
2016-06-15 10:10 ` Peter Maydell
2016-06-15 14:02 ` Shannon Zhao
2016-06-15 14:06 ` Peter Maydell
2016-06-16 2:17 ` Shannon Zhao
2016-06-22 18:09 ` Ed Maste
2016-06-22 20:53 ` Peter Maydell
2016-06-22 21:45 ` Ed Maste
2016-06-22 21:56 ` Peter Maydell
2016-06-23 1:42 ` Shannon Zhao
2016-06-23 11:36 ` Laszlo Ersek
2016-06-23 12:07 ` Andrew Jones
2016-06-23 14:18 ` Ed Maste
2016-06-23 14:52 ` Laszlo Ersek
2016-06-23 20:03 ` Ard Biesheuvel
2016-06-23 20:33 ` Peter Maydell
2016-06-24 8:16 ` Ard Biesheuvel
2016-06-21 14:45 ` Andrew Jones
2016-06-21 14:55 ` Peter Maydell
2016-06-21 15:12 ` Andrew Jones
2016-06-21 17:15 ` Andrew Jones
2016-06-21 17:17 ` Peter Maydell
2016-06-21 17:18 ` Andrew Jones
2016-06-21 17:21 ` Peter Maydell
2016-06-21 19:45 ` Laszlo Ersek
2016-06-21 19:53 ` Peter Maydell
2016-06-22 1:42 ` Shannon Zhao
2016-06-22 7:43 ` Andrew Jones
2016-06-22 8:27 ` Shannon Zhao [this message]
2016-06-22 9:09 ` Andrew Jones
2016-06-22 15:23 ` Laszlo Ersek
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